1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef __INTEL_FDI_REGS_H__
7 #define __INTEL_FDI_REGS_H__
8 
9 #include "intel_display_reg_defs.h"
10 
11 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
12 #define  FDI_PLL_FB_CLOCK_MASK  0xff
13 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
14 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
15 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
16 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
17 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
18 
19 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
20 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
21 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
22 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
23 
24 #define _FDI_RXA_CHICKEN        0xc200c
25 #define _FDI_RXB_CHICKEN        0xc2010
26 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
27 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
28 #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
29 
30 /* CPU: FDI_TX */
31 #define _FDI_TXA_CTL            0x60100
32 #define _FDI_TXB_CTL            0x61100
33 #define FDI_TX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
34 #define  FDI_TX_DISABLE         (0 << 31)
35 #define  FDI_TX_ENABLE          (1 << 31)
36 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
37 #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
38 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
39 #define  FDI_LINK_TRAIN_NONE            (3 << 28)
40 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
41 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
42 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
43 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
44 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
45 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
46 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
47 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
48 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
49    SNB has different settings. */
50 /* SNB A-stepping */
51 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
52 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
53 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
54 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
55 /* SNB B-stepping */
56 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
57 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
58 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
59 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
60 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
61 #define  FDI_DP_PORT_WIDTH_SHIFT		19
62 #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
63 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
64 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
65 /* Ironlake: hardwired to 1 */
66 #define  FDI_TX_PLL_ENABLE              (1 << 14)
67 
68 /* Ivybridge has different bits for lolz */
69 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
70 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
71 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
72 #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
73 
74 /* both Tx and Rx */
75 #define  FDI_COMPOSITE_SYNC		(1 << 11)
76 #define  FDI_LINK_TRAIN_AUTO		(1 << 10)
77 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
78 #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
79 
80 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
81 #define _FDI_RXA_CTL             0xf000c
82 #define _FDI_RXB_CTL             0xf100c
83 #define FDI_RX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
84 #define  FDI_RX_ENABLE          (1 << 31)
85 /* train, dp width same as FDI_TX */
86 #define  FDI_FS_ERRC_ENABLE		(1 << 27)
87 #define  FDI_FE_ERRC_ENABLE		(1 << 26)
88 #define  FDI_RX_POLARITY_REVERSED_LPT	(1 << 16)
89 #define  FDI_8BPC                       (0 << 16)
90 #define  FDI_10BPC                      (1 << 16)
91 #define  FDI_6BPC                       (2 << 16)
92 #define  FDI_12BPC                      (3 << 16)
93 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
94 #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
95 #define  FDI_RX_PLL_ENABLE              (1 << 13)
96 #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
97 #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
98 #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
99 #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
100 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
101 #define  FDI_PCDCLK	                (1 << 4)
102 /* CPT */
103 #define  FDI_AUTO_TRAINING			(1 << 10)
104 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
105 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1 << 8)
106 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
107 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
108 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
109 
110 #define _FDI_RXA_MISC			0xf0010
111 #define _FDI_RXB_MISC			0xf1010
112 #define  FDI_RX_PWRDN_LANE1_MASK	(3 << 26)
113 #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
114 #define  FDI_RX_PWRDN_LANE0_MASK	(3 << 24)
115 #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
116 #define  FDI_RX_TP1_TO_TP2_48		(2 << 20)
117 #define  FDI_RX_TP1_TO_TP2_64		(3 << 20)
118 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
119 #define FDI_RX_MISC(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
120 
121 #define _FDI_RXA_TUSIZE1        0xf0030
122 #define _FDI_RXA_TUSIZE2        0xf0038
123 #define _FDI_RXB_TUSIZE1        0xf1030
124 #define _FDI_RXB_TUSIZE2        0xf1038
125 #define FDI_RX_TUSIZE1(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
126 #define FDI_RX_TUSIZE2(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
127 
128 /* FDI_RX interrupt register format */
129 #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
130 #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
131 #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
132 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
133 #define FDI_RX_FS_CODE_ERR              (1 << 6)
134 #define FDI_RX_FE_CODE_ERR              (1 << 5)
135 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
136 #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
137 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
138 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
139 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
140 
141 #define _FDI_RXA_IIR            0xf0014
142 #define _FDI_RXA_IMR            0xf0018
143 #define _FDI_RXB_IIR            0xf1014
144 #define _FDI_RXB_IMR            0xf1018
145 #define FDI_RX_IIR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
146 #define FDI_RX_IMR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
147 
148 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
149 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
150 
151 #endif /* __INTEL_FDI_REGS_H__ */
152