Searched defs:_DIG_TRANSMITTER_INFO_HEADER_V3_2 (Results 1 – 2 of 2) sorted by relevance
7306 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ struct7307 ATOM_COMMON_TABLE_HEADER sHeader; 7308 … // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7309 … // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7310 …offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range7311 …yPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7312 …T usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings7313 …egListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7314 …sDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8580 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ struct8581 ATOM_COMMON_TABLE_HEADER sHeader;8582 … // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock8583 … // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info8584 …offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range8585 …hyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info8586 …T usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings8587 …RegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info8588 …sDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings