1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
3 #define _ASM_MICROBLAZE_PCI_BRIDGE_H
4 #ifdef __KERNEL__
5 /*
6  */
7 #include <linux/pci.h>
8 #include <linux/list.h>
9 #include <linux/ioport.h>
10 
11 struct device_node;
12 
13 #ifdef CONFIG_PCI
14 extern struct list_head hose_list;
15 extern int pcibios_vaddr_is_ioport(void __iomem *address);
16 #else
pcibios_vaddr_is_ioport(void __iomem * address)17 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
18 {
19 	return 0;
20 }
21 #endif
22 
23 /*
24  * Structure of a PCI controller (host bridge)
25  */
26 struct pci_controller {
27 	struct pci_bus *bus;
28 	struct list_head list_node;
29 
30 	void __iomem *io_base_virt;
31 
32 	/* Currently, we limit ourselves to 1 IO range and 3 mem
33 	 * ranges since the common pci_bus structure can't handle more
34 	 */
35 	struct resource io_resource;
36 };
37 
38 #ifdef CONFIG_PCI
isa_vaddr_is_ioport(void __iomem * address)39 static inline int isa_vaddr_is_ioport(void __iomem *address)
40 {
41 	/* No specific ISA handling on ppc32 at this stage, it
42 	 * all goes through PCI
43 	 */
44 	return 0;
45 }
46 #endif /* CONFIG_PCI */
47 
48 #endif	/* __KERNEL__ */
49 #endif	/* _ASM_MICROBLAZE_PCI_BRIDGE_H */
50