xref: /openbmc/u-boot/arch/sh/include/asm/cpu_sh4.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4  */
5 
6 #ifndef _ASM_CPU_SH4_H_
7 #define _ASM_CPU_SH4_H_
8 
9 /* cache control */
10 #define CCR_CACHE_STOP   0x00000808
11 #define CCR_CACHE_ENABLE 0x00000101
12 #define CCR_CACHE_ICI    0x00000800
13 
14 #define CACHE_OC_ADDRESS_ARRAY	0xf4000000
15 
16 #if defined (CONFIG_CPU_SH7750) || \
17 	defined(CONFIG_CPU_SH7751)
18 #define CACHE_OC_WAY_SHIFT	14
19 #define CACHE_OC_NUM_ENTRIES	512
20 #else
21 #define CACHE_OC_WAY_SHIFT	13
22 #define CACHE_OC_NUM_ENTRIES	256
23 #endif
24 #define CACHE_OC_ENTRY_SHIFT	5
25 
26 #if defined (CONFIG_CPU_SH7750) || \
27 	defined(CONFIG_CPU_SH7751)
28 # include <asm/cpu_sh7750.h>
29 #elif defined (CONFIG_CPU_SH7722)
30 # include <asm/cpu_sh7722.h>
31 #elif defined (CONFIG_CPU_SH7723)
32 # include <asm/cpu_sh7723.h>
33 #elif defined (CONFIG_CPU_SH7724)
34 # include <asm/cpu_sh7724.h>
35 #elif defined (CONFIG_CPU_SH7734)
36 # include <asm/cpu_sh7734.h>
37 #elif defined (CONFIG_CPU_SH7752)
38 # include <asm/cpu_sh7752.h>
39 #elif defined (CONFIG_CPU_SH7753)
40 # include <asm/cpu_sh7753.h>
41 #elif defined (CONFIG_CPU_SH7757)
42 # include <asm/cpu_sh7757.h>
43 #elif defined (CONFIG_CPU_SH7763)
44 # include <asm/cpu_sh7763.h>
45 #elif defined (CONFIG_CPU_SH7780)
46 # include <asm/cpu_sh7780.h>
47 #elif defined (CONFIG_CPU_SH7785)
48 # include <asm/cpu_sh7785.h>
49 #else
50 # error "Unknown SH4 variant"
51 #endif
52 
53 #if defined(CONFIG_SH_32BIT)
54 #define PMB_ADDR_ARRAY		0xf6100000
55 #define PMB_ADDR_ENTRY		8
56 #define PMB_VPN			24
57 
58 #define PMB_DATA_ARRAY		0xf7100000
59 #define PMB_DATA_ENTRY		8
60 #define PMB_PPN			24
61 #define PMB_UB			9		/* Buffered write */
62 #define PMB_V			8		/* Valid */
63 #define PMB_SZ1			7		/* Page size (upper bit) */
64 #define PMB_SZ0			4		/* Page size (lower bit) */
65 #define PMB_C			3		/* Cacheability */
66 #define PMB_WT			0		/* Write-through */
67 
68 #define PMB_ADDR_BASE(entry)	(PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
69 #define PMB_DATA_BASE(entry)	(PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
70 #define mk_pmb_addr_val(vpn)	((vpn << PMB_VPN))
71 #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt)	\
72 				((ppn << PMB_PPN) | (ub << PMB_UB) | \
73 				 (v << PMB_V) | (sz1 << PMB_SZ1) | \
74 				 (sz0 << PMB_SZ0) | (c << PMB_C) | \
75 				 (wt << PMB_WT))
76 #endif
77 
78 #endif	/* _ASM_CPU_SH4_H_ */
79