1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #ifndef _ASM_ARCH_SYS_PROTO_H 8 #define _ASM_ARCH_SYS_PROTO_H 9 10 #define PAYLOAD_ARG_CNT 5 11 12 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF 13 #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D 14 #define KEY_PTR_LEN 32 15 16 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 17 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2 18 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 19 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 20 #define ZYNQMP_FPGA_BIT_NS 5 21 22 #define ZYNQMP_FPGA_AUTH_DDR 1 23 24 #define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 25 26 #define ZYNQMP_PM_VERSION_MAJOR 1 27 #define ZYNQMP_PM_VERSION_MINOR 0 28 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 29 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF 30 31 #define ZYNQMP_PM_VERSION \ 32 ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ 33 ZYNQMP_PM_VERSION_MINOR) 34 35 #define ZYNQMP_PM_VERSION_INVALID ~0 36 37 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) 38 39 enum { 40 IDCODE, 41 VERSION, 42 IDCODE2, 43 }; 44 45 enum { 46 ZYNQMP_SILICON_V1, 47 ZYNQMP_SILICON_V2, 48 ZYNQMP_SILICON_V3, 49 ZYNQMP_SILICON_V4, 50 }; 51 52 enum { 53 TCM_LOCK, 54 TCM_SPLIT, 55 }; 56 57 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); 58 unsigned int zynqmp_get_silicon_version(void); 59 60 void handoff_setup(void); 61 62 unsigned int zynqmp_pmufw_version(void); 63 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); 64 int zynqmp_mmio_read(const u32 address, u32 *value); 65 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, 66 u32 *ret_payload); 67 68 void initialize_tcm(bool mode); 69 void mem_map_fill(void); 70 int chip_id(unsigned char id); 71 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) 72 void tcm_init(u8 mode); 73 #endif 74 75 #endif /* _ASM_ARCH_SYS_PROTO_H */ 76