1 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
2  *
3  * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
4  *
5  * This program is dual-licensed; you may select either version 2 of
6  * the GNU General Public License ("GPL") or BSD license ("BSD").
7  *
8  * This Synopsys DWC XLGMAC software driver and associated documentation
9  * (hereinafter the "Software") is an unsupported proprietary work of
10  * Synopsys, Inc. unless otherwise expressly agreed to in writing between
11  * Synopsys and you. The Software IS NOT an item of Licensed Software or a
12  * Licensed Product under any End User Software License Agreement or
13  * Agreement for Licensed Products with Synopsys or any supplement thereto.
14  * Synopsys is a registered trademark of Synopsys, Inc. Other names included
15  * in the SOFTWARE may be the trademarks of their respective owners.
16  */
17 
18 #ifndef __DWC_XLGMAC_H__
19 #define __DWC_XLGMAC_H__
20 
21 #include <linux/dma-mapping.h>
22 #include <linux/netdevice.h>
23 #include <linux/workqueue.h>
24 #include <linux/phy.h>
25 #include <linux/if_vlan.h>
26 #include <linux/bitops.h>
27 #include <linux/timecounter.h>
28 
29 #define XLGMAC_DRV_NAME			"dwc-xlgmac"
30 #define XLGMAC_DRV_VERSION		"1.0.0"
31 #define XLGMAC_DRV_DESC			"Synopsys DWC XLGMAC Driver"
32 
33 /* Descriptor related parameters */
34 #define XLGMAC_TX_DESC_CNT		1024
35 #define XLGMAC_TX_DESC_MIN_FREE		(XLGMAC_TX_DESC_CNT >> 3)
36 #define XLGMAC_TX_DESC_MAX_PROC		(XLGMAC_TX_DESC_CNT >> 1)
37 #define XLGMAC_RX_DESC_CNT		1024
38 #define XLGMAC_RX_DESC_MAX_DIRTY	(XLGMAC_RX_DESC_CNT >> 3)
39 
40 /* Descriptors required for maximum contiguous TSO/GSO packet */
41 #define XLGMAC_TX_MAX_SPLIT	\
42 	((GSO_LEGACY_MAX_SIZE / XLGMAC_TX_MAX_BUF_SIZE) + 1)
43 
44 /* Maximum possible descriptors needed for a SKB */
45 #define XLGMAC_TX_MAX_DESC_NR	(MAX_SKB_FRAGS + XLGMAC_TX_MAX_SPLIT + 2)
46 
47 #define XLGMAC_TX_MAX_BUF_SIZE	(0x3fff & ~(64 - 1))
48 #define XLGMAC_RX_MIN_BUF_SIZE	(ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
49 #define XLGMAC_RX_BUF_ALIGN	64
50 
51 /* Maximum Size for Splitting the Header Data
52  * Keep in sync with SKB_ALLOC_SIZE
53  * 3'b000: 64 bytes, 3'b001: 128 bytes
54  * 3'b010: 256 bytes, 3'b011: 512 bytes
55  * 3'b100: 1023 bytes ,   3'b101'3'b111: Reserved
56  */
57 #define XLGMAC_SPH_HDSMS_SIZE		3
58 #define XLGMAC_SKB_ALLOC_SIZE		512
59 
60 #define XLGMAC_MAX_FIFO			81920
61 
62 #define XLGMAC_MAX_DMA_CHANNELS		16
63 #define XLGMAC_DMA_STOP_TIMEOUT		5
64 #define XLGMAC_DMA_INTERRUPT_MASK	0x31c7
65 
66 /* Default coalescing parameters */
67 #define XLGMAC_INIT_DMA_TX_USECS	1000
68 #define XLGMAC_INIT_DMA_TX_FRAMES	25
69 #define XLGMAC_INIT_DMA_RX_USECS	30
70 #define XLGMAC_INIT_DMA_RX_FRAMES	25
71 #define XLGMAC_MAX_DMA_RIWT		0xff
72 #define XLGMAC_MIN_DMA_RIWT		0x01
73 
74 /* Flow control queue count */
75 #define XLGMAC_MAX_FLOW_CONTROL_QUEUES	8
76 
77 /* System clock is 125 MHz */
78 #define XLGMAC_SYSCLOCK			125000000
79 
80 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
81 #define XLGMAC_MAC_HASH_TABLE_SIZE	8
82 
83 /* Receive Side Scaling */
84 #define XLGMAC_RSS_HASH_KEY_SIZE	40
85 #define XLGMAC_RSS_MAX_TABLE_SIZE	256
86 #define XLGMAC_RSS_LOOKUP_TABLE_TYPE	0
87 #define XLGMAC_RSS_HASH_KEY_TYPE	1
88 
89 #define XLGMAC_STD_PACKET_MTU		1500
90 #define XLGMAC_JUMBO_PACKET_MTU		9000
91 
92 /* Helper macro for descriptor handling
93  *  Always use XLGMAC_GET_DESC_DATA to access the descriptor data
94  */
95 #define XLGMAC_GET_DESC_DATA(ring, idx) ({				\
96 	typeof(ring) _ring = (ring);					\
97 	((_ring)->desc_data_head +					\
98 	 ((idx) & ((_ring)->dma_desc_count - 1)));			\
99 })
100 
101 #define XLGMAC_GET_REG_BITS(var, pos, len) ({				\
102 	typeof(pos) _pos = (pos);					\
103 	typeof(len) _len = (len);					\
104 	((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);		\
105 })
106 
107 #define XLGMAC_GET_REG_BITS_LE(var, pos, len) ({			\
108 	typeof(pos) _pos = (pos);					\
109 	typeof(len) _len = (len);					\
110 	typeof(var) _var = le32_to_cpu((var));				\
111 	((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);		\
112 })
113 
114 #define XLGMAC_SET_REG_BITS(var, pos, len, val) ({			\
115 	typeof(var) _var = (var);					\
116 	typeof(pos) _pos = (pos);					\
117 	typeof(len) _len = (len);					\
118 	typeof(val) _val = (val);					\
119 	_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);		\
120 	_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;		\
121 })
122 
123 #define XLGMAC_SET_REG_BITS_LE(var, pos, len, val) ({			\
124 	typeof(var) _var = (var);					\
125 	typeof(pos) _pos = (pos);					\
126 	typeof(len) _len = (len);					\
127 	typeof(val) _val = (val);					\
128 	_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);		\
129 	_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;		\
130 	cpu_to_le32(_var);						\
131 })
132 
133 struct xlgmac_pdata;
134 
135 enum xlgmac_int {
136 	XLGMAC_INT_DMA_CH_SR_TI,
137 	XLGMAC_INT_DMA_CH_SR_TPS,
138 	XLGMAC_INT_DMA_CH_SR_TBU,
139 	XLGMAC_INT_DMA_CH_SR_RI,
140 	XLGMAC_INT_DMA_CH_SR_RBU,
141 	XLGMAC_INT_DMA_CH_SR_RPS,
142 	XLGMAC_INT_DMA_CH_SR_TI_RI,
143 	XLGMAC_INT_DMA_CH_SR_FBE,
144 	XLGMAC_INT_DMA_ALL,
145 };
146 
147 struct xlgmac_stats {
148 	/* MMC TX counters */
149 	u64 txoctetcount_gb;
150 	u64 txframecount_gb;
151 	u64 txbroadcastframes_g;
152 	u64 txmulticastframes_g;
153 	u64 tx64octets_gb;
154 	u64 tx65to127octets_gb;
155 	u64 tx128to255octets_gb;
156 	u64 tx256to511octets_gb;
157 	u64 tx512to1023octets_gb;
158 	u64 tx1024tomaxoctets_gb;
159 	u64 txunicastframes_gb;
160 	u64 txmulticastframes_gb;
161 	u64 txbroadcastframes_gb;
162 	u64 txunderflowerror;
163 	u64 txoctetcount_g;
164 	u64 txframecount_g;
165 	u64 txpauseframes;
166 	u64 txvlanframes_g;
167 
168 	/* MMC RX counters */
169 	u64 rxframecount_gb;
170 	u64 rxoctetcount_gb;
171 	u64 rxoctetcount_g;
172 	u64 rxbroadcastframes_g;
173 	u64 rxmulticastframes_g;
174 	u64 rxcrcerror;
175 	u64 rxrunterror;
176 	u64 rxjabbererror;
177 	u64 rxundersize_g;
178 	u64 rxoversize_g;
179 	u64 rx64octets_gb;
180 	u64 rx65to127octets_gb;
181 	u64 rx128to255octets_gb;
182 	u64 rx256to511octets_gb;
183 	u64 rx512to1023octets_gb;
184 	u64 rx1024tomaxoctets_gb;
185 	u64 rxunicastframes_g;
186 	u64 rxlengtherror;
187 	u64 rxoutofrangetype;
188 	u64 rxpauseframes;
189 	u64 rxfifooverflow;
190 	u64 rxvlanframes_gb;
191 	u64 rxwatchdogerror;
192 
193 	/* Extra counters */
194 	u64 tx_tso_packets;
195 	u64 rx_split_header_packets;
196 	u64 tx_process_stopped;
197 	u64 rx_process_stopped;
198 	u64 tx_buffer_unavailable;
199 	u64 rx_buffer_unavailable;
200 	u64 fatal_bus_error;
201 	u64 tx_vlan_packets;
202 	u64 rx_vlan_packets;
203 	u64 napi_poll_isr;
204 	u64 napi_poll_txtimer;
205 };
206 
207 struct xlgmac_ring_buf {
208 	struct sk_buff *skb;
209 	dma_addr_t skb_dma;
210 	unsigned int skb_len;
211 };
212 
213 /* Common Tx and Rx DMA hardware descriptor */
214 struct xlgmac_dma_desc {
215 	__le32 desc0;
216 	__le32 desc1;
217 	__le32 desc2;
218 	__le32 desc3;
219 };
220 
221 /* Page allocation related values */
222 struct xlgmac_page_alloc {
223 	struct page *pages;
224 	unsigned int pages_len;
225 	unsigned int pages_offset;
226 
227 	dma_addr_t pages_dma;
228 };
229 
230 /* Ring entry buffer data */
231 struct xlgmac_buffer_data {
232 	struct xlgmac_page_alloc pa;
233 	struct xlgmac_page_alloc pa_unmap;
234 
235 	dma_addr_t dma_base;
236 	unsigned long dma_off;
237 	unsigned int dma_len;
238 };
239 
240 /* Tx-related desc data */
241 struct xlgmac_tx_desc_data {
242 	unsigned int packets;		/* BQL packet count */
243 	unsigned int bytes;		/* BQL byte count */
244 };
245 
246 /* Rx-related desc data */
247 struct xlgmac_rx_desc_data {
248 	struct xlgmac_buffer_data hdr;	/* Header locations */
249 	struct xlgmac_buffer_data buf;	/* Payload locations */
250 
251 	unsigned short hdr_len;		/* Length of received header */
252 	unsigned short len;		/* Length of received packet */
253 };
254 
255 struct xlgmac_pkt_info {
256 	struct sk_buff *skb;
257 
258 	unsigned int attributes;
259 
260 	unsigned int errors;
261 
262 	/* descriptors needed for this packet */
263 	unsigned int desc_count;
264 	unsigned int length;
265 
266 	unsigned int tx_packets;
267 	unsigned int tx_bytes;
268 
269 	unsigned int header_len;
270 	unsigned int tcp_header_len;
271 	unsigned int tcp_payload_len;
272 	unsigned short mss;
273 
274 	unsigned short vlan_ctag;
275 
276 	u64 rx_tstamp;
277 
278 	u32 rss_hash;
279 	enum pkt_hash_types rss_hash_type;
280 };
281 
282 struct xlgmac_desc_data {
283 	/* dma_desc: Virtual address of descriptor
284 	 *  dma_desc_addr: DMA address of descriptor
285 	 */
286 	struct xlgmac_dma_desc *dma_desc;
287 	dma_addr_t dma_desc_addr;
288 
289 	/* skb: Virtual address of SKB
290 	 *  skb_dma: DMA address of SKB data
291 	 *  skb_dma_len: Length of SKB DMA area
292 	 */
293 	struct sk_buff *skb;
294 	dma_addr_t skb_dma;
295 	unsigned int skb_dma_len;
296 
297 	/* Tx/Rx -related data */
298 	struct xlgmac_tx_desc_data tx;
299 	struct xlgmac_rx_desc_data rx;
300 
301 	unsigned int mapped_as_page;
302 
303 	/* Incomplete receive save location.  If the budget is exhausted
304 	 * or the last descriptor (last normal descriptor or a following
305 	 * context descriptor) has not been DMA'd yet the current state
306 	 * of the receive processing needs to be saved.
307 	 */
308 	unsigned int state_saved;
309 	struct {
310 		struct sk_buff *skb;
311 		unsigned int len;
312 		unsigned int error;
313 	} state;
314 };
315 
316 struct xlgmac_ring {
317 	/* Per packet related information */
318 	struct xlgmac_pkt_info pkt_info;
319 
320 	/* Virtual/DMA addresses of DMA descriptor list and the total count */
321 	struct xlgmac_dma_desc *dma_desc_head;
322 	dma_addr_t dma_desc_head_addr;
323 	unsigned int dma_desc_count;
324 
325 	/* Array of descriptor data corresponding the DMA descriptor
326 	 * (always use the XLGMAC_GET_DESC_DATA macro to access this data)
327 	 */
328 	struct xlgmac_desc_data *desc_data_head;
329 
330 	/* Page allocation for RX buffers */
331 	struct xlgmac_page_alloc rx_hdr_pa;
332 	struct xlgmac_page_alloc rx_buf_pa;
333 
334 	/* Ring index values
335 	 *  cur   - Tx: index of descriptor to be used for current transfer
336 	 *          Rx: index of descriptor to check for packet availability
337 	 *  dirty - Tx: index of descriptor to check for transfer complete
338 	 *          Rx: index of descriptor to check for buffer reallocation
339 	 */
340 	unsigned int cur;
341 	unsigned int dirty;
342 
343 	/* Coalesce frame count used for interrupt bit setting */
344 	unsigned int coalesce_count;
345 
346 	union {
347 		struct {
348 			unsigned int xmit_more;
349 			unsigned int queue_stopped;
350 			unsigned short cur_mss;
351 			unsigned short cur_vlan_ctag;
352 		} tx;
353 	};
354 } ____cacheline_aligned;
355 
356 struct xlgmac_channel {
357 	char name[16];
358 
359 	/* Address of private data area for device */
360 	struct xlgmac_pdata *pdata;
361 
362 	/* Queue index and base address of queue's DMA registers */
363 	unsigned int queue_index;
364 	void __iomem *dma_regs;
365 
366 	/* Per channel interrupt irq number */
367 	int dma_irq;
368 	char dma_irq_name[IFNAMSIZ + 32];
369 
370 	/* Netdev related settings */
371 	struct napi_struct napi;
372 
373 	unsigned int saved_ier;
374 
375 	unsigned int tx_timer_active;
376 	struct timer_list tx_timer;
377 
378 	struct xlgmac_ring *tx_ring;
379 	struct xlgmac_ring *rx_ring;
380 } ____cacheline_aligned;
381 
382 struct xlgmac_desc_ops {
383 	int (*alloc_channels_and_rings)(struct xlgmac_pdata *pdata);
384 	void (*free_channels_and_rings)(struct xlgmac_pdata *pdata);
385 	int (*map_tx_skb)(struct xlgmac_channel *channel,
386 			  struct sk_buff *skb);
387 	int (*map_rx_buffer)(struct xlgmac_pdata *pdata,
388 			     struct xlgmac_ring *ring,
389 			struct xlgmac_desc_data *desc_data);
390 	void (*unmap_desc_data)(struct xlgmac_pdata *pdata,
391 				struct xlgmac_desc_data *desc_data);
392 	void (*tx_desc_init)(struct xlgmac_pdata *pdata);
393 	void (*rx_desc_init)(struct xlgmac_pdata *pdata);
394 };
395 
396 struct xlgmac_hw_ops {
397 	int (*init)(struct xlgmac_pdata *pdata);
398 	int (*exit)(struct xlgmac_pdata *pdata);
399 
400 	int (*tx_complete)(struct xlgmac_dma_desc *dma_desc);
401 
402 	void (*enable_tx)(struct xlgmac_pdata *pdata);
403 	void (*disable_tx)(struct xlgmac_pdata *pdata);
404 	void (*enable_rx)(struct xlgmac_pdata *pdata);
405 	void (*disable_rx)(struct xlgmac_pdata *pdata);
406 
407 	int (*enable_int)(struct xlgmac_channel *channel,
408 			  enum xlgmac_int int_id);
409 	int (*disable_int)(struct xlgmac_channel *channel,
410 			   enum xlgmac_int int_id);
411 	void (*dev_xmit)(struct xlgmac_channel *channel);
412 	int (*dev_read)(struct xlgmac_channel *channel);
413 
414 	int (*set_mac_address)(struct xlgmac_pdata *pdata, const u8 *addr);
415 	int (*config_rx_mode)(struct xlgmac_pdata *pdata);
416 	int (*enable_rx_csum)(struct xlgmac_pdata *pdata);
417 	int (*disable_rx_csum)(struct xlgmac_pdata *pdata);
418 
419 	/* For MII speed configuration */
420 	int (*set_xlgmii_25000_speed)(struct xlgmac_pdata *pdata);
421 	int (*set_xlgmii_40000_speed)(struct xlgmac_pdata *pdata);
422 	int (*set_xlgmii_50000_speed)(struct xlgmac_pdata *pdata);
423 	int (*set_xlgmii_100000_speed)(struct xlgmac_pdata *pdata);
424 
425 	/* For descriptor related operation */
426 	void (*tx_desc_init)(struct xlgmac_channel *channel);
427 	void (*rx_desc_init)(struct xlgmac_channel *channel);
428 	void (*tx_desc_reset)(struct xlgmac_desc_data *desc_data);
429 	void (*rx_desc_reset)(struct xlgmac_pdata *pdata,
430 			      struct xlgmac_desc_data *desc_data,
431 			unsigned int index);
432 	int (*is_last_desc)(struct xlgmac_dma_desc *dma_desc);
433 	int (*is_context_desc)(struct xlgmac_dma_desc *dma_desc);
434 	void (*tx_start_xmit)(struct xlgmac_channel *channel,
435 			      struct xlgmac_ring *ring);
436 
437 	/* For Flow Control */
438 	int (*config_tx_flow_control)(struct xlgmac_pdata *pdata);
439 	int (*config_rx_flow_control)(struct xlgmac_pdata *pdata);
440 
441 	/* For Vlan related config */
442 	int (*enable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
443 	int (*disable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
444 	int (*enable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
445 	int (*disable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
446 	int (*update_vlan_hash_table)(struct xlgmac_pdata *pdata);
447 
448 	/* For RX coalescing */
449 	int (*config_rx_coalesce)(struct xlgmac_pdata *pdata);
450 	int (*config_tx_coalesce)(struct xlgmac_pdata *pdata);
451 	unsigned int (*usec_to_riwt)(struct xlgmac_pdata *pdata,
452 				     unsigned int usec);
453 	unsigned int (*riwt_to_usec)(struct xlgmac_pdata *pdata,
454 				     unsigned int riwt);
455 
456 	/* For RX and TX threshold config */
457 	int (*config_rx_threshold)(struct xlgmac_pdata *pdata,
458 				   unsigned int val);
459 	int (*config_tx_threshold)(struct xlgmac_pdata *pdata,
460 				   unsigned int val);
461 
462 	/* For RX and TX Store and Forward Mode config */
463 	int (*config_rsf_mode)(struct xlgmac_pdata *pdata,
464 			       unsigned int val);
465 	int (*config_tsf_mode)(struct xlgmac_pdata *pdata,
466 			       unsigned int val);
467 
468 	/* For TX DMA Operate on Second Frame config */
469 	int (*config_osp_mode)(struct xlgmac_pdata *pdata);
470 
471 	/* For RX and TX PBL config */
472 	int (*config_rx_pbl_val)(struct xlgmac_pdata *pdata);
473 	int (*get_rx_pbl_val)(struct xlgmac_pdata *pdata);
474 	int (*config_tx_pbl_val)(struct xlgmac_pdata *pdata);
475 	int (*get_tx_pbl_val)(struct xlgmac_pdata *pdata);
476 	int (*config_pblx8)(struct xlgmac_pdata *pdata);
477 
478 	/* For MMC statistics */
479 	void (*rx_mmc_int)(struct xlgmac_pdata *pdata);
480 	void (*tx_mmc_int)(struct xlgmac_pdata *pdata);
481 	void (*read_mmc_stats)(struct xlgmac_pdata *pdata);
482 
483 	/* For Receive Side Scaling */
484 	int (*enable_rss)(struct xlgmac_pdata *pdata);
485 	int (*disable_rss)(struct xlgmac_pdata *pdata);
486 	int (*set_rss_hash_key)(struct xlgmac_pdata *pdata,
487 				const u8 *key);
488 	int (*set_rss_lookup_table)(struct xlgmac_pdata *pdata,
489 				    const u32 *table);
490 };
491 
492 /* This structure contains flags that indicate what hardware features
493  * or configurations are present in the device.
494  */
495 struct xlgmac_hw_features {
496 	/* HW Version */
497 	unsigned int version;
498 
499 	/* HW Feature Register0 */
500 	unsigned int phyifsel;		/* PHY interface support */
501 	unsigned int vlhash;		/* VLAN Hash Filter */
502 	unsigned int sma;		/* SMA(MDIO) Interface */
503 	unsigned int rwk;		/* PMT remote wake-up packet */
504 	unsigned int mgk;		/* PMT magic packet */
505 	unsigned int mmc;		/* RMON module */
506 	unsigned int aoe;		/* ARP Offload */
507 	unsigned int ts;		/* IEEE 1588-2008 Advanced Timestamp */
508 	unsigned int eee;		/* Energy Efficient Ethernet */
509 	unsigned int tx_coe;		/* Tx Checksum Offload */
510 	unsigned int rx_coe;		/* Rx Checksum Offload */
511 	unsigned int addn_mac;		/* Additional MAC Addresses */
512 	unsigned int ts_src;		/* Timestamp Source */
513 	unsigned int sa_vlan_ins;	/* Source Address or VLAN Insertion */
514 
515 	/* HW Feature Register1 */
516 	unsigned int rx_fifo_size;	/* MTL Receive FIFO Size */
517 	unsigned int tx_fifo_size;	/* MTL Transmit FIFO Size */
518 	unsigned int adv_ts_hi;		/* Advance Timestamping High Word */
519 	unsigned int dma_width;		/* DMA width */
520 	unsigned int dcb;		/* DCB Feature */
521 	unsigned int sph;		/* Split Header Feature */
522 	unsigned int tso;		/* TCP Segmentation Offload */
523 	unsigned int dma_debug;		/* DMA Debug Registers */
524 	unsigned int rss;		/* Receive Side Scaling */
525 	unsigned int tc_cnt;		/* Number of Traffic Classes */
526 	unsigned int hash_table_size;	/* Hash Table Size */
527 	unsigned int l3l4_filter_num;	/* Number of L3-L4 Filters */
528 
529 	/* HW Feature Register2 */
530 	unsigned int rx_q_cnt;		/* Number of MTL Receive Queues */
531 	unsigned int tx_q_cnt;		/* Number of MTL Transmit Queues */
532 	unsigned int rx_ch_cnt;		/* Number of DMA Receive Channels */
533 	unsigned int tx_ch_cnt;		/* Number of DMA Transmit Channels */
534 	unsigned int pps_out_num;	/* Number of PPS outputs */
535 	unsigned int aux_snap_num;	/* Number of Aux snapshot inputs */
536 };
537 
538 struct xlgmac_resources {
539 	void __iomem *addr;
540 	int irq;
541 };
542 
543 struct xlgmac_pdata {
544 	struct net_device *netdev;
545 	struct device *dev;
546 
547 	struct xlgmac_hw_ops hw_ops;
548 	struct xlgmac_desc_ops desc_ops;
549 
550 	/* Device statistics */
551 	struct xlgmac_stats stats;
552 
553 	u32 msg_enable;
554 
555 	/* MAC registers base */
556 	void __iomem *mac_regs;
557 
558 	/* Hardware features of the device */
559 	struct xlgmac_hw_features hw_feat;
560 
561 	struct work_struct restart_work;
562 
563 	/* Rings for Tx/Rx on a DMA channel */
564 	struct xlgmac_channel *channel_head;
565 	unsigned int channel_count;
566 	unsigned int tx_ring_count;
567 	unsigned int rx_ring_count;
568 	unsigned int tx_desc_count;
569 	unsigned int rx_desc_count;
570 	unsigned int tx_q_count;
571 	unsigned int rx_q_count;
572 
573 	/* Tx/Rx common settings */
574 	unsigned int pblx8;
575 
576 	/* Tx settings */
577 	unsigned int tx_sf_mode;
578 	unsigned int tx_threshold;
579 	unsigned int tx_pbl;
580 	unsigned int tx_osp_mode;
581 
582 	/* Rx settings */
583 	unsigned int rx_sf_mode;
584 	unsigned int rx_threshold;
585 	unsigned int rx_pbl;
586 
587 	/* Tx coalescing settings */
588 	unsigned int tx_usecs;
589 	unsigned int tx_frames;
590 
591 	/* Rx coalescing settings */
592 	unsigned int rx_riwt;
593 	unsigned int rx_usecs;
594 	unsigned int rx_frames;
595 
596 	/* Current Rx buffer size */
597 	unsigned int rx_buf_size;
598 
599 	/* Flow control settings */
600 	unsigned int tx_pause;
601 	unsigned int rx_pause;
602 
603 	/* Device interrupt number */
604 	int dev_irq;
605 	unsigned int per_channel_irq;
606 	int channel_irq[XLGMAC_MAX_DMA_CHANNELS];
607 
608 	/* Netdev related settings */
609 	unsigned char mac_addr[ETH_ALEN];
610 	netdev_features_t netdev_features;
611 	struct napi_struct napi;
612 
613 	/* Filtering support */
614 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
615 
616 	/* Device clocks */
617 	unsigned long sysclk_rate;
618 
619 	/* RSS addressing mutex */
620 	struct mutex rss_mutex;
621 
622 	/* Receive Side Scaling settings */
623 	u8 rss_key[XLGMAC_RSS_HASH_KEY_SIZE];
624 	u32 rss_table[XLGMAC_RSS_MAX_TABLE_SIZE];
625 	u32 rss_options;
626 
627 	int phy_speed;
628 
629 	char drv_name[32];
630 	char drv_ver[32];
631 };
632 
633 void xlgmac_init_desc_ops(struct xlgmac_desc_ops *desc_ops);
634 void xlgmac_init_hw_ops(struct xlgmac_hw_ops *hw_ops);
635 const struct net_device_ops *xlgmac_get_netdev_ops(void);
636 const struct ethtool_ops *xlgmac_get_ethtool_ops(void);
637 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
638 			 struct xlgmac_ring *ring,
639 			 unsigned int idx,
640 			 unsigned int count,
641 			 unsigned int flag);
642 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
643 			 struct xlgmac_ring *ring,
644 			 unsigned int idx);
645 void xlgmac_print_pkt(struct net_device *netdev,
646 		      struct sk_buff *skb, bool tx_rx);
647 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata);
648 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata);
649 int xlgmac_drv_probe(struct device *dev,
650 		     struct xlgmac_resources *res);
651 int xlgmac_drv_remove(struct device *dev);
652 
653 /* For debug prints */
654 #ifdef XLGMAC_DEBUG
655 #define XLGMAC_PR(fmt, args...) \
656 	pr_alert("[%s,%d]:" fmt, __func__, __LINE__, ## args)
657 #else
658 #define XLGMAC_PR(x...)		do { } while (0)
659 #endif
660 
661 #endif /* __DWC_XLGMAC_H__ */
662