xref: /openbmc/linux/drivers/net/ethernet/amd/xgbe/xgbe.h (revision 4f3b20bf)
1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * This file is available to you under your choice of the following two
5  * licenses:
6  *
7  * License 1: GPLv2
8  *
9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60  * All rights reserved.
61  *
62  * Redistribution and use in source and binary forms, with or without
63  * modification, are permitted provided that the following conditions are met:
64  *     * Redistributions of source code must retain the above copyright
65  *       notice, this list of conditions and the following disclaimer.
66  *     * Redistributions in binary form must reproduce the above copyright
67  *       notice, this list of conditions and the following disclaimer in the
68  *       documentation and/or other materials provided with the distribution.
69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
70  *       names of its contributors may be used to endorse or promote products
71  *       derived from this software without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83  *
84  * This file incorporates work covered by the following copyright and
85  * permission notice:
86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89  *     and you.
90  *
91  *     The Software IS NOT an item of Licensed Software or Licensed Product
92  *     under any End User Software License Agreement or Agreement for Licensed
93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
94  *     granted, free of charge, to any person obtaining a copy of this software
95  *     annotated with this license and the Software, to deal in the Software
96  *     without restriction, including without limitation the rights to use,
97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98  *     of the Software, and to permit persons to whom the Software is furnished
99  *     to do so, subject to the following conditions:
100  *
101  *     The above copyright notice and this permission notice shall be included
102  *     in all copies or substantial portions of the Software.
103  *
104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114  *     THE POSSIBILITY OF SUCH DAMAGE.
115  */
116 
117 #ifndef __XGBE_H__
118 #define __XGBE_H__
119 
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/timecounter.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
130 #include <linux/completion.h>
131 #include <linux/cpumask.h>
132 #include <linux/interrupt.h>
133 #include <linux/dcache.h>
134 #include <linux/ethtool.h>
135 #include <linux/list.h>
136 
137 #define XGBE_DRV_NAME		"amd-xgbe"
138 #define XGBE_DRV_DESC		"AMD 10 Gigabit Ethernet Driver"
139 
140 /* Descriptor related defines */
141 #define XGBE_TX_DESC_CNT	512
142 #define XGBE_TX_DESC_MIN_FREE	(XGBE_TX_DESC_CNT >> 3)
143 #define XGBE_TX_DESC_MAX_PROC	(XGBE_TX_DESC_CNT >> 1)
144 #define XGBE_RX_DESC_CNT	512
145 
146 #define XGBE_TX_DESC_CNT_MIN	64
147 #define XGBE_TX_DESC_CNT_MAX	4096
148 #define XGBE_RX_DESC_CNT_MIN	64
149 #define XGBE_RX_DESC_CNT_MAX	4096
150 
151 #define XGBE_TX_MAX_BUF_SIZE	(0x3fff & ~(64 - 1))
152 
153 /* Descriptors required for maximum contiguous TSO/GSO packet */
154 #define XGBE_TX_MAX_SPLIT	\
155 	((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
156 
157 /* Maximum possible descriptors needed for an SKB:
158  * - Maximum number of SKB frags
159  * - Maximum descriptors for contiguous TSO/GSO packet
160  * - Possible context descriptor
161  * - Possible TSO header descriptor
162  */
163 #define XGBE_TX_MAX_DESCS	(MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
164 
165 #define XGBE_RX_MIN_BUF_SIZE	(ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
166 #define XGBE_RX_BUF_ALIGN	64
167 #define XGBE_SKB_ALLOC_SIZE	256
168 #define XGBE_SPH_HDSMS_SIZE	2	/* Keep in sync with SKB_ALLOC_SIZE */
169 
170 #define XGBE_MAX_DMA_CHANNELS	16
171 #define XGBE_MAX_QUEUES		16
172 #define XGBE_PRIORITY_QUEUES	8
173 #define XGBE_DMA_STOP_TIMEOUT	1
174 
175 /* DMA cache settings - Outer sharable, write-back, write-allocate */
176 #define XGBE_DMA_OS_ARCR	0x002b2b2b
177 #define XGBE_DMA_OS_AWCR	0x2f2f2f2f
178 
179 /* DMA cache settings - System, no caches used */
180 #define XGBE_DMA_SYS_ARCR	0x00303030
181 #define XGBE_DMA_SYS_AWCR	0x30303030
182 
183 /* DMA cache settings - PCI device */
184 #define XGBE_DMA_PCI_ARCR	0x000f0f0f
185 #define XGBE_DMA_PCI_AWCR	0x0f0f0f0f
186 #define XGBE_DMA_PCI_AWARCR	0x00000f0f
187 
188 /* DMA channel interrupt modes */
189 #define XGBE_IRQ_MODE_EDGE	0
190 #define XGBE_IRQ_MODE_LEVEL	1
191 
192 #define XGMAC_MIN_PACKET	60
193 #define XGMAC_STD_PACKET_MTU	1500
194 #define XGMAC_MAX_STD_PACKET	1518
195 #define XGMAC_JUMBO_PACKET_MTU	9000
196 #define XGMAC_MAX_JUMBO_PACKET	9018
197 #define XGMAC_ETH_PREAMBLE	(12 + 8)	/* Inter-frame gap + preamble */
198 
199 #define XGMAC_PFC_DATA_LEN	46
200 #define XGMAC_PFC_DELAYS	14000
201 
202 #define XGMAC_PRIO_QUEUES(_cnt)					\
203 	min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
204 
205 /* Common property names */
206 #define XGBE_MAC_ADDR_PROPERTY	"mac-address"
207 #define XGBE_PHY_MODE_PROPERTY	"phy-mode"
208 #define XGBE_DMA_IRQS_PROPERTY	"amd,per-channel-interrupt"
209 #define XGBE_SPEEDSET_PROPERTY	"amd,speed-set"
210 
211 /* Device-tree clock names */
212 #define XGBE_DMA_CLOCK		"dma_clk"
213 #define XGBE_PTP_CLOCK		"ptp_clk"
214 
215 /* ACPI property names */
216 #define XGBE_ACPI_DMA_FREQ	"amd,dma-freq"
217 #define XGBE_ACPI_PTP_FREQ	"amd,ptp-freq"
218 
219 /* PCI BAR mapping */
220 #define XGBE_XGMAC_BAR		0
221 #define XGBE_XPCS_BAR		1
222 #define XGBE_MAC_PROP_OFFSET	0x1d000
223 #define XGBE_I2C_CTRL_OFFSET	0x1e000
224 
225 /* PCI MSI/MSIx support */
226 #define XGBE_MSI_BASE_COUNT	4
227 #define XGBE_MSI_MIN_COUNT	(XGBE_MSI_BASE_COUNT + 1)
228 
229 /* PCI clock frequencies */
230 #define XGBE_V2_DMA_CLOCK_FREQ	500000000	/* 500 MHz */
231 #define XGBE_V2_PTP_CLOCK_FREQ	125000000	/* 125 MHz */
232 
233 /* Timestamp support - values based on 50MHz PTP clock
234  *   50MHz => 20 nsec
235  */
236 #define XGBE_TSTAMP_SSINC	20
237 #define XGBE_TSTAMP_SNSINC	0
238 
239 /* Driver PMT macros */
240 #define XGMAC_DRIVER_CONTEXT	1
241 #define XGMAC_IOCTL_CONTEXT	2
242 
243 #define XGMAC_FIFO_MIN_ALLOC	2048
244 #define XGMAC_FIFO_UNIT		256
245 #define XGMAC_FIFO_ALIGN(_x)				\
246 	(((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
247 #define XGMAC_FIFO_FC_OFF	2048
248 #define XGMAC_FIFO_FC_MIN	4096
249 
250 #define XGBE_TC_MIN_QUANTUM	10
251 
252 /* Helper macro for descriptor handling
253  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
254  *  since the index is free-running and needs to be and-ed
255  *  with the descriptor count value of the ring to index to
256  *  the proper descriptor data.
257  */
258 #define XGBE_GET_DESC_DATA(_ring, _idx)				\
259 	((_ring)->rdata +					\
260 	 ((_idx) & ((_ring)->rdesc_count - 1)))
261 
262 /* Default coalescing parameters */
263 #define XGMAC_INIT_DMA_TX_USECS		1000
264 #define XGMAC_INIT_DMA_TX_FRAMES	25
265 
266 #define XGMAC_MAX_DMA_RIWT		0xff
267 #define XGMAC_INIT_DMA_RX_USECS		30
268 #define XGMAC_INIT_DMA_RX_FRAMES	25
269 
270 /* Flow control queue count */
271 #define XGMAC_MAX_FLOW_CONTROL_QUEUES	8
272 
273 /* Flow control threshold units */
274 #define XGMAC_FLOW_CONTROL_UNIT		512
275 #define XGMAC_FLOW_CONTROL_ALIGN(_x)				\
276 	(((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
277 #define XGMAC_FLOW_CONTROL_VALUE(_x)				\
278 	(((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
279 #define XGMAC_FLOW_CONTROL_MAX		33280
280 
281 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
282 #define XGBE_MAC_HASH_TABLE_SIZE	8
283 
284 /* Receive Side Scaling */
285 #define XGBE_RSS_HASH_KEY_SIZE		40
286 #define XGBE_RSS_MAX_TABLE_SIZE		256
287 #define XGBE_RSS_LOOKUP_TABLE_TYPE	0
288 #define XGBE_RSS_HASH_KEY_TYPE		1
289 
290 /* Auto-negotiation */
291 #define XGBE_AN_MS_TIMEOUT		500
292 #define XGBE_LINK_TIMEOUT		5
293 #define XGBE_KR_TRAINING_WAIT_ITER	50
294 
295 #define XGBE_SGMII_AN_LINK_STATUS	BIT(1)
296 #define XGBE_SGMII_AN_LINK_SPEED	(BIT(2) | BIT(3))
297 #define XGBE_SGMII_AN_LINK_SPEED_10	0x00
298 #define XGBE_SGMII_AN_LINK_SPEED_100	0x04
299 #define XGBE_SGMII_AN_LINK_SPEED_1000	0x08
300 #define XGBE_SGMII_AN_LINK_DUPLEX	BIT(4)
301 
302 /* ECC correctable error notification window (seconds) */
303 #define XGBE_ECC_LIMIT			60
304 
305 /* MDIO port types */
306 #define XGMAC_MAX_C22_PORT		3
307 
308 /* Link mode bit operations */
309 #define XGBE_ZERO_SUP(_ls)		\
310 	ethtool_link_ksettings_zero_link_mode((_ls), supported)
311 
312 #define XGBE_SET_SUP(_ls, _mode)	\
313 	ethtool_link_ksettings_add_link_mode((_ls), supported, _mode)
314 
315 #define XGBE_CLR_SUP(_ls, _mode)	\
316 	ethtool_link_ksettings_del_link_mode((_ls), supported, _mode)
317 
318 #define XGBE_IS_SUP(_ls, _mode)	\
319 	ethtool_link_ksettings_test_link_mode((_ls), supported, _mode)
320 
321 #define XGBE_ZERO_ADV(_ls)		\
322 	ethtool_link_ksettings_zero_link_mode((_ls), advertising)
323 
324 #define XGBE_SET_ADV(_ls, _mode)	\
325 	ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode)
326 
327 #define XGBE_CLR_ADV(_ls, _mode)	\
328 	ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode)
329 
330 #define XGBE_ADV(_ls, _mode)		\
331 	ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode)
332 
333 #define XGBE_ZERO_LP_ADV(_ls)		\
334 	ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising)
335 
336 #define XGBE_SET_LP_ADV(_ls, _mode)	\
337 	ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode)
338 
339 #define XGBE_CLR_LP_ADV(_ls, _mode)	\
340 	ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode)
341 
342 #define XGBE_LP_ADV(_ls, _mode)		\
343 	ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode)
344 
345 #define XGBE_LM_COPY(_dst, _dname, _src, _sname)	\
346 	bitmap_copy((_dst)->link_modes._dname,		\
347 		    (_src)->link_modes._sname,		\
348 		    __ETHTOOL_LINK_MODE_MASK_NBITS)
349 
350 struct xgbe_prv_data;
351 
352 struct xgbe_packet_data {
353 	struct sk_buff *skb;
354 
355 	unsigned int attributes;
356 
357 	unsigned int errors;
358 
359 	unsigned int rdesc_count;
360 	unsigned int length;
361 
362 	unsigned int header_len;
363 	unsigned int tcp_header_len;
364 	unsigned int tcp_payload_len;
365 	unsigned short mss;
366 
367 	unsigned short vlan_ctag;
368 
369 	u64 rx_tstamp;
370 
371 	u32 rss_hash;
372 	enum pkt_hash_types rss_hash_type;
373 
374 	unsigned int tx_packets;
375 	unsigned int tx_bytes;
376 };
377 
378 /* Common Rx and Tx descriptor mapping */
379 struct xgbe_ring_desc {
380 	__le32 desc0;
381 	__le32 desc1;
382 	__le32 desc2;
383 	__le32 desc3;
384 };
385 
386 /* Page allocation related values */
387 struct xgbe_page_alloc {
388 	struct page *pages;
389 	unsigned int pages_len;
390 	unsigned int pages_offset;
391 
392 	dma_addr_t pages_dma;
393 };
394 
395 /* Ring entry buffer data */
396 struct xgbe_buffer_data {
397 	struct xgbe_page_alloc pa;
398 	struct xgbe_page_alloc pa_unmap;
399 
400 	dma_addr_t dma_base;
401 	unsigned long dma_off;
402 	unsigned int dma_len;
403 };
404 
405 /* Tx-related ring data */
406 struct xgbe_tx_ring_data {
407 	unsigned int packets;		/* BQL packet count */
408 	unsigned int bytes;		/* BQL byte count */
409 };
410 
411 /* Rx-related ring data */
412 struct xgbe_rx_ring_data {
413 	struct xgbe_buffer_data hdr;	/* Header locations */
414 	struct xgbe_buffer_data buf;	/* Payload locations */
415 
416 	unsigned short hdr_len;		/* Length of received header */
417 	unsigned short len;		/* Length of received packet */
418 };
419 
420 /* Structure used to hold information related to the descriptor
421  * and the packet associated with the descriptor (always use
422  * the XGBE_GET_DESC_DATA macro to access this data from the ring)
423  */
424 struct xgbe_ring_data {
425 	struct xgbe_ring_desc *rdesc;	/* Virtual address of descriptor */
426 	dma_addr_t rdesc_dma;		/* DMA address of descriptor */
427 
428 	struct sk_buff *skb;		/* Virtual address of SKB */
429 	dma_addr_t skb_dma;		/* DMA address of SKB data */
430 	unsigned int skb_dma_len;	/* Length of SKB DMA area */
431 
432 	struct xgbe_tx_ring_data tx;	/* Tx-related data */
433 	struct xgbe_rx_ring_data rx;	/* Rx-related data */
434 
435 	unsigned int mapped_as_page;
436 
437 	/* Incomplete receive save location.  If the budget is exhausted
438 	 * or the last descriptor (last normal descriptor or a following
439 	 * context descriptor) has not been DMA'd yet the current state
440 	 * of the receive processing needs to be saved.
441 	 */
442 	unsigned int state_saved;
443 	struct {
444 		struct sk_buff *skb;
445 		unsigned int len;
446 		unsigned int error;
447 	} state;
448 };
449 
450 struct xgbe_ring {
451 	/* Ring lock - used just for TX rings at the moment */
452 	spinlock_t lock;
453 
454 	/* Per packet related information */
455 	struct xgbe_packet_data packet_data;
456 
457 	/* Virtual/DMA addresses and count of allocated descriptor memory */
458 	struct xgbe_ring_desc *rdesc;
459 	dma_addr_t rdesc_dma;
460 	unsigned int rdesc_count;
461 
462 	/* Array of descriptor data corresponding the descriptor memory
463 	 * (always use the XGBE_GET_DESC_DATA macro to access this data)
464 	 */
465 	struct xgbe_ring_data *rdata;
466 
467 	/* Page allocation for RX buffers */
468 	struct xgbe_page_alloc rx_hdr_pa;
469 	struct xgbe_page_alloc rx_buf_pa;
470 	int node;
471 
472 	/* Ring index values
473 	 *  cur   - Tx: index of descriptor to be used for current transfer
474 	 *          Rx: index of descriptor to check for packet availability
475 	 *  dirty - Tx: index of descriptor to check for transfer complete
476 	 *          Rx: index of descriptor to check for buffer reallocation
477 	 */
478 	unsigned int cur;
479 	unsigned int dirty;
480 
481 	/* Coalesce frame count used for interrupt bit setting */
482 	unsigned int coalesce_count;
483 
484 	union {
485 		struct {
486 			unsigned int queue_stopped;
487 			unsigned int xmit_more;
488 			unsigned short cur_mss;
489 			unsigned short cur_vlan_ctag;
490 		} tx;
491 	};
492 } ____cacheline_aligned;
493 
494 /* Structure used to describe the descriptor rings associated with
495  * a DMA channel.
496  */
497 struct xgbe_channel {
498 	char name[16];
499 
500 	/* Address of private data area for device */
501 	struct xgbe_prv_data *pdata;
502 
503 	/* Queue index and base address of queue's DMA registers */
504 	unsigned int queue_index;
505 	void __iomem *dma_regs;
506 
507 	/* Per channel interrupt irq number */
508 	int dma_irq;
509 	char dma_irq_name[IFNAMSIZ + 32];
510 
511 	/* Netdev related settings */
512 	struct napi_struct napi;
513 
514 	/* Per channel interrupt enablement tracker */
515 	unsigned int curr_ier;
516 	unsigned int saved_ier;
517 
518 	unsigned int tx_timer_active;
519 	struct timer_list tx_timer;
520 
521 	struct xgbe_ring *tx_ring;
522 	struct xgbe_ring *rx_ring;
523 
524 	int node;
525 	cpumask_t affinity_mask;
526 } ____cacheline_aligned;
527 
528 enum xgbe_state {
529 	XGBE_DOWN,
530 	XGBE_LINK_INIT,
531 	XGBE_LINK_ERR,
532 	XGBE_STOPPED,
533 };
534 
535 enum xgbe_int {
536 	XGMAC_INT_DMA_CH_SR_TI,
537 	XGMAC_INT_DMA_CH_SR_TPS,
538 	XGMAC_INT_DMA_CH_SR_TBU,
539 	XGMAC_INT_DMA_CH_SR_RI,
540 	XGMAC_INT_DMA_CH_SR_RBU,
541 	XGMAC_INT_DMA_CH_SR_RPS,
542 	XGMAC_INT_DMA_CH_SR_TI_RI,
543 	XGMAC_INT_DMA_CH_SR_FBE,
544 	XGMAC_INT_DMA_ALL,
545 };
546 
547 enum xgbe_int_state {
548 	XGMAC_INT_STATE_SAVE,
549 	XGMAC_INT_STATE_RESTORE,
550 };
551 
552 enum xgbe_ecc_sec {
553 	XGBE_ECC_SEC_TX,
554 	XGBE_ECC_SEC_RX,
555 	XGBE_ECC_SEC_DESC,
556 };
557 
558 enum xgbe_speed {
559 	XGBE_SPEED_1000 = 0,
560 	XGBE_SPEED_2500,
561 	XGBE_SPEED_10000,
562 	XGBE_SPEEDS,
563 };
564 
565 enum xgbe_xpcs_access {
566 	XGBE_XPCS_ACCESS_V1 = 0,
567 	XGBE_XPCS_ACCESS_V2,
568 };
569 
570 enum xgbe_an_mode {
571 	XGBE_AN_MODE_CL73 = 0,
572 	XGBE_AN_MODE_CL73_REDRV,
573 	XGBE_AN_MODE_CL37,
574 	XGBE_AN_MODE_CL37_SGMII,
575 	XGBE_AN_MODE_NONE,
576 };
577 
578 enum xgbe_an {
579 	XGBE_AN_READY = 0,
580 	XGBE_AN_PAGE_RECEIVED,
581 	XGBE_AN_INCOMPAT_LINK,
582 	XGBE_AN_COMPLETE,
583 	XGBE_AN_NO_LINK,
584 	XGBE_AN_ERROR,
585 };
586 
587 enum xgbe_rx {
588 	XGBE_RX_BPA = 0,
589 	XGBE_RX_XNP,
590 	XGBE_RX_COMPLETE,
591 	XGBE_RX_ERROR,
592 };
593 
594 enum xgbe_mode {
595 	XGBE_MODE_KX_1000 = 0,
596 	XGBE_MODE_KX_2500,
597 	XGBE_MODE_KR,
598 	XGBE_MODE_X,
599 	XGBE_MODE_SGMII_10,
600 	XGBE_MODE_SGMII_100,
601 	XGBE_MODE_SGMII_1000,
602 	XGBE_MODE_SFI,
603 	XGBE_MODE_UNKNOWN,
604 };
605 
606 enum xgbe_speedset {
607 	XGBE_SPEEDSET_1000_10000 = 0,
608 	XGBE_SPEEDSET_2500_10000,
609 };
610 
611 enum xgbe_mdio_mode {
612 	XGBE_MDIO_MODE_NONE = 0,
613 	XGBE_MDIO_MODE_CL22,
614 	XGBE_MDIO_MODE_CL45,
615 };
616 
617 enum xgbe_mb_cmd {
618 	XGBE_MB_CMD_POWER_OFF = 0,
619 	XGBE_MB_CMD_SET_1G,
620 	XGBE_MB_CMD_SET_2_5G,
621 	XGBE_MB_CMD_SET_10G_SFI,
622 	XGBE_MB_CMD_SET_10G_KR,
623 	XGBE_MB_CMD_RRC
624 };
625 
626 enum xgbe_mb_subcmd {
627 	XGBE_MB_SUBCMD_NONE = 0,
628 	XGBE_MB_SUBCMD_RX_ADAP,
629 
630 	/* 10GbE SFP subcommands */
631 	XGBE_MB_SUBCMD_ACTIVE = 0,
632 	XGBE_MB_SUBCMD_PASSIVE_1M,
633 	XGBE_MB_SUBCMD_PASSIVE_3M,
634 	XGBE_MB_SUBCMD_PASSIVE_OTHER,
635 
636 	/* 1GbE Mode subcommands */
637 	XGBE_MB_SUBCMD_10MBITS = 0,
638 	XGBE_MB_SUBCMD_100MBITS,
639 	XGBE_MB_SUBCMD_1G_SGMII,
640 	XGBE_MB_SUBCMD_1G_KX
641 };
642 
643 struct xgbe_phy {
644 	struct ethtool_link_ksettings lks;
645 
646 	int address;
647 
648 	int autoneg;
649 	int speed;
650 	int duplex;
651 
652 	int link;
653 
654 	int pause_autoneg;
655 	int tx_pause;
656 	int rx_pause;
657 };
658 
659 enum xgbe_i2c_cmd {
660 	XGBE_I2C_CMD_READ = 0,
661 	XGBE_I2C_CMD_WRITE,
662 };
663 
664 struct xgbe_i2c_op {
665 	enum xgbe_i2c_cmd cmd;
666 
667 	unsigned int target;
668 
669 	void *buf;
670 	unsigned int len;
671 };
672 
673 struct xgbe_i2c_op_state {
674 	struct xgbe_i2c_op *op;
675 
676 	unsigned int tx_len;
677 	unsigned char *tx_buf;
678 
679 	unsigned int rx_len;
680 	unsigned char *rx_buf;
681 
682 	unsigned int tx_abort_source;
683 
684 	int ret;
685 };
686 
687 struct xgbe_i2c {
688 	unsigned int started;
689 	unsigned int max_speed_mode;
690 	unsigned int rx_fifo_size;
691 	unsigned int tx_fifo_size;
692 
693 	struct xgbe_i2c_op_state op_state;
694 };
695 
696 struct xgbe_mmc_stats {
697 	/* Tx Stats */
698 	u64 txoctetcount_gb;
699 	u64 txframecount_gb;
700 	u64 txbroadcastframes_g;
701 	u64 txmulticastframes_g;
702 	u64 tx64octets_gb;
703 	u64 tx65to127octets_gb;
704 	u64 tx128to255octets_gb;
705 	u64 tx256to511octets_gb;
706 	u64 tx512to1023octets_gb;
707 	u64 tx1024tomaxoctets_gb;
708 	u64 txunicastframes_gb;
709 	u64 txmulticastframes_gb;
710 	u64 txbroadcastframes_gb;
711 	u64 txunderflowerror;
712 	u64 txoctetcount_g;
713 	u64 txframecount_g;
714 	u64 txpauseframes;
715 	u64 txvlanframes_g;
716 
717 	/* Rx Stats */
718 	u64 rxframecount_gb;
719 	u64 rxoctetcount_gb;
720 	u64 rxoctetcount_g;
721 	u64 rxbroadcastframes_g;
722 	u64 rxmulticastframes_g;
723 	u64 rxcrcerror;
724 	u64 rxrunterror;
725 	u64 rxjabbererror;
726 	u64 rxundersize_g;
727 	u64 rxoversize_g;
728 	u64 rx64octets_gb;
729 	u64 rx65to127octets_gb;
730 	u64 rx128to255octets_gb;
731 	u64 rx256to511octets_gb;
732 	u64 rx512to1023octets_gb;
733 	u64 rx1024tomaxoctets_gb;
734 	u64 rxunicastframes_g;
735 	u64 rxlengtherror;
736 	u64 rxoutofrangetype;
737 	u64 rxpauseframes;
738 	u64 rxfifooverflow;
739 	u64 rxvlanframes_gb;
740 	u64 rxwatchdogerror;
741 };
742 
743 struct xgbe_ext_stats {
744 	u64 tx_tso_packets;
745 	u64 rx_split_header_packets;
746 	u64 rx_buffer_unavailable;
747 
748 	u64 txq_packets[XGBE_MAX_DMA_CHANNELS];
749 	u64 txq_bytes[XGBE_MAX_DMA_CHANNELS];
750 	u64 rxq_packets[XGBE_MAX_DMA_CHANNELS];
751 	u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS];
752 
753 	u64 tx_vxlan_packets;
754 	u64 rx_vxlan_packets;
755 	u64 rx_csum_errors;
756 	u64 rx_vxlan_csum_errors;
757 };
758 
759 struct xgbe_hw_if {
760 	int (*tx_complete)(struct xgbe_ring_desc *);
761 
762 	int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr);
763 	int (*config_rx_mode)(struct xgbe_prv_data *);
764 
765 	int (*enable_rx_csum)(struct xgbe_prv_data *);
766 	int (*disable_rx_csum)(struct xgbe_prv_data *);
767 
768 	int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
769 	int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
770 	int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
771 	int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
772 	int (*update_vlan_hash_table)(struct xgbe_prv_data *);
773 
774 	int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
775 	void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
776 	int (*set_speed)(struct xgbe_prv_data *, int);
777 
778 	int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
779 				enum xgbe_mdio_mode);
780 	int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int);
781 	int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16);
782 	int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int);
783 	int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int,
784 				      u16);
785 
786 	int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
787 	int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
788 
789 	void (*enable_tx)(struct xgbe_prv_data *);
790 	void (*disable_tx)(struct xgbe_prv_data *);
791 	void (*enable_rx)(struct xgbe_prv_data *);
792 	void (*disable_rx)(struct xgbe_prv_data *);
793 
794 	void (*powerup_tx)(struct xgbe_prv_data *);
795 	void (*powerdown_tx)(struct xgbe_prv_data *);
796 	void (*powerup_rx)(struct xgbe_prv_data *);
797 	void (*powerdown_rx)(struct xgbe_prv_data *);
798 
799 	int (*init)(struct xgbe_prv_data *);
800 	int (*exit)(struct xgbe_prv_data *);
801 
802 	int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
803 	int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
804 	void (*dev_xmit)(struct xgbe_channel *);
805 	int (*dev_read)(struct xgbe_channel *);
806 	void (*tx_desc_init)(struct xgbe_channel *);
807 	void (*rx_desc_init)(struct xgbe_channel *);
808 	void (*tx_desc_reset)(struct xgbe_ring_data *);
809 	void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
810 			      unsigned int);
811 	int (*is_last_desc)(struct xgbe_ring_desc *);
812 	int (*is_context_desc)(struct xgbe_ring_desc *);
813 	void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
814 
815 	/* For FLOW ctrl */
816 	int (*config_tx_flow_control)(struct xgbe_prv_data *);
817 	int (*config_rx_flow_control)(struct xgbe_prv_data *);
818 
819 	/* For RX coalescing */
820 	int (*config_rx_coalesce)(struct xgbe_prv_data *);
821 	int (*config_tx_coalesce)(struct xgbe_prv_data *);
822 	unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
823 	unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
824 
825 	/* For RX and TX threshold config */
826 	int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
827 	int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
828 
829 	/* For RX and TX Store and Forward Mode config */
830 	int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
831 	int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
832 
833 	/* For TX DMA Operate on Second Frame config */
834 	int (*config_osp_mode)(struct xgbe_prv_data *);
835 
836 	/* For MMC statistics */
837 	void (*rx_mmc_int)(struct xgbe_prv_data *);
838 	void (*tx_mmc_int)(struct xgbe_prv_data *);
839 	void (*read_mmc_stats)(struct xgbe_prv_data *);
840 
841 	/* For Timestamp config */
842 	int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
843 	void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
844 	void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
845 				unsigned int nsec);
846 	u64 (*get_tstamp_time)(struct xgbe_prv_data *);
847 	u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
848 
849 	/* For Data Center Bridging config */
850 	void (*config_tc)(struct xgbe_prv_data *);
851 	void (*config_dcb_tc)(struct xgbe_prv_data *);
852 	void (*config_dcb_pfc)(struct xgbe_prv_data *);
853 
854 	/* For Receive Side Scaling */
855 	int (*enable_rss)(struct xgbe_prv_data *);
856 	int (*disable_rss)(struct xgbe_prv_data *);
857 	int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
858 	int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
859 
860 	/* For ECC */
861 	void (*disable_ecc_ded)(struct xgbe_prv_data *);
862 	void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
863 
864 	/* For VXLAN */
865 	void (*enable_vxlan)(struct xgbe_prv_data *);
866 	void (*disable_vxlan)(struct xgbe_prv_data *);
867 	void (*set_vxlan_id)(struct xgbe_prv_data *);
868 };
869 
870 /* This structure represents implementation specific routines for an
871  * implementation of a PHY. All routines are required unless noted below.
872  *   Optional routines:
873  *     an_pre, an_post
874  *     kr_training_pre, kr_training_post
875  *     module_info, module_eeprom
876  */
877 struct xgbe_phy_impl_if {
878 	/* Perform Setup/teardown actions */
879 	int (*init)(struct xgbe_prv_data *);
880 	void (*exit)(struct xgbe_prv_data *);
881 
882 	/* Perform start/stop specific actions */
883 	int (*reset)(struct xgbe_prv_data *);
884 	int (*start)(struct xgbe_prv_data *);
885 	void (*stop)(struct xgbe_prv_data *);
886 
887 	/* Return the link status */
888 	int (*link_status)(struct xgbe_prv_data *, int *);
889 
890 	/* Indicate if a particular speed is valid */
891 	bool (*valid_speed)(struct xgbe_prv_data *, int);
892 
893 	/* Check if the specified mode can/should be used */
894 	bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
895 	/* Switch the PHY into various modes */
896 	void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
897 	/* Retrieve mode needed for a specific speed */
898 	enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
899 	/* Retrieve new/next mode when trying to auto-negotiate */
900 	enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
901 	/* Retrieve current mode */
902 	enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
903 
904 	/* Retrieve current auto-negotiation mode */
905 	enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
906 
907 	/* Configure auto-negotiation settings */
908 	int (*an_config)(struct xgbe_prv_data *);
909 
910 	/* Set/override auto-negotiation advertisement settings */
911 	void (*an_advertising)(struct xgbe_prv_data *,
912 			       struct ethtool_link_ksettings *);
913 
914 	/* Process results of auto-negotiation */
915 	enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
916 
917 	/* Pre/Post auto-negotiation support */
918 	void (*an_pre)(struct xgbe_prv_data *);
919 	void (*an_post)(struct xgbe_prv_data *);
920 
921 	/* Pre/Post KR training enablement support */
922 	void (*kr_training_pre)(struct xgbe_prv_data *);
923 	void (*kr_training_post)(struct xgbe_prv_data *);
924 
925 	/* SFP module related info */
926 	int (*module_info)(struct xgbe_prv_data *pdata,
927 			   struct ethtool_modinfo *modinfo);
928 	int (*module_eeprom)(struct xgbe_prv_data *pdata,
929 			     struct ethtool_eeprom *eeprom, u8 *data);
930 };
931 
932 struct xgbe_phy_if {
933 	/* For PHY setup/teardown */
934 	int (*phy_init)(struct xgbe_prv_data *);
935 	void (*phy_exit)(struct xgbe_prv_data *);
936 
937 	/* For PHY support when setting device up/down */
938 	int (*phy_reset)(struct xgbe_prv_data *);
939 	int (*phy_start)(struct xgbe_prv_data *);
940 	void (*phy_stop)(struct xgbe_prv_data *);
941 
942 	/* For PHY support while device is up */
943 	void (*phy_status)(struct xgbe_prv_data *);
944 	int (*phy_config_aneg)(struct xgbe_prv_data *);
945 
946 	/* For PHY settings validation */
947 	bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
948 
949 	/* For single interrupt support */
950 	irqreturn_t (*an_isr)(struct xgbe_prv_data *);
951 
952 	/* For ethtool PHY support */
953 	int (*module_info)(struct xgbe_prv_data *pdata,
954 			   struct ethtool_modinfo *modinfo);
955 	int (*module_eeprom)(struct xgbe_prv_data *pdata,
956 			     struct ethtool_eeprom *eeprom, u8 *data);
957 
958 	/* PHY implementation specific services */
959 	struct xgbe_phy_impl_if phy_impl;
960 };
961 
962 struct xgbe_i2c_if {
963 	/* For initial I2C setup */
964 	int (*i2c_init)(struct xgbe_prv_data *);
965 
966 	/* For I2C support when setting device up/down */
967 	int (*i2c_start)(struct xgbe_prv_data *);
968 	void (*i2c_stop)(struct xgbe_prv_data *);
969 
970 	/* For performing I2C operations */
971 	int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
972 
973 	/* For single interrupt support */
974 	irqreturn_t (*i2c_isr)(struct xgbe_prv_data *);
975 };
976 
977 struct xgbe_desc_if {
978 	int (*alloc_ring_resources)(struct xgbe_prv_data *);
979 	void (*free_ring_resources)(struct xgbe_prv_data *);
980 	int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
981 	int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
982 			     struct xgbe_ring_data *);
983 	void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
984 	void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
985 	void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
986 };
987 
988 /* This structure contains flags that indicate what hardware features
989  * or configurations are present in the device.
990  */
991 struct xgbe_hw_features {
992 	/* HW Version */
993 	unsigned int version;
994 
995 	/* HW Feature Register0 */
996 	unsigned int gmii;		/* 1000 Mbps support */
997 	unsigned int vlhash;		/* VLAN Hash Filter */
998 	unsigned int sma;		/* SMA(MDIO) Interface */
999 	unsigned int rwk;		/* PMT remote wake-up packet */
1000 	unsigned int mgk;		/* PMT magic packet */
1001 	unsigned int mmc;		/* RMON module */
1002 	unsigned int aoe;		/* ARP Offload */
1003 	unsigned int ts;		/* IEEE 1588-2008 Advanced Timestamp */
1004 	unsigned int eee;		/* Energy Efficient Ethernet */
1005 	unsigned int tx_coe;		/* Tx Checksum Offload */
1006 	unsigned int rx_coe;		/* Rx Checksum Offload */
1007 	unsigned int addn_mac;		/* Additional MAC Addresses */
1008 	unsigned int ts_src;		/* Timestamp Source */
1009 	unsigned int sa_vlan_ins;	/* Source Address or VLAN Insertion */
1010 	unsigned int vxn;		/* VXLAN/NVGRE */
1011 
1012 	/* HW Feature Register1 */
1013 	unsigned int rx_fifo_size;	/* MTL Receive FIFO Size */
1014 	unsigned int tx_fifo_size;	/* MTL Transmit FIFO Size */
1015 	unsigned int adv_ts_hi;		/* Advance Timestamping High Word */
1016 	unsigned int dma_width;		/* DMA width */
1017 	unsigned int dcb;		/* DCB Feature */
1018 	unsigned int sph;		/* Split Header Feature */
1019 	unsigned int tso;		/* TCP Segmentation Offload */
1020 	unsigned int dma_debug;		/* DMA Debug Registers */
1021 	unsigned int rss;		/* Receive Side Scaling */
1022 	unsigned int tc_cnt;		/* Number of Traffic Classes */
1023 	unsigned int hash_table_size;	/* Hash Table Size */
1024 	unsigned int l3l4_filter_num;	/* Number of L3-L4 Filters */
1025 
1026 	/* HW Feature Register2 */
1027 	unsigned int rx_q_cnt;		/* Number of MTL Receive Queues */
1028 	unsigned int tx_q_cnt;		/* Number of MTL Transmit Queues */
1029 	unsigned int rx_ch_cnt;		/* Number of DMA Receive Channels */
1030 	unsigned int tx_ch_cnt;		/* Number of DMA Transmit Channels */
1031 	unsigned int pps_out_num;	/* Number of PPS outputs */
1032 	unsigned int aux_snap_num;	/* Number of Aux snapshot inputs */
1033 };
1034 
1035 struct xgbe_version_data {
1036 	void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
1037 	enum xgbe_xpcs_access xpcs_access;
1038 	unsigned int mmc_64bit;
1039 	unsigned int tx_max_fifo_size;
1040 	unsigned int rx_max_fifo_size;
1041 	unsigned int tx_tstamp_workaround;
1042 	unsigned int ecc_support;
1043 	unsigned int i2c_support;
1044 	unsigned int irq_reissue_support;
1045 	unsigned int tx_desc_prefetch;
1046 	unsigned int rx_desc_prefetch;
1047 	unsigned int an_cdr_workaround;
1048 	unsigned int enable_rrc;
1049 };
1050 
1051 struct xgbe_prv_data {
1052 	struct net_device *netdev;
1053 	struct pci_dev *pcidev;
1054 	struct platform_device *platdev;
1055 	struct acpi_device *adev;
1056 	struct device *dev;
1057 	struct platform_device *phy_platdev;
1058 	struct device *phy_dev;
1059 
1060 	/* Version related data */
1061 	struct xgbe_version_data *vdata;
1062 
1063 	/* ACPI or DT flag */
1064 	unsigned int use_acpi;
1065 
1066 	/* XGMAC/XPCS related mmio registers */
1067 	void __iomem *xgmac_regs;	/* XGMAC CSRs */
1068 	void __iomem *xpcs_regs;	/* XPCS MMD registers */
1069 	void __iomem *rxtx_regs;	/* SerDes Rx/Tx CSRs */
1070 	void __iomem *sir0_regs;	/* SerDes integration registers (1/2) */
1071 	void __iomem *sir1_regs;	/* SerDes integration registers (2/2) */
1072 	void __iomem *xprop_regs;	/* XGBE property registers */
1073 	void __iomem *xi2c_regs;	/* XGBE I2C CSRs */
1074 
1075 	/* Port property registers */
1076 	unsigned int pp0;
1077 	unsigned int pp1;
1078 	unsigned int pp2;
1079 	unsigned int pp3;
1080 	unsigned int pp4;
1081 
1082 	/* Overall device lock */
1083 	spinlock_t lock;
1084 
1085 	/* XPCS indirect addressing lock */
1086 	spinlock_t xpcs_lock;
1087 	unsigned int xpcs_window_def_reg;
1088 	unsigned int xpcs_window_sel_reg;
1089 	unsigned int xpcs_window;
1090 	unsigned int xpcs_window_size;
1091 	unsigned int xpcs_window_mask;
1092 
1093 	/* RSS addressing mutex */
1094 	struct mutex rss_mutex;
1095 
1096 	/* Flags representing xgbe_state */
1097 	unsigned long dev_state;
1098 
1099 	/* ECC support */
1100 	unsigned long tx_sec_period;
1101 	unsigned long tx_ded_period;
1102 	unsigned long rx_sec_period;
1103 	unsigned long rx_ded_period;
1104 	unsigned long desc_sec_period;
1105 	unsigned long desc_ded_period;
1106 
1107 	unsigned int tx_sec_count;
1108 	unsigned int tx_ded_count;
1109 	unsigned int rx_sec_count;
1110 	unsigned int rx_ded_count;
1111 	unsigned int desc_ded_count;
1112 	unsigned int desc_sec_count;
1113 
1114 	int dev_irq;
1115 	int ecc_irq;
1116 	int i2c_irq;
1117 	int channel_irq[XGBE_MAX_DMA_CHANNELS];
1118 
1119 	unsigned int per_channel_irq;
1120 	unsigned int irq_count;
1121 	unsigned int channel_irq_count;
1122 	unsigned int channel_irq_mode;
1123 
1124 	char ecc_name[IFNAMSIZ + 32];
1125 
1126 	struct xgbe_hw_if hw_if;
1127 	struct xgbe_phy_if phy_if;
1128 	struct xgbe_desc_if desc_if;
1129 	struct xgbe_i2c_if i2c_if;
1130 
1131 	/* AXI DMA settings */
1132 	unsigned int coherent;
1133 	unsigned int arcr;
1134 	unsigned int awcr;
1135 	unsigned int awarcr;
1136 
1137 	/* Service routine support */
1138 	struct workqueue_struct *dev_workqueue;
1139 	struct work_struct service_work;
1140 	struct timer_list service_timer;
1141 
1142 	/* Rings for Tx/Rx on a DMA channel */
1143 	struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1144 	unsigned int tx_max_channel_count;
1145 	unsigned int rx_max_channel_count;
1146 	unsigned int channel_count;
1147 	unsigned int tx_ring_count;
1148 	unsigned int tx_desc_count;
1149 	unsigned int rx_ring_count;
1150 	unsigned int rx_desc_count;
1151 
1152 	unsigned int new_tx_ring_count;
1153 	unsigned int new_rx_ring_count;
1154 
1155 	unsigned int tx_max_q_count;
1156 	unsigned int rx_max_q_count;
1157 	unsigned int tx_q_count;
1158 	unsigned int rx_q_count;
1159 
1160 	/* Tx/Rx common settings */
1161 	unsigned int blen;
1162 	unsigned int pbl;
1163 	unsigned int aal;
1164 	unsigned int rd_osr_limit;
1165 	unsigned int wr_osr_limit;
1166 
1167 	/* Tx settings */
1168 	unsigned int tx_sf_mode;
1169 	unsigned int tx_threshold;
1170 	unsigned int tx_osp_mode;
1171 	unsigned int tx_max_fifo_size;
1172 
1173 	/* Rx settings */
1174 	unsigned int rx_sf_mode;
1175 	unsigned int rx_threshold;
1176 	unsigned int rx_max_fifo_size;
1177 
1178 	/* Tx coalescing settings */
1179 	unsigned int tx_usecs;
1180 	unsigned int tx_frames;
1181 
1182 	/* Rx coalescing settings */
1183 	unsigned int rx_riwt;
1184 	unsigned int rx_usecs;
1185 	unsigned int rx_frames;
1186 
1187 	/* Current Rx buffer size */
1188 	unsigned int rx_buf_size;
1189 
1190 	/* Flow control settings */
1191 	unsigned int pause_autoneg;
1192 	unsigned int tx_pause;
1193 	unsigned int rx_pause;
1194 	unsigned int rx_rfa[XGBE_MAX_QUEUES];
1195 	unsigned int rx_rfd[XGBE_MAX_QUEUES];
1196 
1197 	/* Receive Side Scaling settings */
1198 	u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
1199 	u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1200 	u32 rss_options;
1201 
1202 	/* VXLAN settings */
1203 	u16 vxlan_port;
1204 
1205 	/* Netdev related settings */
1206 	unsigned char mac_addr[ETH_ALEN];
1207 	netdev_features_t netdev_features;
1208 	struct napi_struct napi;
1209 	struct xgbe_mmc_stats mmc_stats;
1210 	struct xgbe_ext_stats ext_stats;
1211 
1212 	/* Filtering support */
1213 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1214 
1215 	/* Device clocks */
1216 	struct clk *sysclk;
1217 	unsigned long sysclk_rate;
1218 	struct clk *ptpclk;
1219 	unsigned long ptpclk_rate;
1220 
1221 	/* Timestamp support */
1222 	spinlock_t tstamp_lock;
1223 	struct ptp_clock_info ptp_clock_info;
1224 	struct ptp_clock *ptp_clock;
1225 	struct hwtstamp_config tstamp_config;
1226 	struct cyclecounter tstamp_cc;
1227 	struct timecounter tstamp_tc;
1228 	unsigned int tstamp_addend;
1229 	struct work_struct tx_tstamp_work;
1230 	struct sk_buff *tx_tstamp_skb;
1231 	u64 tx_tstamp;
1232 
1233 	/* DCB support */
1234 	struct ieee_ets *ets;
1235 	struct ieee_pfc *pfc;
1236 	unsigned int q2tc_map[XGBE_MAX_QUEUES];
1237 	unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1238 	unsigned int pfcq[XGBE_MAX_QUEUES];
1239 	unsigned int pfc_rfa;
1240 	u8 num_tcs;
1241 
1242 	/* Hardware features of the device */
1243 	struct xgbe_hw_features hw_feat;
1244 
1245 	/* Device work structures */
1246 	struct work_struct restart_work;
1247 	struct work_struct stopdev_work;
1248 
1249 	/* Keeps track of power mode */
1250 	unsigned int power_down;
1251 
1252 	/* Network interface message level setting */
1253 	u32 msg_enable;
1254 
1255 	/* Current PHY settings */
1256 	phy_interface_t phy_mode;
1257 	int phy_link;
1258 	int phy_speed;
1259 
1260 	/* MDIO/PHY related settings */
1261 	unsigned int phy_started;
1262 	void *phy_data;
1263 	struct xgbe_phy phy;
1264 	int mdio_mmd;
1265 	unsigned long link_check;
1266 	struct completion mdio_complete;
1267 
1268 	unsigned int kr_redrv;
1269 
1270 	char an_name[IFNAMSIZ + 32];
1271 	struct workqueue_struct *an_workqueue;
1272 
1273 	int an_irq;
1274 	struct work_struct an_irq_work;
1275 
1276 	/* Auto-negotiation state machine support */
1277 	unsigned int an_int;
1278 	unsigned int an_status;
1279 	struct mutex an_mutex;
1280 	enum xgbe_an an_result;
1281 	enum xgbe_an an_state;
1282 	enum xgbe_rx kr_state;
1283 	enum xgbe_rx kx_state;
1284 	struct work_struct an_work;
1285 	unsigned int an_again;
1286 	unsigned int an_supported;
1287 	unsigned int parallel_detect;
1288 	unsigned int fec_ability;
1289 	unsigned long an_start;
1290 	unsigned long kr_start_time;
1291 	enum xgbe_an_mode an_mode;
1292 
1293 	/* I2C support */
1294 	struct xgbe_i2c i2c;
1295 	struct mutex i2c_mutex;
1296 	struct completion i2c_complete;
1297 	char i2c_name[IFNAMSIZ + 32];
1298 
1299 	unsigned int lpm_ctrl;		/* CTRL1 for resume */
1300 
1301 	unsigned int isr_as_tasklet;
1302 	struct tasklet_struct tasklet_dev;
1303 	struct tasklet_struct tasklet_ecc;
1304 	struct tasklet_struct tasklet_i2c;
1305 	struct tasklet_struct tasklet_an;
1306 
1307 	struct dentry *xgbe_debugfs;
1308 
1309 	unsigned int debugfs_xgmac_reg;
1310 
1311 	unsigned int debugfs_xpcs_mmd;
1312 	unsigned int debugfs_xpcs_reg;
1313 
1314 	unsigned int debugfs_xprop_reg;
1315 
1316 	unsigned int debugfs_xi2c_reg;
1317 
1318 	bool debugfs_an_cdr_workaround;
1319 	bool debugfs_an_cdr_track_early;
1320 	bool en_rx_adap;
1321 	int rx_adapt_retries;
1322 	bool rx_adapt_done;
1323 	bool mode_set;
1324 };
1325 
1326 /* Function prototypes*/
1327 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
1328 void xgbe_free_pdata(struct xgbe_prv_data *);
1329 void xgbe_set_counts(struct xgbe_prv_data *);
1330 int xgbe_config_netdev(struct xgbe_prv_data *);
1331 void xgbe_deconfig_netdev(struct xgbe_prv_data *);
1332 
1333 int xgbe_platform_init(void);
1334 void xgbe_platform_exit(void);
1335 #ifdef CONFIG_PCI
1336 int xgbe_pci_init(void);
1337 void xgbe_pci_exit(void);
1338 #else
xgbe_pci_init(void)1339 static inline int xgbe_pci_init(void) { return 0; }
xgbe_pci_exit(void)1340 static inline void xgbe_pci_exit(void) { }
1341 #endif
1342 
1343 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1344 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1345 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1346 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1347 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1348 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1349 const struct net_device_ops *xgbe_get_netdev_ops(void);
1350 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1351 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void);
1352 
1353 #ifdef CONFIG_AMD_XGBE_DCB
1354 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1355 #endif
1356 
1357 void xgbe_ptp_register(struct xgbe_prv_data *);
1358 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1359 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1360 		       unsigned int, unsigned int, unsigned int);
1361 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1362 		       unsigned int);
1363 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1364 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1365 int xgbe_powerup(struct net_device *, unsigned int);
1366 int xgbe_powerdown(struct net_device *, unsigned int);
1367 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1368 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1369 void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1370 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1371 
1372 #ifdef CONFIG_DEBUG_FS
1373 void xgbe_debugfs_init(struct xgbe_prv_data *);
1374 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1375 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata);
1376 #else
xgbe_debugfs_init(struct xgbe_prv_data * pdata)1377 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_exit(struct xgbe_prv_data * pdata)1378 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_rename(struct xgbe_prv_data * pdata)1379 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {}
1380 #endif /* CONFIG_DEBUG_FS */
1381 
1382 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1383 #if 0
1384 #define YDEBUG
1385 #define YDEBUG_MDIO
1386 #endif
1387 
1388 /* For debug prints */
1389 #ifdef YDEBUG
1390 #define DBGPR(x...) pr_alert(x)
1391 #else
1392 #define DBGPR(x...) do { } while (0)
1393 #endif
1394 
1395 #ifdef YDEBUG_MDIO
1396 #define DBGPR_MDIO(x...) pr_alert(x)
1397 #else
1398 #define DBGPR_MDIO(x...) do { } while (0)
1399 #endif
1400 
1401 #endif
1402