xref: /openbmc/u-boot/include/fsl_esdhc.h (revision 748ad078)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * FSL SD/MMC Defines
4  *-------------------------------------------------------------------
5  *
6  * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
7  */
8 
9 #ifndef  __FSL_ESDHC_H__
10 #define	__FSL_ESDHC_H__
11 
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <asm/byteorder.h>
15 
16 /* needed for the mmc_cfg definition */
17 #include <mmc.h>
18 
19 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
20 #include "../board/freescale/common/qixis.h"
21 #endif
22 
23 /* FSL eSDHC-specific constants */
24 #define SYSCTL			0x0002e02c
25 #define SYSCTL_INITA		0x08000000
26 #define SYSCTL_TIMEOUT_MASK	0x000f0000
27 #define SYSCTL_CLOCK_MASK	0x0000fff0
28 #if !defined(CONFIG_FSL_USDHC)
29 #define SYSCTL_CKEN		0x00000008
30 #define SYSCTL_PEREN		0x00000004
31 #define SYSCTL_HCKEN		0x00000002
32 #define SYSCTL_IPGEN		0x00000001
33 #endif
34 #define SYSCTL_RSTA		0x01000000
35 #define SYSCTL_RSTC		0x02000000
36 #define SYSCTL_RSTD		0x04000000
37 
38 #define VENDORSPEC_CKEN		0x00004000
39 #define VENDORSPEC_PEREN	0x00002000
40 #define VENDORSPEC_HCKEN	0x00001000
41 #define VENDORSPEC_IPGEN	0x00000800
42 #define VENDORSPEC_INIT		0x20007809
43 
44 #define IRQSTAT			0x0002e030
45 #define IRQSTAT_DMAE		(0x10000000)
46 #define IRQSTAT_AC12E		(0x01000000)
47 #define IRQSTAT_DEBE		(0x00400000)
48 #define IRQSTAT_DCE		(0x00200000)
49 #define IRQSTAT_DTOE		(0x00100000)
50 #define IRQSTAT_CIE		(0x00080000)
51 #define IRQSTAT_CEBE		(0x00040000)
52 #define IRQSTAT_CCE		(0x00020000)
53 #define IRQSTAT_CTOE		(0x00010000)
54 #define IRQSTAT_CINT		(0x00000100)
55 #define IRQSTAT_CRM		(0x00000080)
56 #define IRQSTAT_CINS		(0x00000040)
57 #define IRQSTAT_BRR		(0x00000020)
58 #define IRQSTAT_BWR		(0x00000010)
59 #define IRQSTAT_DINT		(0x00000008)
60 #define IRQSTAT_BGE		(0x00000004)
61 #define IRQSTAT_TC		(0x00000002)
62 #define IRQSTAT_CC		(0x00000001)
63 
64 #define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
65 #define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
66 				IRQSTAT_DMAE)
67 #define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
68 
69 #define IRQSTATEN		0x0002e034
70 #define IRQSTATEN_DMAE		(0x10000000)
71 #define IRQSTATEN_AC12E		(0x01000000)
72 #define IRQSTATEN_DEBE		(0x00400000)
73 #define IRQSTATEN_DCE		(0x00200000)
74 #define IRQSTATEN_DTOE		(0x00100000)
75 #define IRQSTATEN_CIE		(0x00080000)
76 #define IRQSTATEN_CEBE		(0x00040000)
77 #define IRQSTATEN_CCE		(0x00020000)
78 #define IRQSTATEN_CTOE		(0x00010000)
79 #define IRQSTATEN_CINT		(0x00000100)
80 #define IRQSTATEN_CRM		(0x00000080)
81 #define IRQSTATEN_CINS		(0x00000040)
82 #define IRQSTATEN_BRR		(0x00000020)
83 #define IRQSTATEN_BWR		(0x00000010)
84 #define IRQSTATEN_DINT		(0x00000008)
85 #define IRQSTATEN_BGE		(0x00000004)
86 #define IRQSTATEN_TC		(0x00000002)
87 #define IRQSTATEN_CC		(0x00000001)
88 
89 #define ESDHCCTL		0x0002e40c
90 #define ESDHCCTL_PCS		(0x00080000)
91 
92 #define PRSSTAT			0x0002e024
93 #define PRSSTAT_DAT0		(0x01000000)
94 #define PRSSTAT_CLSL		(0x00800000)
95 #define PRSSTAT_WPSPL		(0x00080000)
96 #define PRSSTAT_CDPL		(0x00040000)
97 #define PRSSTAT_CINS		(0x00010000)
98 #define PRSSTAT_BREN		(0x00000800)
99 #define PRSSTAT_BWEN		(0x00000400)
100 #define PRSSTAT_SDSTB		(0X00000008)
101 #define PRSSTAT_DLA		(0x00000004)
102 #define PRSSTAT_CICHB		(0x00000002)
103 #define PRSSTAT_CIDHB		(0x00000001)
104 
105 #define PROCTL			0x0002e028
106 #define PROCTL_INIT		0x00000020
107 #define PROCTL_DTW_4		0x00000002
108 #define PROCTL_DTW_8		0x00000004
109 #define PROCTL_D3CD		0x00000008
110 
111 #define CMDARG			0x0002e008
112 
113 #define XFERTYP			0x0002e00c
114 #define XFERTYP_CMD(x)		((x & 0x3f) << 24)
115 #define XFERTYP_CMDTYP_NORMAL	0x0
116 #define XFERTYP_CMDTYP_SUSPEND	0x00400000
117 #define XFERTYP_CMDTYP_RESUME	0x00800000
118 #define XFERTYP_CMDTYP_ABORT	0x00c00000
119 #define XFERTYP_DPSEL		0x00200000
120 #define XFERTYP_CICEN		0x00100000
121 #define XFERTYP_CCCEN		0x00080000
122 #define XFERTYP_RSPTYP_NONE	0
123 #define XFERTYP_RSPTYP_136	0x00010000
124 #define XFERTYP_RSPTYP_48	0x00020000
125 #define XFERTYP_RSPTYP_48_BUSY	0x00030000
126 #define XFERTYP_MSBSEL		0x00000020
127 #define XFERTYP_DTDSEL		0x00000010
128 #define XFERTYP_DDREN		0x00000008
129 #define XFERTYP_AC12EN		0x00000004
130 #define XFERTYP_BCEN		0x00000002
131 #define XFERTYP_DMAEN		0x00000001
132 
133 #define CINS_TIMEOUT		1000
134 #define PIO_TIMEOUT		500
135 
136 #define DSADDR		0x2e004
137 
138 #define CMDRSP0		0x2e010
139 #define CMDRSP1		0x2e014
140 #define CMDRSP2		0x2e018
141 #define CMDRSP3		0x2e01c
142 
143 #define DATPORT		0x2e020
144 
145 #define WML		0x2e044
146 #define WML_WRITE	0x00010000
147 #ifdef CONFIG_FSL_SDHC_V2_3
148 #define WML_RD_WML_MAX		0x80
149 #define WML_WR_WML_MAX		0x80
150 #define WML_RD_WML_MAX_VAL	0x0
151 #define WML_WR_WML_MAX_VAL	0x0
152 #define WML_RD_WML_MASK		0x7f
153 #define WML_WR_WML_MASK		0x7f0000
154 #else
155 #define WML_RD_WML_MAX		0x10
156 #define WML_WR_WML_MAX		0x80
157 #define WML_RD_WML_MAX_VAL	0x10
158 #define WML_WR_WML_MAX_VAL	0x80
159 #define WML_RD_WML_MASK	0xff
160 #define WML_WR_WML_MASK	0xff0000
161 #endif
162 
163 #define BLKATTR		0x2e004
164 #define BLKATTR_CNT(x)	((x & 0xffff) << 16)
165 #define BLKATTR_SIZE(x)	(x & 0x1fff)
166 #define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
167 
168 #define ESDHC_HOSTCAPBLT_VS18	0x04000000
169 #define ESDHC_HOSTCAPBLT_VS30	0x02000000
170 #define ESDHC_HOSTCAPBLT_VS33	0x01000000
171 #define ESDHC_HOSTCAPBLT_SRS	0x00800000
172 #define ESDHC_HOSTCAPBLT_DMAS	0x00400000
173 #define ESDHC_HOSTCAPBLT_HSS	0x00200000
174 
175 #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
176 
177 /* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
178 #define	MIX_CTRL_DDREN		BIT(3)
179 #define MIX_CTRL_DTDSEL_READ	BIT(4)
180 #define	MIX_CTRL_AC23EN		BIT(7)
181 #define	MIX_CTRL_EXE_TUNE	BIT(22)
182 #define	MIX_CTRL_SMPCLK_SEL	BIT(23)
183 #define	MIX_CTRL_AUTO_TUNE_EN	BIT(24)
184 #define	MIX_CTRL_FBCLK_SEL	BIT(25)
185 #define	MIX_CTRL_HS400_EN	BIT(26)
186 #define	MIX_CTRL_HS400_ES	BIT(27)
187 /* Bits 3 and 6 are not SDHCI standard definitions */
188 #define	MIX_CTRL_SDHCI_MASK	0xb7
189 /* Tuning bits */
190 #define	MIX_CTRL_TUNING_MASK	0x03c00000
191 
192 /* strobe dll register */
193 #define ESDHC_STROBE_DLL_CTRL		0x70
194 #define ESDHC_STROBE_DLL_CTRL_ENABLE	BIT(0)
195 #define ESDHC_STROBE_DLL_CTRL_RESET	BIT(1)
196 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
197 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
198 
199 #define ESDHC_STROBE_DLL_STATUS		0x74
200 #define ESDHC_STROBE_DLL_STS_REF_LOCK	BIT(1)
201 #define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
202 #define ESDHC_STROBE_DLL_CLK_FREQ	100000000
203 
204 #define ESDHC_STD_TUNING_EN             BIT(24)
205 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
206 #define ESDHC_TUNING_START_TAP_DEFAULT	0x1
207 #define ESDHC_TUNING_START_TAP_MASK	0xff
208 #define ESDHC_TUNING_STEP_MASK		0x00070000
209 #define ESDHC_TUNING_STEP_SHIFT		16
210 
211 #define	ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
212 #define	ESDHC_FLAG_ENGCM07207		BIT(2)
213 #define	ESDHC_FLAG_USDHC		BIT(3)
214 #define	ESDHC_FLAG_MAN_TUNING		BIT(4)
215 #define	ESDHC_FLAG_STD_TUNING		BIT(5)
216 #define	ESDHC_FLAG_HAVE_CAP1		BIT(6)
217 #define	ESDHC_FLAG_ERR004536		BIT(7)
218 #define	ESDHC_FLAG_HS200		BIT(8)
219 #define	ESDHC_FLAG_HS400		BIT(9)
220 #define	ESDHC_FLAG_ERR010450		BIT(10)
221 #define	ESDHC_FLAG_HS400_ES		BIT(11)
222 
223 struct fsl_esdhc_cfg {
224 	phys_addr_t esdhc_base;
225 	u32	sdhc_clk;
226 	u8	max_bus_width;
227 	int	wp_enable;
228 	int	vs18_enable; /* Use 1.8V if set to 1 */
229 	struct mmc_config cfg;
230 };
231 
232 /* Select the correct accessors depending on endianess */
233 #if defined CONFIG_SYS_FSL_ESDHC_LE
234 #define esdhc_read32		in_le32
235 #define esdhc_write32		out_le32
236 #define esdhc_clrsetbits32	clrsetbits_le32
237 #define esdhc_clrbits32		clrbits_le32
238 #define esdhc_setbits32		setbits_le32
239 #elif defined(CONFIG_SYS_FSL_ESDHC_BE)
240 #define esdhc_read32            in_be32
241 #define esdhc_write32           out_be32
242 #define esdhc_clrsetbits32      clrsetbits_be32
243 #define esdhc_clrbits32         clrbits_be32
244 #define esdhc_setbits32         setbits_be32
245 #elif __BYTE_ORDER == __LITTLE_ENDIAN
246 #define esdhc_read32		in_le32
247 #define esdhc_write32		out_le32
248 #define esdhc_clrsetbits32	clrsetbits_le32
249 #define esdhc_clrbits32		clrbits_le32
250 #define esdhc_setbits32		setbits_le32
251 #elif __BYTE_ORDER == __BIG_ENDIAN
252 #define esdhc_read32		in_be32
253 #define esdhc_write32		out_be32
254 #define esdhc_clrsetbits32	clrsetbits_be32
255 #define esdhc_clrbits32		clrbits_be32
256 #define esdhc_setbits32		setbits_be32
257 #else
258 #error "Endianess is not defined: please fix to continue"
259 #endif
260 
261 #ifdef CONFIG_FSL_ESDHC
262 int fsl_esdhc_mmc_init(bd_t *bis);
263 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
264 void fdt_fixup_esdhc(void *blob, bd_t *bd);
265 #else
fsl_esdhc_mmc_init(bd_t * bis)266 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
fdt_fixup_esdhc(void * blob,bd_t * bd)267 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
268 #endif /* CONFIG_FSL_ESDHC */
269 void __noreturn mmc_boot(void);
270 void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
271 
272 #endif  /* __FSL_ESDHC_H__ */
273