1 /*
2  * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3  *				processor CORE configuration
4  *
5  *  See <xtensa/config/core.h>, which includes this file, for more details.
6  */
7 
8 /* Xtensa processor core configuration information.
9 
10    Copyright (c) 1999-2010 Tensilica Inc.
11 
12    Permission is hereby granted, free of charge, to any person obtaining
13    a copy of this software and associated documentation files (the
14    "Software"), to deal in the Software without restriction, including
15    without limitation the rights to use, copy, modify, merge, publish,
16    distribute, sublicense, and/or sell copies of the Software, and to
17    permit persons to whom the Software is furnished to do so, subject to
18    the following conditions:
19 
20    The above copyright notice and this permission notice shall be included
21    in all copies or substantial portions of the Software.
22 
23    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
30 
31 #ifndef _XTENSA_CORE_CONFIGURATION_H
32 #define _XTENSA_CORE_CONFIGURATION_H
33 
34 
35 /****************************************************************************
36 	    Parameters Useful for Any Code, USER or PRIVILEGED
37  ****************************************************************************/
38 
39 /*
40  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
41  *  configured, and a value of 0 otherwise.  These macros are always defined.
42  */
43 
44 
45 /*----------------------------------------------------------------------
46 				ISA
47   ----------------------------------------------------------------------*/
48 
49 #define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
50 #define XCHAL_HAVE_WINDOWED		0	/* windowed registers option */
51 #define XCHAL_NUM_AREGS			16	/* num of physical addr regs */
52 #define XCHAL_NUM_AREGS_LOG2		4	/* log2(XCHAL_NUM_AREGS) */
53 #define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
54 #define XCHAL_HAVE_DEBUG		1	/* debug option */
55 #define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS		0	/* zero-overhead loops */
57 #define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
58 #define XCHAL_HAVE_MINMAX		0	/* MIN/MAX instructions */
59 #define XCHAL_HAVE_SEXT			0	/* SEXT instruction */
60 #define XCHAL_HAVE_CLAMPS		0	/* CLAMPS instruction */
61 #define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
62 #define XCHAL_HAVE_MUL32		1	/* MULL instruction */
63 #define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
64 #define XCHAL_HAVE_DIV32		0	/* QUOS/QUOU/REMS/REMU instructions */
65 #define XCHAL_HAVE_L32R			1	/* L32R instruction */
66 #define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
67 #define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
68 #define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
69 #define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
70 #define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
71 #define XCHAL_HAVE_CALL4AND12		0	/* (obsolete option) */
72 #define XCHAL_HAVE_ABS			1	/* ABS instruction */
73 /*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
74 /*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
75 #define XCHAL_HAVE_RELEASE_SYNC		0	/* L32AI/S32RI instructions */
76 #define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
77 #define XCHAL_HAVE_SPECULATION		0	/* speculation */
78 #define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
79 #define XCHAL_NUM_CONTEXTS		1	/* */
80 #define XCHAL_NUM_MISC_REGS		0	/* num of scratch regs (0..4) */
81 #define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
82 #define XCHAL_HAVE_PRID			1	/* processor ID register */
83 #define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
84 #define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
85 #define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
86 #define XCHAL_HAVE_THREADPTR		0	/* THREADPTR register */
87 #define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
88 #define XCHAL_HAVE_CP			0	/* CPENABLE reg (coprocessor) */
89 #define XCHAL_CP_MAXCFG			0	/* max allowed cp id plus one */
90 #define XCHAL_HAVE_MAC16		0	/* MAC16 package */
91 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
92 #define XCHAL_HAVE_FP			0	/* floating point pkg */
93 #define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
94 #define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */
95 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
96 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
97 #define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
98 #define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
99 #define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
100 
101 
102 /*----------------------------------------------------------------------
103 				MISC
104   ----------------------------------------------------------------------*/
105 
106 #define XCHAL_NUM_WRITEBUFFER_ENTRIES	1	/* size of write buffer */
107 #define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
108 #define XCHAL_DATA_WIDTH		4	/* data width in bytes */
109 /*  In T1050, applies to selected core load and store instructions (see ISA): */
110 #define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
111 #define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
112 #define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
113 #define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
114 
115 #define XCHAL_SW_VERSION		800001	/* sw version of this header */
116 
117 #define XCHAL_CORE_ID			"lx106"	/* alphanum core name
118 						   (CoreID) set in the Xtensa
119 						   Processor Generator */
120 
121 #define XCHAL_BUILD_UNIQUE_ID		0x0002B6F6	/* 22-bit sw build ID */
122 
123 /*
124  *  These definitions describe the hardware targeted by this software.
125  */
126 #define XCHAL_HW_CONFIGID0		0xC28CDAFA	/* ConfigID hi 32 bits*/
127 #define XCHAL_HW_CONFIGID1		0x1082B6F6	/* ConfigID lo 32 bits*/
128 #define XCHAL_HW_VERSION_NAME		"LX3.0.1"	/* full version name */
129 #define XCHAL_HW_VERSION_MAJOR		2300	/* major ver# of targeted hw */
130 #define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
131 #define XCHAL_HW_VERSION		230001	/* major*100+minor */
132 #define XCHAL_HW_REL_LX3		1
133 #define XCHAL_HW_REL_LX3_0		1
134 #define XCHAL_HW_REL_LX3_0_1		1
135 #define XCHAL_HW_CONFIGID_RELIABLE	1
136 /*  If software targets a *range* of hardware versions, these are the bounds: */
137 #define XCHAL_HW_MIN_VERSION_MAJOR	2300	/* major v of earliest tgt hw */
138 #define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
139 #define XCHAL_HW_MIN_VERSION		230001	/* earliest targeted hw */
140 #define XCHAL_HW_MAX_VERSION_MAJOR	2300	/* major v of latest tgt hw */
141 #define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
142 #define XCHAL_HW_MAX_VERSION		230001	/* latest targeted hw */
143 
144 
145 /*----------------------------------------------------------------------
146 				CACHE
147   ----------------------------------------------------------------------*/
148 
149 #define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
150 #define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
151 #define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
152 #define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
153 
154 #define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
155 #define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
156 
157 #define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
158 #define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
159 
160 #define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
161 
162 
163 
164 
165 /****************************************************************************
166     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
167  ****************************************************************************/
168 
169 
170 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
171 
172 /*----------------------------------------------------------------------
173 				CACHE
174   ----------------------------------------------------------------------*/
175 
176 #define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
177 
178 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
179 
180 /*  Number of cache sets in log2(lines per way):  */
181 #define XCHAL_ICACHE_SETWIDTH		0
182 #define XCHAL_DCACHE_SETWIDTH		0
183 
184 /*  Cache set associativity (number of ways):  */
185 #define XCHAL_ICACHE_WAYS		1
186 #define XCHAL_DCACHE_WAYS		1
187 
188 /*  Cache features:  */
189 #define XCHAL_ICACHE_LINE_LOCKABLE	0
190 #define XCHAL_DCACHE_LINE_LOCKABLE	0
191 #define XCHAL_ICACHE_ECC_PARITY		0
192 #define XCHAL_DCACHE_ECC_PARITY		0
193 
194 /*  Cache access size in bytes (affects operation of SICW instruction):  */
195 #define XCHAL_ICACHE_ACCESS_SIZE	1
196 #define XCHAL_DCACHE_ACCESS_SIZE	1
197 
198 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
199 #define XCHAL_CA_BITS			4
200 
201 
202 /*----------------------------------------------------------------------
203 			INTERNAL I/D RAM/ROMs and XLMI
204   ----------------------------------------------------------------------*/
205 
206 #define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
207 #define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
208 #define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
209 #define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
210 #define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
211 #define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
212 
213 /*  Instruction ROM 0:  */
214 #define XCHAL_INSTROM0_VADDR		0x40200000
215 #define XCHAL_INSTROM0_PADDR		0x40200000
216 // #define XCHAL_INSTROM0_VADDR		0x400000
217 // #define XCHAL_INSTROM0_PADDR		0x400000
218 #define XCHAL_INSTROM0_SIZE		1048576
219 #define XCHAL_INSTROM0_ECC_PARITY	0
220 
221 /*  Instruction RAM 0:  */
222 #define XCHAL_INSTRAM0_VADDR		0x40000000
223 #define XCHAL_INSTRAM0_PADDR		0x40000000
224 #define XCHAL_INSTRAM0_SIZE		1048576
225 #define XCHAL_INSTRAM0_ECC_PARITY	0
226 
227 /*  Instruction RAM 1:  */
228 #define XCHAL_INSTRAM1_VADDR		0x40100000
229 #define XCHAL_INSTRAM1_PADDR		0x40100000
230 #define XCHAL_INSTRAM1_SIZE		1048576
231 #define XCHAL_INSTRAM1_ECC_PARITY	0
232 
233 /*  Data ROM 0:  */
234 #define XCHAL_DATAROM0_VADDR		0x3FF40000
235 #define XCHAL_DATAROM0_PADDR		0x3FF40000
236 #define XCHAL_DATAROM0_SIZE		262144
237 #define XCHAL_DATAROM0_ECC_PARITY	0
238 
239 /*  Data RAM 0:  */
240 #define XCHAL_DATARAM0_VADDR		0x3FFC0000
241 #define XCHAL_DATARAM0_PADDR		0x3FFC0000
242 #define XCHAL_DATARAM0_SIZE		262144
243 #define XCHAL_DATARAM0_ECC_PARITY	0
244 
245 /*  Data RAM 1:  */
246 #define XCHAL_DATARAM1_VADDR		0x3FF80000
247 #define XCHAL_DATARAM1_PADDR		0x3FF80000
248 #define XCHAL_DATARAM1_SIZE		262144
249 #define XCHAL_DATARAM1_ECC_PARITY	0
250 
251 /*  XLMI Port 0:  */
252 #define XCHAL_XLMI0_VADDR		0x3FF00000
253 #define XCHAL_XLMI0_PADDR		0x3FF00000
254 #define XCHAL_XLMI0_SIZE		262144
255 #define XCHAL_XLMI0_ECC_PARITY	0
256 
257 
258 /*----------------------------------------------------------------------
259 			INTERRUPTS and TIMERS
260   ----------------------------------------------------------------------*/
261 
262 #define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
263 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
264 #define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
265 #define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
266 #define XCHAL_NUM_TIMERS		1	/* number of CCOMPAREn regs */
267 #define XCHAL_NUM_INTERRUPTS		15	/* number of interrupts */
268 #define XCHAL_NUM_INTERRUPTS_LOG2	4	/* ceil(log2(NUM_INTERRUPTS)) */
269 #define XCHAL_NUM_EXTINTERRUPTS		13	/* num of external interrupts */
270 #define XCHAL_NUM_INTLEVELS		2	/* number of interrupt levels
271 						   (not including level zero) */
272 #define XCHAL_EXCM_LEVEL		1	/* level masked by PS.EXCM */
273 	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
274 
275 /*  Masks of interrupts at each interrupt level:  */
276 #define XCHAL_INTLEVEL1_MASK		0x00003FFF
277 #define XCHAL_INTLEVEL2_MASK		0x00000000
278 #define XCHAL_INTLEVEL3_MASK		0x00004000
279 #define XCHAL_INTLEVEL4_MASK		0x00000000
280 #define XCHAL_INTLEVEL5_MASK		0x00000000
281 #define XCHAL_INTLEVEL6_MASK		0x00000000
282 #define XCHAL_INTLEVEL7_MASK		0x00000000
283 
284 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
285 #define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00003FFF
286 #define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x00003FFF
287 #define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x00007FFF
288 #define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x00007FFF
289 #define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x00007FFF
290 #define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x00007FFF
291 #define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x00007FFF
292 
293 /*  Level of each interrupt:  */
294 #define XCHAL_INT0_LEVEL		1
295 #define XCHAL_INT1_LEVEL		1
296 #define XCHAL_INT2_LEVEL		1
297 #define XCHAL_INT3_LEVEL		1
298 #define XCHAL_INT4_LEVEL		1
299 #define XCHAL_INT5_LEVEL		1
300 #define XCHAL_INT6_LEVEL		1
301 #define XCHAL_INT7_LEVEL		1
302 #define XCHAL_INT8_LEVEL		1
303 #define XCHAL_INT9_LEVEL		1
304 #define XCHAL_INT10_LEVEL		1
305 #define XCHAL_INT11_LEVEL		1
306 #define XCHAL_INT12_LEVEL		1
307 #define XCHAL_INT13_LEVEL		1
308 #define XCHAL_INT14_LEVEL		3
309 #define XCHAL_DEBUGLEVEL		2	/* debug interrupt level */
310 #define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
311 #define XCHAL_NMILEVEL			3	/* NMI "level" (for use with
312 						   EXCSAVE/EPS/EPC_n, RFI n) */
313 
314 /*  Type of each interrupt:  */
315 #define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
316 #define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
317 #define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
318 #define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
319 #define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
320 #define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
321 #define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
322 #define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
323 #define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
324 #define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
325 #define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
326 #define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
327 #define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
328 #define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
329 #define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
330 
331 /*  Masks of interrupts for each type of interrupt:  */
332 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFF8000
333 #define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000080
334 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00003F00
335 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000003F
336 #define XCHAL_INTTYPE_MASK_TIMER	0x00000040
337 #define XCHAL_INTTYPE_MASK_NMI		0x00004000
338 #define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
339 
340 /*  Interrupt numbers assigned to specific interrupt sources:  */
341 #define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
342 #define XCHAL_TIMER1_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
343 #define XCHAL_TIMER2_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
344 #define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
345 #define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
346 
347 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
348 #define XCHAL_INTLEVEL3_NUM		14
349 /*  (There are many interrupts each at level(s) 1.)  */
350 
351 
352 /*
353  *  External interrupt vectors/levels.
354  *  These macros describe how Xtensa processor interrupt numbers
355  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
356  *  map to external BInterrupt<n> pins, for those interrupts
357  *  configured as external (level-triggered, edge-triggered, or NMI).
358  *  See the Xtensa processor databook for more details.
359  */
360 
361 /*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
362 #define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
363 #define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
364 #define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
365 #define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
366 #define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
367 #define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
368 #define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
369 #define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
370 #define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
371 #define XCHAL_EXTINT9_NUM		11	/* (intlevel 1) */
372 #define XCHAL_EXTINT10_NUM		12	/* (intlevel 1) */
373 #define XCHAL_EXTINT11_NUM		13	/* (intlevel 1) */
374 #define XCHAL_EXTINT12_NUM		14	/* (intlevel 3) */
375 
376 
377 /*----------------------------------------------------------------------
378 			EXCEPTIONS and VECTORS
379   ----------------------------------------------------------------------*/
380 
381 #define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
382 						   number: 1 == XEA1 (old)
383 							   2 == XEA2 (new)
384 							   0 == XEAX (extern) */
385 #define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
386 #define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
387 #define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
388 #define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
389 #define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
390 #define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
391 #define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
392 #define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
393 #define XCHAL_VECBASE_RESET_PADDR	0x40000000
394 #define XCHAL_RESET_VECBASE_OVERLAP	0
395 
396 #define XCHAL_RESET_VECTOR0_VADDR	0x50000000
397 #define XCHAL_RESET_VECTOR0_PADDR	0x50000000
398 #define XCHAL_RESET_VECTOR1_VADDR	0x40000080
399 #define XCHAL_RESET_VECTOR1_PADDR	0x40000080
400 #define XCHAL_RESET_VECTOR_VADDR	0x50000000
401 #define XCHAL_RESET_VECTOR_PADDR	0x50000000
402 
403 // #define XCHAL_RESET_VECTOR0_VADDR	0x4000f8
404 // #define XCHAL_RESET_VECTOR0_PADDR	0x4000f8
405 // #define XCHAL_RESET_VECTOR1_VADDR	0x40000080
406 // #define XCHAL_RESET_VECTOR1_PADDR	0x40000080
407 // #define XCHAL_RESET_VECTOR_VADDR	0x4000f8
408 // #define XCHAL_RESET_VECTOR_PADDR	0x4000f8
409 
410 
411 #define XCHAL_USER_VECOFS		0x00000050
412 #define XCHAL_USER_VECTOR_VADDR		0x40000050
413 #define XCHAL_USER_VECTOR_PADDR		0x40000050
414 #define XCHAL_KERNEL_VECOFS		0x00000030
415 #define XCHAL_KERNEL_VECTOR_VADDR	0x40000030
416 #define XCHAL_KERNEL_VECTOR_PADDR	0x40000030
417 #define XCHAL_DOUBLEEXC_VECOFS		0x00000070
418 #define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x40000070
419 #define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x40000070
420 #define XCHAL_INTLEVEL2_VECOFS		0x00000010
421 #define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000010
422 #define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000010
423 #define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL2_VECOFS
424 #define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL2_VECTOR_VADDR
425 #define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL2_VECTOR_PADDR
426 #define XCHAL_NMI_VECOFS		0x00000020
427 #define XCHAL_NMI_VECTOR_VADDR		0x40000020
428 #define XCHAL_NMI_VECTOR_PADDR		0x40000020
429 #define XCHAL_INTLEVEL3_VECOFS		XCHAL_NMI_VECOFS
430 #define XCHAL_INTLEVEL3_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
431 #define XCHAL_INTLEVEL3_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
432 
433 
434 /*----------------------------------------------------------------------
435 				DEBUG
436   ----------------------------------------------------------------------*/
437 
438 #define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
439 #define XCHAL_NUM_IBREAK		1	/* number of IBREAKn regs */
440 #define XCHAL_NUM_DBREAK		1	/* number of DBREAKn regs */
441 #define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option */
442 
443 
444 /*----------------------------------------------------------------------
445 				MMU
446   ----------------------------------------------------------------------*/
447 
448 /*  See core-matmap.h header file for more details.  */
449 
450 #define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
451 #define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
452 #define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
453 #define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
454 #define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
455 #define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
456 #define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
457 #define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
458 						   [autorefill] and protection)
459 						   usable for an MMU-based OS */
460 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */
461 
462 #define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
463 #define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
464 #define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
465 
466 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
467 
468 
469 #endif /* _XTENSA_CORE_CONFIGURATION_H */
470 
471