Home
last modified time | relevance | path

Searched defs:XCHAL_ICACHE_LINEWIDTH (Results 1 – 13 of 13) sorted by relevance

/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h118 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h158 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h151 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h122 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h121 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h161 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h140 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h182 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h210 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h188 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h219 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h233 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h282 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro