1 #ifndef CPER_SECTION_ARM_H 2 #define CPER_SECTION_ARM_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #include <json.h> 9 #include "../edk/Cper.h" 10 11 #define ARM_ERROR_VALID_BITFIELD_NAMES \ 12 (const char *[]) \ 13 { \ 14 "mpidrValid", "errorAffinityLevelValid", "runningStateValid", \ 15 "vendorSpecificInfoValid" \ 16 } 17 #define ARM_ERROR_INFO_ENTRY_VALID_BITFIELD_NAMES \ 18 (const char *[]) \ 19 { \ 20 "multipleErrorValid", "flagsValid", "errorInformationValid", \ 21 "virtualFaultAddressValid", \ 22 "physicalFaultAddressValid" \ 23 } 24 #define ARM_ERROR_INFO_ENTRY_FLAGS_NAMES \ 25 (const char *[]) \ 26 { \ 27 "firstErrorCaptured", "lastErrorCaptured", "propagated", \ 28 "overflow" \ 29 } 30 #define ARM_CACHE_TLB_ERROR_VALID_BITFIELD_NAMES \ 31 (const char *[]) \ 32 { \ 33 "transactionTypeValid", "operationValid", "levelValid", \ 34 "processorContextCorruptValid", "correctedValid", \ 35 "precisePCValid", "restartablePCValid" \ 36 } 37 #define ARM_BUS_ERROR_VALID_BITFIELD_NAMES \ 38 (const char *[]) \ 39 { \ 40 "transactionTypeValid", "operationValid", "levelValid", \ 41 "processorContextCorruptValid", "correctedValid", \ 42 "precisePCValid", "restartablePCValid", \ 43 "participationTypeValid", "timedOutValid", \ 44 "addressSpaceValid", "memoryAttributesValid", \ 45 "accessModeValid" \ 46 } 47 #define ARM_ERROR_TRANSACTION_TYPES_KEYS \ 48 (int[]) \ 49 { \ 50 0, 1, 2 \ 51 } 52 #define ARM_ERROR_TRANSACTION_TYPES_VALUES \ 53 (const char *[]) \ 54 { \ 55 "Instruction", "Data Access", "Generic" \ 56 } 57 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_KEYS \ 58 (int[]) \ 59 { \ 60 0, 1, 2, 3 \ 61 } 62 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_VALUES \ 63 (const char *[]) \ 64 { \ 65 "Cache Error", "TLB Error", "Bus Error", \ 66 "Micro-Architectural Error" \ 67 } 68 #define ARM_CACHE_BUS_OPERATION_TYPES_KEYS \ 69 (int[]) \ 70 { \ 71 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 \ 72 } 73 #define ARM_CACHE_BUS_OPERATION_TYPES_VALUES \ 74 (const char *[]) \ 75 { \ 76 "Generic Error", "Generic Read", "Generic Write", "Data Read", \ 77 "Data Write", "Instruction Fetch", "Prefetch", \ 78 "Eviction", "Snooping", "Snooped", "Management" \ 79 } 80 #define ARM_TLB_OPERATION_TYPES_KEYS \ 81 (int[]) \ 82 { \ 83 0, 1, 2, 3, 4, 5, 6, 7, 8 \ 84 } 85 #define ARM_TLB_OPERATION_TYPES_VALUES \ 86 (const char *[]) \ 87 { \ 88 "Generic Error", "Generic Read", "Generic Write", "Data Read", \ 89 "Data Write", "Instruction Fetch", "Prefetch", \ 90 "Local Management Operation", \ 91 "External Management Operation" \ 92 } 93 #define ARM_BUS_PARTICIPATION_TYPES_KEYS \ 94 (int[]) \ 95 { \ 96 0, 1, 2, 3 \ 97 } 98 #define ARM_BUS_PARTICIPATION_TYPES_VALUES \ 99 (const char *[]) \ 100 { \ 101 "Local Processor Originated Request", \ 102 "Local Processor Responded to Request", \ 103 "Local Processor Observed", "Generic" \ 104 } 105 #define ARM_BUS_ADDRESS_SPACE_TYPES_KEYS \ 106 (int[]) \ 107 { \ 108 0, 1, 3 \ 109 } 110 #define ARM_BUS_ADDRESS_SPACE_TYPES_VALUES \ 111 (const char *[]) \ 112 { \ 113 "External Memory Access", "Internal Memory Access", \ 114 "Device Memory Access" \ 115 } 116 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_KEYS \ 117 (int[]) \ 118 { \ 119 0, 1, 2, 3, 4, 5, 6, 7, 8 \ 120 } 121 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_VALUES \ 122 (const char *[]) \ 123 { \ 124 "AArch32 General Purpose Registers", \ 125 "AArch32 EL1 Context Registers", \ 126 "AArch32 EL2 Context Registers", \ 127 "AArch32 Secure Context Registers", \ 128 "AArch64 General Purpose Registers", \ 129 "AArch64 EL1 Context Registers", \ 130 "AArch64 EL2 Context Registers", \ 131 "AArch64 EL3 Context Registers", \ 132 "Miscellaneous System Register Structure" \ 133 } 134 #define ARM_AARCH32_GPR_NAMES \ 135 (const char *[]) \ 136 { \ 137 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 138 "r10", "r11", "r12", "r13_sp", "r14_lr", "r15_pc" \ 139 } 140 #define ARM_AARCH32_EL1_REGISTER_NAMES \ 141 (const char *[]) \ 142 { \ 143 "dfar", "dfsr", "ifar", "isr", "mair0", "mair1", "midr", \ 144 "mpidr", "nmrr", "prrr", "sctlr_ns", "spsr", \ 145 "spsr_abt", "spsr_fiq", "spsr_irq", "spsr_svc", \ 146 "spsr_und", "tpidrprw", "tpidruro", "tpidrurw", \ 147 "ttbcr", "ttbr0", "ttbr1", "dacr" \ 148 } 149 #define ARM_AARCH32_EL2_REGISTER_NAMES \ 150 (const char *[]) \ 151 { \ 152 "elr_hyp", "hamair0", "hamair1", "hcr", "hcr2", "hdfar", \ 153 "hifar", "hpfar", "hsr", "htcr", "htpidr", "httbr", \ 154 "spsr_hyp", "vtcr", "vttbr", "dacr32_el2" \ 155 } 156 #define ARM_AARCH32_SECURE_REGISTER_NAMES \ 157 (const char *[]) \ 158 { \ 159 "sctlr_s", "spsr_mon" \ 160 } 161 #define ARM_AARCH64_GPR_NAMES \ 162 (const char *[]) \ 163 { \ 164 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", \ 165 "x10", "x11", "x12", "x13", "x14", "x15", "x16", \ 166 "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 167 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp" \ 168 } 169 #define ARM_AARCH64_EL1_REGISTER_NAMES \ 170 (const char *[]) \ 171 { \ 172 "elr_el1", "esr_el1", "far_el1", "isr_el1", "mair_el1", \ 173 "midr_el1", "mpidr_el1", "sctlr_el1", "sp_el0", \ 174 "sp_el1", "spsr_el1", "tcr_el1", "tpidr_el0", \ 175 "tpidr_el1", "tpidrro_el0", "ttbr0_el1", "ttbr1_el1" \ 176 } 177 #define ARM_AARCH64_EL2_REGISTER_NAMES \ 178 (const char *[]) \ 179 { \ 180 "elr_el2", "esr_el2", "far_el2", "hacr_el2", "hcr_el2", \ 181 "hpfar_el2", "mair_el2", "sctlr_el2", "sp_el2", \ 182 "spsr_el2", "tcr_el2", "tpidr_el2", "ttbr0_el2", \ 183 "vtcr_el2", "vttbr_el2" \ 184 } 185 #define ARM_AARCH64_EL3_REGISTER_NAMES \ 186 (const char *[]) \ 187 { \ 188 "elr_el3", "esr_el3", "far_el3", "mair_el3", "sctlr_el3", \ 189 "sp_el3", "spsr_el3", "tcr_el3", "tpidr_el3", \ 190 "ttbr0_el3" \ 191 } 192 193 /// 194 /// ARM Processor Error Record 195 /// 196 typedef struct { 197 UINT32 ValidFields; 198 UINT16 ErrInfoNum; 199 UINT16 ContextInfoNum; 200 UINT32 SectionLength; 201 UINT32 ErrorAffinityLevel; 202 UINT64 MPIDR_EL1; 203 UINT64 MIDR_EL1; 204 UINT32 RunningState; 205 UINT32 PsciState; 206 } __attribute__((packed, aligned(1))) EFI_ARM_ERROR_RECORD; 207 208 /// 209 /// ARM Processor Error Information Structure 210 /// 211 #define ARM_ERROR_INFORMATION_TYPE_CACHE 0 212 #define ARM_ERROR_INFORMATION_TYPE_TLB 1 213 #define ARM_ERROR_INFORMATION_TYPE_BUS 2 214 #define ARM_ERROR_INFORMATION_TYPE_MICROARCH 3 215 216 typedef struct { 217 UINT64 ValidationBits : 16; 218 UINT64 TransactionType : 2; 219 UINT64 Operation : 4; 220 UINT64 Level : 3; 221 UINT64 ProcessorContextCorrupt : 1; 222 UINT64 Corrected : 1; 223 UINT64 PrecisePC : 1; 224 UINT64 RestartablePC : 1; 225 UINT64 Reserved : 34; 226 } EFI_ARM_CACHE_ERROR_STRUCTURE; 227 228 typedef struct { 229 UINT64 ValidationBits : 16; 230 UINT64 TransactionType : 2; 231 UINT64 Operation : 4; 232 UINT64 Level : 3; 233 UINT64 ProcessorContextCorrupt : 1; 234 UINT64 Corrected : 1; 235 UINT64 PrecisePC : 1; 236 UINT64 RestartablePC : 1; 237 UINT64 Reserved : 34; 238 } EFI_ARM_TLB_ERROR_STRUCTURE; 239 240 typedef struct { 241 UINT64 ValidationBits : 16; 242 UINT64 TransactionType : 2; 243 UINT64 Operation : 4; 244 UINT64 Level : 3; 245 UINT64 ProcessorContextCorrupt : 1; 246 UINT64 Corrected : 1; 247 UINT64 PrecisePC : 1; 248 UINT64 RestartablePC : 1; 249 UINT64 ParticipationType : 2; 250 UINT64 TimeOut : 1; 251 UINT64 AddressSpace : 2; 252 UINT64 MemoryAddressAttributes : 8; 253 UINT64 AccessMode : 1; 254 UINT64 Reserved : 19; 255 } EFI_ARM_BUS_ERROR_STRUCTURE; 256 257 typedef union { 258 UINT64 Value; 259 EFI_ARM_CACHE_ERROR_STRUCTURE CacheError; 260 EFI_ARM_TLB_ERROR_STRUCTURE TlbError; 261 EFI_ARM_BUS_ERROR_STRUCTURE BusError; 262 } EFI_ARM_ERROR_INFORMATION_STRUCTURE; 263 264 typedef struct { 265 UINT8 Version; 266 UINT8 Length; 267 UINT16 ValidationBits; 268 UINT8 Type; 269 UINT16 MultipleError; 270 UINT8 Flags; 271 EFI_ARM_ERROR_INFORMATION_STRUCTURE ErrorInformation; 272 UINT64 VirtualFaultAddress; 273 UINT64 PhysicalFaultAddress; 274 } __attribute__((packed, aligned(1))) EFI_ARM_ERROR_INFORMATION_ENTRY; 275 276 /// 277 /// ARM Processor Context Information Structure 278 /// 279 typedef struct { 280 UINT16 Version; 281 UINT16 RegisterContextType; 282 UINT32 RegisterArraySize; 283 } __attribute__((packed, aligned(1))) EFI_ARM_CONTEXT_INFORMATION_HEADER; 284 285 /// 286 /// ARM Processor Context Register Types 287 /// 288 #define EFI_ARM_CONTEXT_TYPE_AARCH32_GPR 0 289 #define EFI_ARM_CONTEXT_TYPE_AARCH32_EL1 1 290 #define EFI_ARM_CONTEXT_TYPE_AARCH32_EL2 2 291 #define EFI_ARM_CONTEXT_TYPE_AARCH32_SECURE 3 292 #define EFI_ARM_CONTEXT_TYPE_AARCH64_GPR 4 293 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL1 5 294 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL2 6 295 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL3 7 296 #define EFI_ARM_CONTEXT_TYPE_MISC 8 297 298 typedef struct { 299 UINT32 R0; 300 UINT32 R1; 301 UINT32 R2; 302 UINT32 R3; 303 UINT32 R4; 304 UINT32 R5; 305 UINT32 R6; 306 UINT32 R7; 307 UINT32 R8; 308 UINT32 R9; 309 UINT32 R10; 310 UINT32 R11; 311 UINT32 R12; 312 UINT32 R13_sp; 313 UINT32 R14_lr; 314 UINT32 R15_pc; 315 } EFI_ARM_V8_AARCH32_GPR; 316 317 typedef struct { 318 UINT32 Dfar; 319 UINT32 Dfsr; 320 UINT32 Ifar; 321 UINT32 Isr; 322 UINT32 Mair0; 323 UINT32 Mair1; 324 UINT32 Midr; 325 UINT32 Mpidr; 326 UINT32 Nmrr; 327 UINT32 Prrr; 328 UINT32 Sctlr_Ns; 329 UINT32 Spsr; 330 UINT32 Spsr_Abt; 331 UINT32 Spsr_Fiq; 332 UINT32 Spsr_Irq; 333 UINT32 Spsr_Svc; 334 UINT32 Spsr_Und; 335 UINT32 Tpidrprw; 336 UINT32 Tpidruro; 337 UINT32 Tpidrurw; 338 UINT32 Ttbcr; 339 UINT32 Ttbr0; 340 UINT32 Ttbr1; 341 UINT32 Dacr; 342 } EFI_ARM_AARCH32_EL1_CONTEXT_REGISTERS; 343 344 typedef struct { 345 UINT32 Elr_Hyp; 346 UINT32 Hamair0; 347 UINT32 Hamair1; 348 UINT32 Hcr; 349 UINT32 Hcr2; 350 UINT32 Hdfar; 351 UINT32 Hifar; 352 UINT32 Hpfar; 353 UINT32 Hsr; 354 UINT32 Htcr; 355 UINT32 Htpidr; 356 UINT32 Httbr; 357 UINT32 Spsr_Hyp; 358 UINT32 Vtcr; 359 UINT32 Vttbr; 360 UINT32 Dacr32_El2; 361 } EFI_ARM_AARCH32_EL2_CONTEXT_REGISTERS; 362 363 typedef struct { 364 UINT32 Sctlr_S; 365 UINT32 Spsr_Mon; 366 } EFI_ARM_AARCH32_SECURE_CONTEXT_REGISTERS; 367 368 typedef struct { 369 UINT64 X0; 370 UINT64 X1; 371 UINT64 X2; 372 UINT64 X3; 373 UINT64 X4; 374 UINT64 X5; 375 UINT64 X6; 376 UINT64 X7; 377 UINT64 X8; 378 UINT64 X9; 379 UINT64 X10; 380 UINT64 X11; 381 UINT64 X12; 382 UINT64 X13; 383 UINT64 X14; 384 UINT64 X15; 385 UINT64 X16; 386 UINT64 X17; 387 UINT64 X18; 388 UINT64 X19; 389 UINT64 X20; 390 UINT64 X21; 391 UINT64 X22; 392 UINT64 X23; 393 UINT64 X24; 394 UINT64 X25; 395 UINT64 X26; 396 UINT64 X27; 397 UINT64 X28; 398 UINT64 X29; 399 UINT64 X30; 400 UINT64 Sp; 401 } EFI_ARM_V8_AARCH64_GPR; 402 403 typedef struct { 404 UINT64 Elr_El1; 405 UINT64 Esr_El1; 406 UINT64 Far_El1; 407 UINT64 Isr_El1; 408 UINT64 Mair_El1; 409 UINT64 Midr_El1; 410 UINT64 Mpidr_El1; 411 UINT64 Sctlr_El1; 412 UINT64 Sp_El0; 413 UINT64 Sp_El1; 414 UINT64 Spsr_El1; 415 UINT64 Tcr_El1; 416 UINT64 Tpidr_El0; 417 UINT64 Tpidr_El1; 418 UINT64 Tpidrro_El0; 419 UINT64 Ttbr0_El1; 420 UINT64 Ttbr1_El1; 421 } EFI_ARM_AARCH64_EL1_CONTEXT_REGISTERS; 422 423 typedef struct { 424 UINT64 Elr_El2; 425 UINT64 Esr_El2; 426 UINT64 Far_El2; 427 UINT64 Hacr_El2; 428 UINT64 Hcr_El2; 429 UINT64 Hpfar_El2; 430 UINT64 Mair_El2; 431 UINT64 Sctlr_El2; 432 UINT64 Sp_El2; 433 UINT64 Spsr_El2; 434 UINT64 Tcr_El2; 435 UINT64 Tpidr_El2; 436 UINT64 Ttbr0_El2; 437 UINT64 Vtcr_El2; 438 UINT64 Vttbr_El2; 439 } EFI_ARM_AARCH64_EL2_CONTEXT_REGISTERS; 440 441 typedef struct { 442 UINT64 Elr_El3; 443 UINT64 Esr_El3; 444 UINT64 Far_El3; 445 UINT64 Mair_El3; 446 UINT64 Sctlr_El3; 447 UINT64 Sp_El3; 448 UINT64 Spsr_El3; 449 UINT64 Tcr_El3; 450 UINT64 Tpidr_El3; 451 UINT64 Ttbr0_El3; 452 } EFI_ARM_AARCH64_EL3_CONTEXT_REGISTERS; 453 454 typedef struct { 455 UINT64 MrsOp2 : 3; 456 UINT64 MrsCrm : 4; 457 UINT64 MrsCrn : 4; 458 UINT64 MrsOp1 : 3; 459 UINT64 MrsO0 : 1; 460 UINT64 Value : 64; 461 } EFI_ARM_MISC_CONTEXT_REGISTER; 462 463 json_object *cper_section_arm_to_ir(void *section); 464 void ir_section_arm_to_cper(json_object *section, FILE *out); 465 466 #ifdef __cplusplus 467 } 468 #endif 469 470 #endif 471