1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/msi.h>
9 #include <linux/pci.h>
10
11 #include "pci.h"
12 #include "core.h"
13 #include "hif.h"
14 #include "mhi.h"
15 #include "debug.h"
16
17 #define ATH12K_PCI_BAR_NUM 0
18 #define ATH12K_PCI_DMA_MASK 32
19
20 #define ATH12K_PCI_IRQ_CE0_OFFSET 3
21
22 #define WINDOW_ENABLE_BIT 0x40000000
23 #define WINDOW_REG_ADDRESS 0x310c
24 #define WINDOW_VALUE_MASK GENMASK(24, 19)
25 #define WINDOW_START 0x80000
26 #define WINDOW_RANGE_MASK GENMASK(18, 0)
27 #define WINDOW_STATIC_MASK GENMASK(31, 6)
28
29 #define TCSR_SOC_HW_VERSION 0x1B00000
30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4)
32
33 /* BAR0 + 4k is always accessible, and no
34 * need to force wakeup.
35 * 4K - 32 = 0xFE0
36 */
37 #define ACCESS_ALWAYS_OFF 0xFE0
38
39 #define QCN9274_DEVICE_ID 0x1109
40 #define WCN7850_DEVICE_ID 0x1107
41
42 static const struct pci_device_id ath12k_pci_id_table[] = {
43 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
44 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
45 {0}
46 };
47
48 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
49
50 /* TODO: revisit IRQ mapping for new SRNG's */
51 static const struct ath12k_msi_config ath12k_msi_config[] = {
52 {
53 .total_vectors = 16,
54 .total_users = 3,
55 .users = (struct ath12k_msi_user[]) {
56 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
57 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
58 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
59 },
60 },
61 };
62
63 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {
64 "bhi",
65 "mhi-er0",
66 "mhi-er1",
67 "ce0",
68 "ce1",
69 "ce2",
70 "ce3",
71 "ce4",
72 "ce5",
73 "ce6",
74 "ce7",
75 "ce8",
76 "ce9",
77 "ce10",
78 "ce11",
79 "ce12",
80 "ce13",
81 "ce14",
82 "ce15",
83 "host2wbm-desc-feed",
84 "host2reo-re-injection",
85 "host2reo-command",
86 "host2rxdma-monitor-ring3",
87 "host2rxdma-monitor-ring2",
88 "host2rxdma-monitor-ring1",
89 "reo2ost-exception",
90 "wbm2host-rx-release",
91 "reo2host-status",
92 "reo2host-destination-ring4",
93 "reo2host-destination-ring3",
94 "reo2host-destination-ring2",
95 "reo2host-destination-ring1",
96 "rxdma2host-monitor-destination-mac3",
97 "rxdma2host-monitor-destination-mac2",
98 "rxdma2host-monitor-destination-mac1",
99 "ppdu-end-interrupts-mac3",
100 "ppdu-end-interrupts-mac2",
101 "ppdu-end-interrupts-mac1",
102 "rxdma2host-monitor-status-ring-mac3",
103 "rxdma2host-monitor-status-ring-mac2",
104 "rxdma2host-monitor-status-ring-mac1",
105 "host2rxdma-host-buf-ring-mac3",
106 "host2rxdma-host-buf-ring-mac2",
107 "host2rxdma-host-buf-ring-mac1",
108 "rxdma2host-destination-ring-mac3",
109 "rxdma2host-destination-ring-mac2",
110 "rxdma2host-destination-ring-mac1",
111 "host2tcl-input-ring4",
112 "host2tcl-input-ring3",
113 "host2tcl-input-ring2",
114 "host2tcl-input-ring1",
115 "wbm2host-tx-completions-ring4",
116 "wbm2host-tx-completions-ring3",
117 "wbm2host-tx-completions-ring2",
118 "wbm2host-tx-completions-ring1",
119 "tcl2host-status-ring",
120 };
121
ath12k_pci_bus_wake_up(struct ath12k_base * ab)122 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab)
123 {
124 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
125
126 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
127 }
128
ath12k_pci_bus_release(struct ath12k_base * ab)129 static void ath12k_pci_bus_release(struct ath12k_base *ab)
130 {
131 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
132
133 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
134 }
135
136 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = {
137 .wakeup = NULL,
138 .release = NULL,
139 };
140
141 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = {
142 .wakeup = ath12k_pci_bus_wake_up,
143 .release = ath12k_pci_bus_release,
144 };
145
ath12k_pci_select_window(struct ath12k_pci * ab_pci,u32 offset)146 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset)
147 {
148 struct ath12k_base *ab = ab_pci->ab;
149
150 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK);
151 u32 static_window;
152
153 lockdep_assert_held(&ab_pci->window_lock);
154
155 /* Preserve the static window configuration and reset only dynamic window */
156 static_window = ab_pci->register_window & WINDOW_STATIC_MASK;
157 window |= static_window;
158
159 if (window != ab_pci->register_window) {
160 iowrite32(WINDOW_ENABLE_BIT | window,
161 ab->mem + WINDOW_REG_ADDRESS);
162 ioread32(ab->mem + WINDOW_REG_ADDRESS);
163 ab_pci->register_window = window;
164 }
165 }
166
ath12k_pci_select_static_window(struct ath12k_pci * ab_pci)167 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci)
168 {
169 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK);
170 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK);
171 u32 window;
172
173 window = (umac_window << 12) | (ce_window << 6);
174
175 spin_lock_bh(&ab_pci->window_lock);
176 ab_pci->register_window = window;
177 spin_unlock_bh(&ab_pci->window_lock);
178
179 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
180 }
181
ath12k_pci_get_window_start(struct ath12k_base * ab,u32 offset)182 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab,
183 u32 offset)
184 {
185 u32 window_start;
186
187 /* If offset lies within DP register range, use 3rd window */
188 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
189 window_start = 3 * WINDOW_START;
190 /* If offset lies within CE register range, use 2nd window */
191 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
192 window_start = 2 * WINDOW_START;
193 /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE
194 * use 0th window
195 */
196 else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) &&
197 !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK))
198 window_start = 0;
199 else
200 window_start = WINDOW_START;
201
202 return window_start;
203 }
204
ath12k_pci_soc_global_reset(struct ath12k_base * ab)205 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
206 {
207 u32 val, delay;
208
209 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
210
211 val |= PCIE_SOC_GLOBAL_RESET_V;
212
213 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
214
215 /* TODO: exact time to sleep is uncertain */
216 delay = 10;
217 mdelay(delay);
218
219 /* Need to toggle V bit back otherwise stuck in reset status */
220 val &= ~PCIE_SOC_GLOBAL_RESET_V;
221
222 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
223
224 mdelay(delay);
225
226 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
227 if (val == 0xffffffff)
228 ath12k_warn(ab, "link down error during global reset\n");
229 }
230
ath12k_pci_clear_dbg_registers(struct ath12k_base * ab)231 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab)
232 {
233 u32 val;
234
235 /* read cookie */
236 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
237 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val);
238
239 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
240 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
241
242 /* TODO: exact time to sleep is uncertain */
243 mdelay(10);
244
245 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
246 * continuing warm path and entering dead loop.
247 */
248 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0);
249 mdelay(10);
250
251 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
252 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
253
254 /* A read clear register. clear the register to prevent
255 * Q6 from entering wrong code path.
256 */
257 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
258 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val);
259 }
260
ath12k_pci_enable_ltssm(struct ath12k_base * ab)261 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab)
262 {
263 u32 val;
264 int i;
265
266 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
267
268 /* PCIE link seems very unstable after the Hot Reset*/
269 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
270 if (val == 0xffffffff)
271 mdelay(5);
272
273 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
274 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
275 }
276
277 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);
278
279 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
280 val |= GCC_GCC_PCIE_HOT_RST_VAL;
281 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
282 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
283
284 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
285
286 mdelay(5);
287 }
288
ath12k_pci_clear_all_intrs(struct ath12k_base * ab)289 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab)
290 {
291 /* This is a WAR for PCIE Hotreset.
292 * When target receive Hotreset, but will set the interrupt.
293 * So when download SBL again, SBL will open Interrupt and
294 * receive it, and crash immediately.
295 */
296 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
297 }
298
ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base * ab)299 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab)
300 {
301 u32 val;
302
303 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
304 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
305 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
306 }
307
ath12k_pci_force_wake(struct ath12k_base * ab)308 static void ath12k_pci_force_wake(struct ath12k_base *ab)
309 {
310 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
311 mdelay(5);
312 }
313
ath12k_pci_sw_reset(struct ath12k_base * ab,bool power_on)314 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on)
315 {
316 if (power_on) {
317 ath12k_pci_enable_ltssm(ab);
318 ath12k_pci_clear_all_intrs(ab);
319 ath12k_pci_set_wlaon_pwr_ctrl(ab);
320 }
321
322 ath12k_mhi_clear_vector(ab);
323 ath12k_pci_clear_dbg_registers(ab);
324 ath12k_pci_soc_global_reset(ab);
325 ath12k_mhi_set_mhictrl_reset(ab);
326 }
327
ath12k_pci_free_ext_irq(struct ath12k_base * ab)328 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab)
329 {
330 int i, j;
331
332 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
333 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
334
335 for (j = 0; j < irq_grp->num_irq; j++)
336 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
337
338 netif_napi_del(&irq_grp->napi);
339 }
340 }
341
ath12k_pci_free_irq(struct ath12k_base * ab)342 static void ath12k_pci_free_irq(struct ath12k_base *ab)
343 {
344 int i, irq_idx;
345
346 for (i = 0; i < ab->hw_params->ce_count; i++) {
347 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
348 continue;
349 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
350 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
351 }
352
353 ath12k_pci_free_ext_irq(ab);
354 }
355
ath12k_pci_ce_irq_enable(struct ath12k_base * ab,u16 ce_id)356 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)
357 {
358 u32 irq_idx;
359
360 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
361 enable_irq(ab->irq_num[irq_idx]);
362 }
363
ath12k_pci_ce_irq_disable(struct ath12k_base * ab,u16 ce_id)364 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)
365 {
366 u32 irq_idx;
367
368 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
369 disable_irq_nosync(ab->irq_num[irq_idx]);
370 }
371
ath12k_pci_ce_irqs_disable(struct ath12k_base * ab)372 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)
373 {
374 int i;
375
376 for (i = 0; i < ab->hw_params->ce_count; i++) {
377 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
378 continue;
379 ath12k_pci_ce_irq_disable(ab, i);
380 }
381 }
382
ath12k_pci_sync_ce_irqs(struct ath12k_base * ab)383 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab)
384 {
385 int i;
386 int irq_idx;
387
388 for (i = 0; i < ab->hw_params->ce_count; i++) {
389 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
390 continue;
391
392 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
393 synchronize_irq(ab->irq_num[irq_idx]);
394 }
395 }
396
ath12k_pci_ce_tasklet(struct tasklet_struct * t)397 static void ath12k_pci_ce_tasklet(struct tasklet_struct *t)
398 {
399 struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
400
401 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
402
403 ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
404 }
405
ath12k_pci_ce_interrupt_handler(int irq,void * arg)406 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)
407 {
408 struct ath12k_ce_pipe *ce_pipe = arg;
409
410 /* last interrupt received for this CE */
411 ce_pipe->timestamp = jiffies;
412
413 ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
414 tasklet_schedule(&ce_pipe->intr_tq);
415
416 return IRQ_HANDLED;
417 }
418
ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp * irq_grp)419 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
420 {
421 int i;
422
423 for (i = 0; i < irq_grp->num_irq; i++)
424 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
425 }
426
__ath12k_pci_ext_irq_disable(struct ath12k_base * sc)427 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *sc)
428 {
429 int i;
430
431 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
432 struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
433
434 ath12k_pci_ext_grp_disable(irq_grp);
435
436 napi_synchronize(&irq_grp->napi);
437 napi_disable(&irq_grp->napi);
438 }
439 }
440
ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp * irq_grp)441 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)
442 {
443 int i;
444
445 for (i = 0; i < irq_grp->num_irq; i++)
446 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
447 }
448
ath12k_pci_sync_ext_irqs(struct ath12k_base * ab)449 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab)
450 {
451 int i, j, irq_idx;
452
453 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
454 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
455
456 for (j = 0; j < irq_grp->num_irq; j++) {
457 irq_idx = irq_grp->irqs[j];
458 synchronize_irq(ab->irq_num[irq_idx]);
459 }
460 }
461 }
462
ath12k_pci_ext_grp_napi_poll(struct napi_struct * napi,int budget)463 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
464 {
465 struct ath12k_ext_irq_grp *irq_grp = container_of(napi,
466 struct ath12k_ext_irq_grp,
467 napi);
468 struct ath12k_base *ab = irq_grp->ab;
469 int work_done;
470
471 work_done = ath12k_dp_service_srng(ab, irq_grp, budget);
472 if (work_done < budget) {
473 napi_complete_done(napi, work_done);
474 ath12k_pci_ext_grp_enable(irq_grp);
475 }
476
477 if (work_done > budget)
478 work_done = budget;
479
480 return work_done;
481 }
482
ath12k_pci_ext_interrupt_handler(int irq,void * arg)483 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)
484 {
485 struct ath12k_ext_irq_grp *irq_grp = arg;
486
487 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);
488
489 /* last interrupt received for this group */
490 irq_grp->timestamp = jiffies;
491
492 ath12k_pci_ext_grp_disable(irq_grp);
493
494 napi_schedule(&irq_grp->napi);
495
496 return IRQ_HANDLED;
497 }
498
ath12k_pci_ext_irq_config(struct ath12k_base * ab)499 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)
500 {
501 int i, j, ret, num_vectors = 0;
502 u32 user_base_data = 0, base_vector = 0, base_idx;
503
504 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
505 ret = ath12k_pci_get_user_msi_assignment(ab, "DP",
506 &num_vectors,
507 &user_base_data,
508 &base_vector);
509 if (ret < 0)
510 return ret;
511
512 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
513 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
514 u32 num_irq = 0;
515
516 irq_grp->ab = ab;
517 irq_grp->grp_id = i;
518 init_dummy_netdev(&irq_grp->napi_ndev);
519 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
520 ath12k_pci_ext_grp_napi_poll);
521
522 if (ab->hw_params->ring_mask->tx[i] ||
523 ab->hw_params->ring_mask->rx[i] ||
524 ab->hw_params->ring_mask->rx_err[i] ||
525 ab->hw_params->ring_mask->rx_wbm_rel[i] ||
526 ab->hw_params->ring_mask->reo_status[i] ||
527 ab->hw_params->ring_mask->host2rxdma[i] ||
528 ab->hw_params->ring_mask->rx_mon_dest[i]) {
529 num_irq = 1;
530 }
531
532 irq_grp->num_irq = num_irq;
533 irq_grp->irqs[0] = base_idx + i;
534
535 for (j = 0; j < irq_grp->num_irq; j++) {
536 int irq_idx = irq_grp->irqs[j];
537 int vector = (i % num_vectors) + base_vector;
538 int irq = ath12k_pci_get_msi_irq(ab->dev, vector);
539
540 ab->irq_num[irq_idx] = irq;
541
542 ath12k_dbg(ab, ATH12K_DBG_PCI,
543 "irq:%d group:%d\n", irq, i);
544
545 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
546 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler,
547 IRQF_SHARED,
548 "DP_EXT_IRQ", irq_grp);
549 if (ret) {
550 ath12k_err(ab, "failed request irq %d: %d\n",
551 vector, ret);
552 return ret;
553 }
554
555 disable_irq_nosync(ab->irq_num[irq_idx]);
556 }
557 }
558
559 return 0;
560 }
561
ath12k_pci_config_irq(struct ath12k_base * ab)562 static int ath12k_pci_config_irq(struct ath12k_base *ab)
563 {
564 struct ath12k_ce_pipe *ce_pipe;
565 u32 msi_data_start;
566 u32 msi_data_count, msi_data_idx;
567 u32 msi_irq_start;
568 unsigned int msi_data;
569 int irq, i, ret, irq_idx;
570
571 ret = ath12k_pci_get_user_msi_assignment(ab,
572 "CE", &msi_data_count,
573 &msi_data_start, &msi_irq_start);
574 if (ret)
575 return ret;
576
577 /* Configure CE irqs */
578
579 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
580 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
581 continue;
582
583 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
584 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data);
585 ce_pipe = &ab->ce.ce_pipe[i];
586
587 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
588
589 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet);
590
591 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler,
592 IRQF_SHARED, irq_name[irq_idx],
593 ce_pipe);
594 if (ret) {
595 ath12k_err(ab, "failed to request irq %d: %d\n",
596 irq_idx, ret);
597 return ret;
598 }
599
600 ab->irq_num[irq_idx] = irq;
601 msi_data_idx++;
602
603 ath12k_pci_ce_irq_disable(ab, i);
604 }
605
606 ret = ath12k_pci_ext_irq_config(ab);
607 if (ret)
608 return ret;
609
610 return 0;
611 }
612
ath12k_pci_init_qmi_ce_config(struct ath12k_base * ab)613 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
614 {
615 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
616
617 cfg->tgt_ce = ab->hw_params->target_ce_config;
618 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
619
620 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
621 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
622 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
623 }
624
ath12k_pci_ce_irqs_enable(struct ath12k_base * ab)625 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
626 {
627 int i;
628
629 for (i = 0; i < ab->hw_params->ce_count; i++) {
630 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
631 continue;
632 ath12k_pci_ce_irq_enable(ab, i);
633 }
634 }
635
ath12k_pci_msi_config(struct ath12k_pci * ab_pci,bool enable)636 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable)
637 {
638 struct pci_dev *dev = ab_pci->pdev;
639 u16 control;
640
641 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
642
643 if (enable)
644 control |= PCI_MSI_FLAGS_ENABLE;
645 else
646 control &= ~PCI_MSI_FLAGS_ENABLE;
647
648 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
649 }
650
ath12k_pci_msi_enable(struct ath12k_pci * ab_pci)651 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci)
652 {
653 ath12k_pci_msi_config(ab_pci, true);
654 }
655
ath12k_pci_msi_disable(struct ath12k_pci * ab_pci)656 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci)
657 {
658 ath12k_pci_msi_config(ab_pci, false);
659 }
660
ath12k_pci_msi_alloc(struct ath12k_pci * ab_pci)661 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)
662 {
663 struct ath12k_base *ab = ab_pci->ab;
664 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
665 struct msi_desc *msi_desc;
666 int num_vectors;
667 int ret;
668
669 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
670 msi_config->total_vectors,
671 msi_config->total_vectors,
672 PCI_IRQ_MSI);
673 if (num_vectors != msi_config->total_vectors) {
674 ath12k_err(ab, "failed to get %d MSI vectors, only %d available",
675 msi_config->total_vectors, num_vectors);
676
677 if (num_vectors >= 0)
678 return -EINVAL;
679 else
680 return num_vectors;
681 }
682
683 ath12k_pci_msi_disable(ab_pci);
684
685 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
686 if (!msi_desc) {
687 ath12k_err(ab, "msi_desc is NULL!\n");
688 ret = -EINVAL;
689 goto free_msi_vector;
690 }
691
692 ab_pci->msi_ep_base_data = msi_desc->msg.data;
693 if (msi_desc->pci.msi_attrib.is_64)
694 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
695
696 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
697
698 return 0;
699
700 free_msi_vector:
701 pci_free_irq_vectors(ab_pci->pdev);
702
703 return ret;
704 }
705
ath12k_pci_msi_free(struct ath12k_pci * ab_pci)706 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci)
707 {
708 pci_free_irq_vectors(ab_pci->pdev);
709 }
710
ath12k_pci_claim(struct ath12k_pci * ab_pci,struct pci_dev * pdev)711 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev)
712 {
713 struct ath12k_base *ab = ab_pci->ab;
714 u16 device_id;
715 int ret = 0;
716
717 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
718 if (device_id != ab_pci->dev_id) {
719 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
720 device_id, ab_pci->dev_id);
721 ret = -EIO;
722 goto out;
723 }
724
725 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM);
726 if (ret) {
727 ath12k_err(ab, "failed to assign pci resource: %d\n", ret);
728 goto out;
729 }
730
731 ret = pci_enable_device(pdev);
732 if (ret) {
733 ath12k_err(ab, "failed to enable pci device: %d\n", ret);
734 goto out;
735 }
736
737 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci");
738 if (ret) {
739 ath12k_err(ab, "failed to request pci region: %d\n", ret);
740 goto disable_device;
741 }
742
743 ret = dma_set_mask_and_coherent(&pdev->dev,
744 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK));
745 if (ret) {
746 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n",
747 ATH12K_PCI_DMA_MASK, ret);
748 goto release_region;
749 }
750
751 pci_set_master(pdev);
752
753 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM);
754 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0);
755 if (!ab->mem) {
756 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM);
757 ret = -EIO;
758 goto release_region;
759 }
760
761 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
762 return 0;
763
764 release_region:
765 pci_release_region(pdev, ATH12K_PCI_BAR_NUM);
766 disable_device:
767 pci_disable_device(pdev);
768 out:
769 return ret;
770 }
771
ath12k_pci_free_region(struct ath12k_pci * ab_pci)772 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci)
773 {
774 struct ath12k_base *ab = ab_pci->ab;
775 struct pci_dev *pci_dev = ab_pci->pdev;
776
777 pci_iounmap(pci_dev, ab->mem);
778 ab->mem = NULL;
779 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM);
780 if (pci_is_enabled(pci_dev))
781 pci_disable_device(pci_dev);
782 }
783
ath12k_pci_aspm_disable(struct ath12k_pci * ab_pci)784 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci)
785 {
786 struct ath12k_base *ab = ab_pci->ab;
787
788 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
789 &ab_pci->link_ctl);
790
791 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
792 ab_pci->link_ctl,
793 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
794 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
795
796 /* disable L0s and L1 */
797 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
798 PCI_EXP_LNKCTL_ASPMC);
799
800 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
801 }
802
ath12k_pci_aspm_restore(struct ath12k_pci * ab_pci)803 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
804 {
805 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
806 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
807 PCI_EXP_LNKCTL_ASPMC,
808 ab_pci->link_ctl &
809 PCI_EXP_LNKCTL_ASPMC);
810 }
811
ath12k_pci_kill_tasklets(struct ath12k_base * ab)812 static void ath12k_pci_kill_tasklets(struct ath12k_base *ab)
813 {
814 int i;
815
816 for (i = 0; i < ab->hw_params->ce_count; i++) {
817 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
818
819 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
820 continue;
821
822 tasklet_kill(&ce_pipe->intr_tq);
823 }
824 }
825
ath12k_pci_ce_irq_disable_sync(struct ath12k_base * ab)826 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab)
827 {
828 ath12k_pci_ce_irqs_disable(ab);
829 ath12k_pci_sync_ce_irqs(ab);
830 ath12k_pci_kill_tasklets(ab);
831 }
832
ath12k_pci_map_service_to_pipe(struct ath12k_base * ab,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)833 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
834 u8 *ul_pipe, u8 *dl_pipe)
835 {
836 const struct service_to_pipe *entry;
837 bool ul_set = false, dl_set = false;
838 int i;
839
840 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) {
841 entry = &ab->hw_params->svc_to_ce_map[i];
842
843 if (__le32_to_cpu(entry->service_id) != service_id)
844 continue;
845
846 switch (__le32_to_cpu(entry->pipedir)) {
847 case PIPEDIR_NONE:
848 break;
849 case PIPEDIR_IN:
850 WARN_ON(dl_set);
851 *dl_pipe = __le32_to_cpu(entry->pipenum);
852 dl_set = true;
853 break;
854 case PIPEDIR_OUT:
855 WARN_ON(ul_set);
856 *ul_pipe = __le32_to_cpu(entry->pipenum);
857 ul_set = true;
858 break;
859 case PIPEDIR_INOUT:
860 WARN_ON(dl_set);
861 WARN_ON(ul_set);
862 *dl_pipe = __le32_to_cpu(entry->pipenum);
863 *ul_pipe = __le32_to_cpu(entry->pipenum);
864 dl_set = true;
865 ul_set = true;
866 break;
867 }
868 }
869
870 if (WARN_ON(!ul_set || !dl_set))
871 return -ENOENT;
872
873 return 0;
874 }
875
ath12k_pci_get_msi_irq(struct device * dev,unsigned int vector)876 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector)
877 {
878 struct pci_dev *pci_dev = to_pci_dev(dev);
879
880 return pci_irq_vector(pci_dev, vector);
881 }
882
ath12k_pci_get_user_msi_assignment(struct ath12k_base * ab,char * user_name,int * num_vectors,u32 * user_base_data,u32 * base_vector)883 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
884 int *num_vectors, u32 *user_base_data,
885 u32 *base_vector)
886 {
887 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
888 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
889 int idx;
890
891 for (idx = 0; idx < msi_config->total_users; idx++) {
892 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
893 *num_vectors = msi_config->users[idx].num_vectors;
894 *user_base_data = msi_config->users[idx].base_vector
895 + ab_pci->msi_ep_base_data;
896 *base_vector = msi_config->users[idx].base_vector;
897
898 ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
899 user_name, *num_vectors, *user_base_data,
900 *base_vector);
901
902 return 0;
903 }
904 }
905
906 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
907
908 return -EINVAL;
909 }
910
ath12k_pci_get_msi_address(struct ath12k_base * ab,u32 * msi_addr_lo,u32 * msi_addr_hi)911 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
912 u32 *msi_addr_hi)
913 {
914 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
915 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
916
917 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
918 msi_addr_lo);
919
920 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
921 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
922 msi_addr_hi);
923 } else {
924 *msi_addr_hi = 0;
925 }
926 }
927
ath12k_pci_get_ce_msi_idx(struct ath12k_base * ab,u32 ce_id,u32 * msi_idx)928 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
929 u32 *msi_idx)
930 {
931 u32 i, msi_data_idx;
932
933 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
934 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
935 continue;
936
937 if (ce_id == i)
938 break;
939
940 msi_data_idx++;
941 }
942 *msi_idx = msi_data_idx;
943 }
944
ath12k_pci_hif_ce_irq_enable(struct ath12k_base * ab)945 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab)
946 {
947 ath12k_pci_ce_irqs_enable(ab);
948 }
949
ath12k_pci_hif_ce_irq_disable(struct ath12k_base * ab)950 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab)
951 {
952 ath12k_pci_ce_irq_disable_sync(ab);
953 }
954
ath12k_pci_ext_irq_enable(struct ath12k_base * ab)955 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)
956 {
957 int i;
958
959 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
960 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
961
962 napi_enable(&irq_grp->napi);
963 ath12k_pci_ext_grp_enable(irq_grp);
964 }
965 }
966
ath12k_pci_ext_irq_disable(struct ath12k_base * ab)967 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
968 {
969 __ath12k_pci_ext_irq_disable(ab);
970 ath12k_pci_sync_ext_irqs(ab);
971 }
972
ath12k_pci_hif_suspend(struct ath12k_base * ab)973 int ath12k_pci_hif_suspend(struct ath12k_base *ab)
974 {
975 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
976
977 ath12k_mhi_suspend(ar_pci);
978
979 return 0;
980 }
981
ath12k_pci_hif_resume(struct ath12k_base * ab)982 int ath12k_pci_hif_resume(struct ath12k_base *ab)
983 {
984 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
985
986 ath12k_mhi_resume(ar_pci);
987
988 return 0;
989 }
990
ath12k_pci_stop(struct ath12k_base * ab)991 void ath12k_pci_stop(struct ath12k_base *ab)
992 {
993 ath12k_pci_ce_irq_disable_sync(ab);
994 ath12k_ce_cleanup_pipes(ab);
995 }
996
ath12k_pci_start(struct ath12k_base * ab)997 int ath12k_pci_start(struct ath12k_base *ab)
998 {
999 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1000
1001 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1002
1003 ath12k_pci_aspm_restore(ab_pci);
1004
1005 ath12k_pci_ce_irqs_enable(ab);
1006 ath12k_ce_rx_post_buf(ab);
1007
1008 return 0;
1009 }
1010
ath12k_pci_read32(struct ath12k_base * ab,u32 offset)1011 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset)
1012 {
1013 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1014 u32 val, window_start;
1015 int ret = 0;
1016
1017 /* for offset beyond BAR + 4K - 32, may
1018 * need to wakeup MHI to access.
1019 */
1020 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1021 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1022 ret = ab_pci->pci_ops->wakeup(ab);
1023
1024 if (offset < WINDOW_START) {
1025 val = ioread32(ab->mem + offset);
1026 } else {
1027 if (ab->static_window_map)
1028 window_start = ath12k_pci_get_window_start(ab, offset);
1029 else
1030 window_start = WINDOW_START;
1031
1032 if (window_start == WINDOW_START) {
1033 spin_lock_bh(&ab_pci->window_lock);
1034 ath12k_pci_select_window(ab_pci, offset);
1035 val = ioread32(ab->mem + window_start +
1036 (offset & WINDOW_RANGE_MASK));
1037 spin_unlock_bh(&ab_pci->window_lock);
1038 } else {
1039 if ((!window_start) &&
1040 (offset >= PCI_MHIREGLEN_REG &&
1041 offset <= PCI_MHI_REGION_END))
1042 offset = offset - PCI_MHIREGLEN_REG;
1043
1044 val = ioread32(ab->mem + window_start +
1045 (offset & WINDOW_RANGE_MASK));
1046 }
1047 }
1048
1049 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1050 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1051 !ret)
1052 ab_pci->pci_ops->release(ab);
1053 return val;
1054 }
1055
ath12k_pci_write32(struct ath12k_base * ab,u32 offset,u32 value)1056 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value)
1057 {
1058 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1059 u32 window_start;
1060 int ret = 0;
1061
1062 /* for offset beyond BAR + 4K - 32, may
1063 * need to wakeup MHI to access.
1064 */
1065 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1066 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1067 ret = ab_pci->pci_ops->wakeup(ab);
1068
1069 if (offset < WINDOW_START) {
1070 iowrite32(value, ab->mem + offset);
1071 } else {
1072 if (ab->static_window_map)
1073 window_start = ath12k_pci_get_window_start(ab, offset);
1074 else
1075 window_start = WINDOW_START;
1076
1077 if (window_start == WINDOW_START) {
1078 spin_lock_bh(&ab_pci->window_lock);
1079 ath12k_pci_select_window(ab_pci, offset);
1080 iowrite32(value, ab->mem + window_start +
1081 (offset & WINDOW_RANGE_MASK));
1082 spin_unlock_bh(&ab_pci->window_lock);
1083 } else {
1084 if ((!window_start) &&
1085 (offset >= PCI_MHIREGLEN_REG &&
1086 offset <= PCI_MHI_REGION_END))
1087 offset = offset - PCI_MHIREGLEN_REG;
1088
1089 iowrite32(value, ab->mem + window_start +
1090 (offset & WINDOW_RANGE_MASK));
1091 }
1092 }
1093
1094 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1095 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1096 !ret)
1097 ab_pci->pci_ops->release(ab);
1098 }
1099
ath12k_pci_power_up(struct ath12k_base * ab)1100 int ath12k_pci_power_up(struct ath12k_base *ab)
1101 {
1102 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1103 int ret;
1104
1105 ab_pci->register_window = 0;
1106 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1107 ath12k_pci_sw_reset(ab_pci->ab, true);
1108
1109 /* Disable ASPM during firmware download due to problems switching
1110 * to AMSS state.
1111 */
1112 ath12k_pci_aspm_disable(ab_pci);
1113
1114 ath12k_pci_msi_enable(ab_pci);
1115
1116 ret = ath12k_mhi_start(ab_pci);
1117 if (ret) {
1118 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1119 return ret;
1120 }
1121
1122 if (ab->static_window_map)
1123 ath12k_pci_select_static_window(ab_pci);
1124
1125 return 0;
1126 }
1127
ath12k_pci_power_down(struct ath12k_base * ab)1128 void ath12k_pci_power_down(struct ath12k_base *ab)
1129 {
1130 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1131
1132 /* restore aspm in case firmware bootup fails */
1133 ath12k_pci_aspm_restore(ab_pci);
1134
1135 ath12k_pci_force_wake(ab_pci->ab);
1136 ath12k_pci_msi_disable(ab_pci);
1137 ath12k_mhi_stop(ab_pci);
1138 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1139 ath12k_pci_sw_reset(ab_pci->ab, false);
1140 }
1141
1142 static const struct ath12k_hif_ops ath12k_pci_hif_ops = {
1143 .start = ath12k_pci_start,
1144 .stop = ath12k_pci_stop,
1145 .read32 = ath12k_pci_read32,
1146 .write32 = ath12k_pci_write32,
1147 .power_down = ath12k_pci_power_down,
1148 .power_up = ath12k_pci_power_up,
1149 .suspend = ath12k_pci_hif_suspend,
1150 .resume = ath12k_pci_hif_resume,
1151 .irq_enable = ath12k_pci_ext_irq_enable,
1152 .irq_disable = ath12k_pci_ext_irq_disable,
1153 .get_msi_address = ath12k_pci_get_msi_address,
1154 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment,
1155 .map_service_to_pipe = ath12k_pci_map_service_to_pipe,
1156 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable,
1157 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable,
1158 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx,
1159 };
1160
1161 static
ath12k_pci_read_hw_version(struct ath12k_base * ab,u32 * major,u32 * minor)1162 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor)
1163 {
1164 u32 soc_hw_version;
1165
1166 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION);
1167 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
1168 soc_hw_version);
1169 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
1170 soc_hw_version);
1171
1172 ath12k_dbg(ab, ATH12K_DBG_PCI,
1173 "pci tcsr_soc_hw_version major %d minor %d\n",
1174 *major, *minor);
1175 }
1176
ath12k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)1177 static int ath12k_pci_probe(struct pci_dev *pdev,
1178 const struct pci_device_id *pci_dev)
1179 {
1180 struct ath12k_base *ab;
1181 struct ath12k_pci *ab_pci;
1182 u32 soc_hw_version_major, soc_hw_version_minor;
1183 int ret;
1184
1185 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI);
1186 if (!ab) {
1187 dev_err(&pdev->dev, "failed to allocate ath12k base\n");
1188 return -ENOMEM;
1189 }
1190
1191 ab->dev = &pdev->dev;
1192 pci_set_drvdata(pdev, ab);
1193 ab_pci = ath12k_pci_priv(ab);
1194 ab_pci->dev_id = pci_dev->device;
1195 ab_pci->ab = ab;
1196 ab_pci->pdev = pdev;
1197 ab->hif.ops = &ath12k_pci_hif_ops;
1198 pci_set_drvdata(pdev, ab);
1199 spin_lock_init(&ab_pci->window_lock);
1200
1201 ret = ath12k_pci_claim(ab_pci, pdev);
1202 if (ret) {
1203 ath12k_err(ab, "failed to claim device: %d\n", ret);
1204 goto err_free_core;
1205 }
1206
1207 switch (pci_dev->device) {
1208 case QCN9274_DEVICE_ID:
1209 ab_pci->msi_config = &ath12k_msi_config[0];
1210 ab->static_window_map = true;
1211 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274;
1212 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1213 &soc_hw_version_minor);
1214 switch (soc_hw_version_major) {
1215 case ATH12K_PCI_SOC_HW_VERSION_2:
1216 ab->hw_rev = ATH12K_HW_QCN9274_HW20;
1217 break;
1218 case ATH12K_PCI_SOC_HW_VERSION_1:
1219 ab->hw_rev = ATH12K_HW_QCN9274_HW10;
1220 break;
1221 default:
1222 dev_err(&pdev->dev,
1223 "Unknown hardware version found for QCN9274: 0x%x\n",
1224 soc_hw_version_major);
1225 ret = -EOPNOTSUPP;
1226 goto err_pci_free_region;
1227 }
1228 break;
1229 case WCN7850_DEVICE_ID:
1230 ab_pci->msi_config = &ath12k_msi_config[0];
1231 ab->static_window_map = false;
1232 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850;
1233 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1234 &soc_hw_version_minor);
1235 switch (soc_hw_version_major) {
1236 case ATH12K_PCI_SOC_HW_VERSION_2:
1237 ab->hw_rev = ATH12K_HW_WCN7850_HW20;
1238 break;
1239 default:
1240 dev_err(&pdev->dev,
1241 "Unknown hardware version found for WCN7850: 0x%x\n",
1242 soc_hw_version_major);
1243 ret = -EOPNOTSUPP;
1244 goto err_pci_free_region;
1245 }
1246 break;
1247
1248 default:
1249 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1250 pci_dev->device);
1251 ret = -EOPNOTSUPP;
1252 goto err_pci_free_region;
1253 }
1254
1255 ret = ath12k_pci_msi_alloc(ab_pci);
1256 if (ret) {
1257 ath12k_err(ab, "failed to alloc msi: %d\n", ret);
1258 goto err_pci_free_region;
1259 }
1260
1261 ret = ath12k_core_pre_init(ab);
1262 if (ret)
1263 goto err_pci_msi_free;
1264
1265 ret = ath12k_mhi_register(ab_pci);
1266 if (ret) {
1267 ath12k_err(ab, "failed to register mhi: %d\n", ret);
1268 goto err_pci_msi_free;
1269 }
1270
1271 ret = ath12k_hal_srng_init(ab);
1272 if (ret)
1273 goto err_mhi_unregister;
1274
1275 ret = ath12k_ce_alloc_pipes(ab);
1276 if (ret) {
1277 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1278 goto err_hal_srng_deinit;
1279 }
1280
1281 ath12k_pci_init_qmi_ce_config(ab);
1282
1283 ret = ath12k_pci_config_irq(ab);
1284 if (ret) {
1285 ath12k_err(ab, "failed to config irq: %d\n", ret);
1286 goto err_ce_free;
1287 }
1288
1289 ret = ath12k_core_init(ab);
1290 if (ret) {
1291 ath12k_err(ab, "failed to init core: %d\n", ret);
1292 goto err_free_irq;
1293 }
1294 return 0;
1295
1296 err_free_irq:
1297 ath12k_pci_free_irq(ab);
1298
1299 err_ce_free:
1300 ath12k_ce_free_pipes(ab);
1301
1302 err_hal_srng_deinit:
1303 ath12k_hal_srng_deinit(ab);
1304
1305 err_mhi_unregister:
1306 ath12k_mhi_unregister(ab_pci);
1307
1308 err_pci_msi_free:
1309 ath12k_pci_msi_free(ab_pci);
1310
1311 err_pci_free_region:
1312 ath12k_pci_free_region(ab_pci);
1313
1314 err_free_core:
1315 ath12k_core_free(ab);
1316
1317 return ret;
1318 }
1319
ath12k_pci_remove(struct pci_dev * pdev)1320 static void ath12k_pci_remove(struct pci_dev *pdev)
1321 {
1322 struct ath12k_base *ab = pci_get_drvdata(pdev);
1323 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1324
1325 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1326 ath12k_pci_power_down(ab);
1327 ath12k_qmi_deinit_service(ab);
1328 goto qmi_fail;
1329 }
1330
1331 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags);
1332
1333 cancel_work_sync(&ab->reset_work);
1334 ath12k_core_deinit(ab);
1335
1336 qmi_fail:
1337 ath12k_mhi_unregister(ab_pci);
1338
1339 ath12k_pci_free_irq(ab);
1340 ath12k_pci_msi_free(ab_pci);
1341 ath12k_pci_free_region(ab_pci);
1342
1343 ath12k_hal_srng_deinit(ab);
1344 ath12k_ce_free_pipes(ab);
1345 ath12k_core_free(ab);
1346 }
1347
ath12k_pci_shutdown(struct pci_dev * pdev)1348 static void ath12k_pci_shutdown(struct pci_dev *pdev)
1349 {
1350 struct ath12k_base *ab = pci_get_drvdata(pdev);
1351
1352 ath12k_pci_power_down(ab);
1353 }
1354
ath12k_pci_pm_suspend(struct device * dev)1355 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev)
1356 {
1357 struct ath12k_base *ab = dev_get_drvdata(dev);
1358 int ret;
1359
1360 ret = ath12k_core_suspend(ab);
1361 if (ret)
1362 ath12k_warn(ab, "failed to suspend core: %d\n", ret);
1363
1364 return ret;
1365 }
1366
ath12k_pci_pm_resume(struct device * dev)1367 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev)
1368 {
1369 struct ath12k_base *ab = dev_get_drvdata(dev);
1370 int ret;
1371
1372 ret = ath12k_core_resume(ab);
1373 if (ret)
1374 ath12k_warn(ab, "failed to resume core: %d\n", ret);
1375
1376 return ret;
1377 }
1378
1379 static SIMPLE_DEV_PM_OPS(ath12k_pci_pm_ops,
1380 ath12k_pci_pm_suspend,
1381 ath12k_pci_pm_resume);
1382
1383 static struct pci_driver ath12k_pci_driver = {
1384 .name = "ath12k_pci",
1385 .id_table = ath12k_pci_id_table,
1386 .probe = ath12k_pci_probe,
1387 .remove = ath12k_pci_remove,
1388 .shutdown = ath12k_pci_shutdown,
1389 .driver.pm = &ath12k_pci_pm_ops,
1390 };
1391
ath12k_pci_init(void)1392 static int ath12k_pci_init(void)
1393 {
1394 int ret;
1395
1396 ret = pci_register_driver(&ath12k_pci_driver);
1397 if (ret) {
1398 pr_err("failed to register ath12k pci driver: %d\n",
1399 ret);
1400 return ret;
1401 }
1402
1403 return 0;
1404 }
1405 module_init(ath12k_pci_init);
1406
ath12k_pci_exit(void)1407 static void ath12k_pci_exit(void)
1408 {
1409 pci_unregister_driver(&ath12k_pci_driver);
1410 }
1411
1412 module_exit(ath12k_pci_exit);
1413
1414 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11be WLAN devices");
1415 MODULE_LICENSE("Dual BSD/GPL");
1416