xref: /openbmc/u-boot/arch/sh/cpu/sh4/watchdog.c (revision e8f80a5a) 
1 // SPDX-License-Identifier: GPL-2.0+
2 
3 #include <common.h>
4 #include <asm/processor.h>
5 #include <asm/system.h>
6 #include <asm/io.h>
7 
8 #define WDT_BASE	WTCNT
9 
10 #define WDT_WD		(1 << 6)
11 #define WDT_RST_P	(0)
12 #define WDT_RST_M	(1 << 5)
13 #define WDT_ENABLE	(1 << 7)
14 
15 #if defined(CONFIG_WATCHDOG)
csr_read(void)16 static unsigned char csr_read(void)
17 {
18 	return inb(WDT_BASE + 0x04);
19 }
20 
cnt_write(unsigned char value)21 static void cnt_write(unsigned char value)
22 {
23 	outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
24 }
25 
csr_write(unsigned char value)26 static void csr_write(unsigned char value)
27 {
28 	outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
29 }
30 
watchdog_reset(void)31 void watchdog_reset(void)
32 {
33 	outl(0x55000000, WDT_BASE + 0x08);
34 }
35 
watchdog_init(void)36 int watchdog_init(void)
37 {
38 	/* Set overflow time*/
39 	cnt_write(0);
40 	/* Power on reset */
41 	csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
42 
43 	return 0;
44 }
45 
watchdog_disable(void)46 int watchdog_disable(void)
47 {
48 	csr_write(csr_read() & ~WDT_ENABLE);
49 	return 0;
50 }
51 #endif
52 
reset_cpu(unsigned long ignored)53 void reset_cpu(unsigned long ignored)
54 {
55 	/* Address error with SR.BL=1 first. */
56 	trigger_address_error();
57 
58 	while (1)
59 		;
60 }
61