1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 * 21 * Lots of defines copied from kernel/include/linux/intel-iommu.h: 22 * Copyright (C) 2006-2008 Intel Corporation 23 * Author: Ashok Raj <ashok.raj@intel.com> 24 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 25 * 26 */ 27 28 #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H 29 #define HW_I386_INTEL_IOMMU_INTERNAL_H 30 #include "hw/i386/intel_iommu.h" 31 32 /* 33 * Intel IOMMU register specification 34 */ 35 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ 36 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ 37 #define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */ 38 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ 39 #define DMAR_ECAP_REG_HI 0X14 40 #define DMAR_GCMD_REG 0x18 /* Global command */ 41 #define DMAR_GSTS_REG 0x1c /* Global status */ 42 #define DMAR_RTADDR_REG 0x20 /* Root entry table */ 43 #define DMAR_RTADDR_REG_HI 0X24 44 #define DMAR_CCMD_REG 0x28 /* Context command */ 45 #define DMAR_CCMD_REG_HI 0x2c 46 #define DMAR_FSTS_REG 0x34 /* Fault status */ 47 #define DMAR_FECTL_REG 0x38 /* Fault control */ 48 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data */ 49 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr */ 50 #define DMAR_FEUADDR_REG 0x44 /* Upper address */ 51 #define DMAR_AFLOG_REG 0x58 /* Advanced fault control */ 52 #define DMAR_AFLOG_REG_HI 0X5c 53 #define DMAR_PMEN_REG 0x64 /* Enable protected memory region */ 54 #define DMAR_PLMBASE_REG 0x68 /* PMRR low addr */ 55 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ 56 #define DMAR_PHMBASE_REG 0x70 /* PMRR high base addr */ 57 #define DMAR_PHMBASE_REG_HI 0X74 58 #define DMAR_PHMLIMIT_REG 0x78 /* PMRR high limit */ 59 #define DMAR_PHMLIMIT_REG_HI 0x7c 60 #define DMAR_IQH_REG 0x80 /* Invalidation queue head */ 61 #define DMAR_IQH_REG_HI 0X84 62 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail */ 63 #define DMAR_IQT_REG_HI 0X8c 64 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr */ 65 #define DMAR_IQA_REG_HI 0x94 66 #define DMAR_ICS_REG 0x9c /* Invalidation complete status */ 67 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */ 68 #define DMAR_IRTA_REG_HI 0xbc 69 #define DMAR_IECTL_REG 0xa0 /* Invalidation event control */ 70 #define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */ 71 #define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */ 72 #define DMAR_IEUADDR_REG 0xac /* Invalidation event address */ 73 #define DMAR_PQH_REG 0xc0 /* Page request queue head */ 74 #define DMAR_PQH_REG_HI 0xc4 75 #define DMAR_PQT_REG 0xc8 /* Page request queue tail*/ 76 #define DMAR_PQT_REG_HI 0xcc 77 #define DMAR_PQA_REG 0xd0 /* Page request queue address */ 78 #define DMAR_PQA_REG_HI 0xd4 79 #define DMAR_PRS_REG 0xdc /* Page request status */ 80 #define DMAR_PECTL_REG 0xe0 /* Page request event control */ 81 #define DMAR_PEDATA_REG 0xe4 /* Page request event data */ 82 #define DMAR_PEADDR_REG 0xe8 /* Page request event address */ 83 #define DMAR_PEUADDR_REG 0xec /* Page event upper address */ 84 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */ 85 #define DMAR_MTRRCAP_REG_HI 0x104 86 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */ 87 #define DMAR_MTRRDEF_REG_HI 0x10c 88 89 /* IOTLB registers */ 90 #define DMAR_IOTLB_REG_OFFSET 0xf0 /* Offset to the IOTLB registers */ 91 #define DMAR_IVA_REG DMAR_IOTLB_REG_OFFSET /* Invalidate address */ 92 #define DMAR_IVA_REG_HI (DMAR_IVA_REG + 4) 93 /* IOTLB invalidate register */ 94 #define DMAR_IOTLB_REG (DMAR_IOTLB_REG_OFFSET + 0x8) 95 #define DMAR_IOTLB_REG_HI (DMAR_IOTLB_REG + 4) 96 97 /* FRCD */ 98 #define DMAR_FRCD_REG_OFFSET 0x220 /* Offset to the fault recording regs */ 99 /* NOTICE: If you change the DMAR_FRCD_REG_NR, please remember to change the 100 * DMAR_REG_SIZE in include/hw/i386/intel_iommu.h. 101 * #define DMAR_REG_SIZE (DMAR_FRCD_REG_OFFSET + 16 * DMAR_FRCD_REG_NR) 102 */ 103 #define DMAR_FRCD_REG_NR 1ULL /* Num of fault recording regs */ 104 105 #define DMAR_FRCD_REG_0_0 0x220 /* The 0th fault recording regs */ 106 #define DMAR_FRCD_REG_0_1 0x224 107 #define DMAR_FRCD_REG_0_2 0x228 108 #define DMAR_FRCD_REG_0_3 0x22c 109 110 /* Interrupt Address Range */ 111 #define VTD_INTERRUPT_ADDR_FIRST 0xfee00000ULL 112 #define VTD_INTERRUPT_ADDR_LAST 0xfeefffffULL 113 #define VTD_INTERRUPT_ADDR_SIZE (VTD_INTERRUPT_ADDR_LAST - \ 114 VTD_INTERRUPT_ADDR_FIRST + 1) 115 116 /* The shift of source_id in the key of IOTLB hash table */ 117 #define VTD_IOTLB_SID_SHIFT 26 118 #define VTD_IOTLB_LVL_SHIFT 42 119 #define VTD_IOTLB_PASID_SHIFT 44 120 #define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table */ 121 122 /* IOTLB_REG */ 123 #define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */ 124 #define VTD_TLB_DSI_FLUSH (2ULL << 60) /* Domain-selective */ 125 #define VTD_TLB_PSI_FLUSH (3ULL << 60) /* Page-selective */ 126 #define VTD_TLB_FLUSH_GRANU_MASK (3ULL << 60) 127 #define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57) 128 #define VTD_TLB_DSI_FLUSH_A (2ULL << 57) 129 #define VTD_TLB_PSI_FLUSH_A (3ULL << 57) 130 #define VTD_TLB_FLUSH_GRANU_MASK_A (3ULL << 57) 131 #define VTD_TLB_IVT (1ULL << 63) 132 #define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK) 133 134 /* IVA_REG */ 135 #define VTD_IVA_ADDR(val) ((val) & ~0xfffULL) 136 #define VTD_IVA_AM(val) ((val) & 0x3fULL) 137 138 /* GCMD_REG */ 139 #define VTD_GCMD_TE (1UL << 31) 140 #define VTD_GCMD_SRTP (1UL << 30) 141 #define VTD_GCMD_SFL (1UL << 29) 142 #define VTD_GCMD_EAFL (1UL << 28) 143 #define VTD_GCMD_WBF (1UL << 27) 144 #define VTD_GCMD_QIE (1UL << 26) 145 #define VTD_GCMD_IRE (1UL << 25) 146 #define VTD_GCMD_SIRTP (1UL << 24) 147 #define VTD_GCMD_CFI (1UL << 23) 148 149 /* GSTS_REG */ 150 #define VTD_GSTS_TES (1UL << 31) 151 #define VTD_GSTS_RTPS (1UL << 30) 152 #define VTD_GSTS_FLS (1UL << 29) 153 #define VTD_GSTS_AFLS (1UL << 28) 154 #define VTD_GSTS_WBFS (1UL << 27) 155 #define VTD_GSTS_QIES (1UL << 26) 156 #define VTD_GSTS_IRES (1UL << 25) 157 #define VTD_GSTS_IRTPS (1UL << 24) 158 #define VTD_GSTS_CFIS (1UL << 23) 159 160 /* CCMD_REG */ 161 #define VTD_CCMD_ICC (1ULL << 63) 162 #define VTD_CCMD_GLOBAL_INVL (1ULL << 61) 163 #define VTD_CCMD_DOMAIN_INVL (2ULL << 61) 164 #define VTD_CCMD_DEVICE_INVL (3ULL << 61) 165 #define VTD_CCMD_CIRG_MASK (3ULL << 61) 166 #define VTD_CCMD_GLOBAL_INVL_A (1ULL << 59) 167 #define VTD_CCMD_DOMAIN_INVL_A (2ULL << 59) 168 #define VTD_CCMD_DEVICE_INVL_A (3ULL << 59) 169 #define VTD_CCMD_CAIG_MASK (3ULL << 59) 170 #define VTD_CCMD_DID(val) ((val) & VTD_DOMAIN_ID_MASK) 171 #define VTD_CCMD_SID(val) (((val) >> 16) & 0xffffULL) 172 #define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL) 173 174 /* RTADDR_REG */ 175 #define VTD_RTADDR_SMT (1ULL << 10) 176 #define VTD_RTADDR_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL) 177 178 /* IRTA_REG */ 179 #define VTD_IRTA_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL) 180 #define VTD_IRTA_EIME (1ULL << 11) 181 #define VTD_IRTA_SIZE_MASK (0xfULL) 182 183 /* ECAP_REG */ 184 /* (offset >> 4) << 8 */ 185 #define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4) 186 #define VTD_ECAP_QI (1ULL << 1) 187 #define VTD_ECAP_DT (1ULL << 2) 188 /* Interrupt Remapping support */ 189 #define VTD_ECAP_IR (1ULL << 3) 190 #define VTD_ECAP_EIM (1ULL << 4) 191 #define VTD_ECAP_PT (1ULL << 6) 192 #define VTD_ECAP_SC (1ULL << 7) 193 #define VTD_ECAP_PRS (1ULL << 29) 194 #define VTD_ECAP_MHMV (15ULL << 20) 195 #define VTD_ECAP_SRS (1ULL << 31) 196 #define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */ 197 #define VTD_ECAP_PASID (1ULL << 40) 198 #define VTD_ECAP_SMTS (1ULL << 43) 199 #define VTD_ECAP_SLTS (1ULL << 46) 200 #define VTD_ECAP_FLTS (1ULL << 47) 201 202 /* CAP_REG */ 203 /* (offset >> 4) << 24 */ 204 #define VTD_CAP_FRO (DMAR_FRCD_REG_OFFSET << 20) 205 #define VTD_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40) 206 #define VTD_DOMAIN_ID_SHIFT 16 /* 16-bit domain id for 64K domains */ 207 #define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1) 208 #define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL) 209 #define VTD_ADDRESS_SIZE(aw) (1ULL << (aw)) 210 #define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16) 211 #define VTD_MAMV 18ULL 212 #define VTD_CAP_MAMV (VTD_MAMV << 48) 213 #define VTD_CAP_PSI (1ULL << 39) 214 #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) 215 #define VTD_CAP_DRAIN_WRITE (1ULL << 54) 216 #define VTD_CAP_DRAIN_READ (1ULL << 55) 217 #define VTD_CAP_FS1GP (1ULL << 56) 218 #define VTD_CAP_ESRTPS (1ULL << 63) 219 #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE) 220 #define VTD_CAP_CM (1ULL << 7) 221 #define VTD_PASID_ID_SHIFT 20 222 #define VTD_PASID_ID_MASK ((1ULL << VTD_PASID_ID_SHIFT) - 1) 223 224 /* Supported Adjusted Guest Address Widths */ 225 #define VTD_CAP_SAGAW_SHIFT 8 226 #define VTD_CAP_SAGAW_MASK (0x1fULL << VTD_CAP_SAGAW_SHIFT) 227 /* 39-bit AGAW, 3-level page-table */ 228 #define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT) 229 /* 48-bit AGAW, 4-level page-table */ 230 #define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT) 231 232 /* IQT_REG */ 233 #define VTD_IQT_QT(dw_bit, val) (dw_bit ? (((val) >> 5) & 0x3fffULL) : \ 234 (((val) >> 4) & 0x7fffULL)) 235 #define VTD_IQT_QT_256_RSV_BIT 0x10 236 237 /* IQA_REG */ 238 #define VTD_IQA_IQA_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL) 239 #define VTD_IQA_QS 0x7ULL 240 #define VTD_IQA_DW_MASK 0x800 241 242 /* IQH_REG */ 243 #define VTD_IQH_QH_SHIFT_4 4 244 #define VTD_IQH_QH_SHIFT_5 5 245 #define VTD_IQH_QH_MASK 0x7fff0ULL 246 247 /* ICS_REG */ 248 #define VTD_ICS_IWC 1UL 249 250 /* IECTL_REG */ 251 #define VTD_IECTL_IM (1UL << 31) 252 #define VTD_IECTL_IP (1UL << 30) 253 254 /* FSTS_REG */ 255 #define VTD_FSTS_FRI_MASK 0xff00UL 256 #define VTD_FSTS_FRI(val) ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK) 257 #define VTD_FSTS_IQE (1UL << 4) 258 #define VTD_FSTS_PPF (1UL << 1) 259 #define VTD_FSTS_PFO 1UL 260 261 /* FECTL_REG */ 262 #define VTD_FECTL_IM (1UL << 31) 263 #define VTD_FECTL_IP (1UL << 30) 264 265 /* Fault Recording Register */ 266 /* For the high 64-bit of 128-bit */ 267 #define VTD_FRCD_F (1ULL << 63) 268 #define VTD_FRCD_T (1ULL << 62) 269 #define VTD_FRCD_FR(val) (((val) & 0xffULL) << 32) 270 #define VTD_FRCD_SID_MASK 0xffffULL 271 #define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK) 272 #define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40) 273 #define VTD_FRCD_PP(val) (((val) & 0x1ULL) << 31) 274 /* For the low 64-bit of 128-bit */ 275 #define VTD_FRCD_FI(val) ((val) & ~0xfffULL) 276 #define VTD_FRCD_IR_IDX(val) (((val) & 0xffffULL) << 48) 277 278 /* DMA Remapping Fault Conditions */ 279 typedef enum VTDFaultReason { 280 VTD_FR_RESERVED = 0, /* Reserved for Advanced Fault logging */ 281 VTD_FR_ROOT_ENTRY_P = 1, /* The Present(P) field of root-entry is 0 */ 282 VTD_FR_CONTEXT_ENTRY_P, /* The Present(P) field of context-entry is 0 */ 283 VTD_FR_CONTEXT_ENTRY_INV, /* Invalid programming of a context-entry */ 284 VTD_FR_ADDR_BEYOND_MGAW, /* Input-address above (2^x-1) */ 285 VTD_FR_WRITE, /* No write permission */ 286 VTD_FR_READ, /* No read permission */ 287 /* Fail to access a second-level paging entry (not SL_PML4E) */ 288 VTD_FR_PAGING_ENTRY_INV, 289 VTD_FR_ROOT_TABLE_INV, /* Fail to access a root-entry */ 290 VTD_FR_CONTEXT_TABLE_INV, /* Fail to access a context-entry */ 291 /* Non-zero reserved field in a present root-entry */ 292 VTD_FR_ROOT_ENTRY_RSVD, 293 /* Non-zero reserved field in a present context-entry */ 294 VTD_FR_CONTEXT_ENTRY_RSVD, 295 /* Non-zero reserved field in a second-level paging entry with at lease one 296 * Read(R) and Write(W) or Execute(E) field is Set. 297 */ 298 VTD_FR_PAGING_ENTRY_RSVD, 299 /* Translation request or translated request explicitly blocked dut to the 300 * programming of the Translation Type (T) field in the present 301 * context-entry. 302 */ 303 VTD_FR_CONTEXT_ENTRY_TT, 304 /* Output address in the interrupt address range */ 305 VTD_FR_INTERRUPT_ADDR = 0xE, 306 307 /* Interrupt remapping transition faults */ 308 VTD_FR_IR_REQ_RSVD = 0x20, /* One or more IR request reserved 309 * fields set */ 310 VTD_FR_IR_INDEX_OVER = 0x21, /* Index value greater than max */ 311 VTD_FR_IR_ENTRY_P = 0x22, /* Present (P) not set in IRTE */ 312 VTD_FR_IR_ROOT_INVAL = 0x23, /* IR Root table invalid */ 313 VTD_FR_IR_IRTE_RSVD = 0x24, /* IRTE Rsvd field non-zero with 314 * Present flag set */ 315 VTD_FR_IR_REQ_COMPAT = 0x25, /* Encountered compatible IR 316 * request while disabled */ 317 VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */ 318 319 VTD_FR_RTADDR_INV_TTM = 0x31, /* Invalid TTM in RTADDR */ 320 321 VTD_FR_SM_PRE_ABS = 0x47, /* SCT.8 : PRE bit in a present SM CE is 0 */ 322 323 /* PASID directory entry access failure */ 324 VTD_FR_PASID_DIR_ACCESS_ERR = 0x50, 325 /* The Present(P) field of pasid directory entry is 0 */ 326 VTD_FR_PASID_DIR_ENTRY_P = 0x51, 327 VTD_FR_PASID_TABLE_ACCESS_ERR = 0x58, /* PASID table entry access failure */ 328 /* The Present(P) field of pasid table entry is 0 */ 329 VTD_FR_PASID_ENTRY_P = 0x59, 330 VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */ 331 332 /* Fail to access a first-level paging entry (not FS_PML4E) */ 333 VTD_FR_FS_PAGING_ENTRY_INV = 0x70, 334 VTD_FR_FS_PAGING_ENTRY_P = 0x71, 335 /* Non-zero reserved field in present first-stage paging entry */ 336 VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72, 337 VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */ 338 VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/ 339 VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */ 340 VTD_FR_SM_WRITE = 0x85, /* No write permission */ 341 342 /* Output address in the interrupt address range for scalable mode */ 343 VTD_FR_SM_INTERRUPT_ADDR = 0x87, 344 VTD_FR_FS_BIT_UPDATE_FAILED = 0x91, /* SFS.10 */ 345 VTD_FR_MAX, /* Guard */ 346 } VTDFaultReason; 347 348 #define VTD_CONTEXT_CACHE_GEN_MAX 0xffffffffUL 349 350 /* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */ 351 struct VTDInvDescIEC { 352 #if HOST_BIG_ENDIAN 353 uint64_t reserved_2:16; 354 uint64_t index:16; /* Start index to invalidate */ 355 uint64_t index_mask:5; /* 2^N for continuous int invalidation */ 356 uint64_t resved_1:22; 357 uint64_t granularity:1; /* If set, it's global IR invalidation */ 358 uint64_t type:4; /* Should always be 0x4 */ 359 #else 360 uint32_t type:4; /* Should always be 0x4 */ 361 uint32_t granularity:1; /* If set, it's global IR invalidation */ 362 uint32_t resved_1:22; 363 uint32_t index_mask:5; /* 2^N for continuous int invalidation */ 364 uint32_t index:16; /* Start index to invalidate */ 365 uint32_t reserved_2:16; 366 #endif 367 }; 368 typedef struct VTDInvDescIEC VTDInvDescIEC; 369 370 /* Queued Invalidation Descriptor */ 371 union VTDInvDesc { 372 struct { 373 uint64_t lo; 374 uint64_t hi; 375 }; 376 struct { 377 uint64_t val[4]; 378 }; 379 union { 380 VTDInvDescIEC iec; 381 }; 382 }; 383 typedef union VTDInvDesc VTDInvDesc; 384 385 /* Page Request Descriptor */ 386 union VTDPRDesc { 387 struct { 388 uint64_t lo; 389 uint64_t hi; 390 }; 391 struct { 392 uint64_t val[4]; 393 }; 394 }; 395 typedef union VTDPRDesc VTDPRDesc; 396 397 /* Masks for struct VTDInvDesc */ 398 #define VTD_INV_DESC_ALL_ONE -1ULL 399 #define VTD_INV_DESC_TYPE(val) ((((val) >> 5) & 0x70ULL) | \ 400 ((val) & 0xfULL)) 401 #define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */ 402 #define VTD_INV_DESC_IOTLB 0x2 403 #define VTD_INV_DESC_DEVICE 0x3 404 #define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache 405 Invalidate Descriptor */ 406 #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */ 407 #define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc */ 408 #define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc */ 409 #define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB inv_desc*/ 410 #define VTD_INV_DESC_PGRESP 0x9 /* Page Group Response Desc */ 411 #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */ 412 413 /* Masks for Invalidation Wait Descriptor*/ 414 #define VTD_INV_DESC_WAIT_SW (1ULL << 5) 415 #define VTD_INV_DESC_WAIT_IF (1ULL << 4) 416 #define VTD_INV_DESC_WAIT_FN (1ULL << 6) 417 #define VTD_INV_DESC_WAIT_DATA_SHIFT 32 418 #define VTD_INV_DESC_WAIT_RSVD_LO 0Xfffff180ULL 419 #define VTD_INV_DESC_WAIT_RSVD_HI 3ULL 420 421 /* Masks for Context-cache Invalidation Descriptor */ 422 #define VTD_INV_DESC_CC_G (3ULL << 4) 423 #define VTD_INV_DESC_CC_GLOBAL (1ULL << 4) 424 #define VTD_INV_DESC_CC_DOMAIN (2ULL << 4) 425 #define VTD_INV_DESC_CC_DEVICE (3ULL << 4) 426 #define VTD_INV_DESC_CC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK) 427 #define VTD_INV_DESC_CC_SID(val) (((val) >> 32) & 0xffffUL) 428 #define VTD_INV_DESC_CC_FM(val) (((val) >> 48) & 3UL) 429 #define VTD_INV_DESC_CC_RSVD 0xfffc00000000f1c0ULL 430 431 /* Masks for IOTLB Invalidate Descriptor */ 432 #define VTD_INV_DESC_IOTLB_G (3ULL << 4) 433 #define VTD_INV_DESC_IOTLB_GLOBAL (1ULL << 4) 434 #define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4) 435 #define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4) 436 #define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK) 437 #define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL) 438 #define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL) 439 #define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000f100ULL 440 #define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL 441 442 /* Mask for Device IOTLB Invalidate Descriptor */ 443 #define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL) 444 #define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1) 445 #define VTD_INV_DESC_DEVICE_IOTLB_SID(val) (((val) >> 32) & 0xFFFFULL) 446 #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL 447 #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0f1f0 448 449 /* Masks for Interrupt Entry Invalidate Descriptor */ 450 #define VTD_INV_DESC_IEC_RSVD 0xffff000007fff1e0ULL 451 452 /* Masks for PASID based Device IOTLB Invalidate Descriptor */ 453 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \ 454 0xfffffffffffff000ULL) 455 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0x1) 456 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1) 457 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & 0xffffULL) 458 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & 0xfffffULL) 459 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL0 0xfff000000000f000ULL 460 #define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL1 0x7feULL 461 462 /* Mask for Page Group Response Descriptor */ 463 #define VTD_INV_DESC_PGRESP_RSVD_HI 0xfffffffffffff003ULL 464 #define VTD_INV_DESC_PGRESP_RSVD_LO 0xfff00000000001e0ULL 465 #define VTD_INV_DESC_PGRESP_PP(val) (((val) >> 4) & 0x1ULL) 466 #define VTD_INV_DESC_PGRESP_RC(val) (((val) >> 12) & 0xfULL) 467 #define VTD_INV_DESC_PGRESP_RID(val) (((val) >> 16) & 0xffffULL) 468 #define VTD_INV_DESC_PGRESP_PASID(val) (((val) >> 32) & 0xfffffULL) 469 #define VTD_INV_DESC_PGRESP_PRGI(val) (((val) >> 3) & 0x1ffULL) 470 471 /* Rsvd field masks for spte */ 472 #define VTD_SPTE_SNP 0x800ULL 473 474 #define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, stale_tm) \ 475 stale_tm ? \ 476 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ 477 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) 478 #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ 479 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) 480 #define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \ 481 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) 482 #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ 483 (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) 484 485 #define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, stale_tm) \ 486 stale_tm ? \ 487 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ 488 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) 489 #define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, stale_tm) \ 490 stale_tm ? \ 491 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ 492 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) 493 494 /* Rsvd field masks for fpte */ 495 #define VTD_FS_UPPER_IGNORED 0xfff0000000000000ULL 496 #define VTD_FPTE_PAGE_L1_RSVD_MASK(aw) \ 497 (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) 498 #define VTD_FPTE_PAGE_L2_RSVD_MASK(aw) \ 499 (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) 500 #define VTD_FPTE_PAGE_L3_RSVD_MASK(aw) \ 501 (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) 502 #define VTD_FPTE_PAGE_L4_RSVD_MASK(aw) \ 503 (0x80ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) 504 505 #define VTD_FPTE_LPAGE_L2_RSVD_MASK(aw) \ 506 (0x1fe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) 507 #define VTD_FPTE_LPAGE_L3_RSVD_MASK(aw) \ 508 (0x3fffe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED)) 509 510 /* Masks for PIOTLB Invalidate Descriptor */ 511 #define VTD_INV_DESC_PIOTLB_G (3ULL << 4) 512 #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) 513 #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) 514 #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK) 515 #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) 516 #define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL) 517 #define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1) 518 #define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL) 519 #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL 520 #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL 521 522 /* PASID-cache Invalidate Descriptor (pc_inv_dsc) fields */ 523 #define VTD_INV_DESC_PASIDC_G(x) extract64((x)->val[0], 4, 2) 524 #define VTD_INV_DESC_PASIDC_G_DSI 0 525 #define VTD_INV_DESC_PASIDC_G_PASID_SI 1 526 #define VTD_INV_DESC_PASIDC_G_GLOBAL 3 527 #define VTD_INV_DESC_PASIDC_DID(x) extract64((x)->val[0], 16, 16) 528 #define VTD_INV_DESC_PASIDC_PASID(x) extract64((x)->val[0], 32, 20) 529 #define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL 530 531 /* Page Request Descriptor */ 532 /* For the low 64-bit of 128-bit */ 533 #define VTD_PRD_TYPE (1ULL) 534 #define VTD_PRD_PP(val) (((val) & 1ULL) << 8) 535 #define VTD_PRD_RID(val) (((val) & 0xffffULL) << 16) 536 #define VTD_PRD_PASID(val) (((val) & 0xfffffULL) << 32) 537 #define VTD_PRD_EXR(val) (((val) & 1ULL) << 52) 538 #define VTD_PRD_PMR(val) (((val) & 1ULL) << 53) 539 /* For the high 64-bit of 128-bit */ 540 #define VTD_PRD_RDR(val) ((val) & 1ULL) 541 #define VTD_PRD_WRR(val) (((val) & 1ULL) << 1) 542 #define VTD_PRD_LPIG(val) (((val) & 1ULL) << 2) 543 #define VTD_PRD_PRGI(val) (((val) & 0x1ffULL) << 3) 544 #define VTD_PRD_ADDR(val) ((val) & 0xfffffffffffff000ULL) 545 546 /* Page Request Queue constants */ 547 #define VTD_PQA_ENTRY_SIZE 32 /* Size of an entry in bytes */ 548 /* Page Request Queue masks */ 549 #define VTD_PQA_ADDR 0xfffffffffffff000ULL /* PR queue address */ 550 #define VTD_PQA_SIZE 0x7ULL /* PR queue size */ 551 #define VTD_PR_STATUS_PPR 1UL /* Pending page request */ 552 #define VTD_PR_STATUS_PRO 2UL /* Page request overflow */ 553 #define VTD_PR_PECTL_IP 0x40000000UL /* PR control interrup pending */ 554 #define VTD_PR_PECTL_IM 0x80000000UL /* PR control interrup mask */ 555 556 /* Information about page-selective IOTLB invalidate */ 557 struct VTDIOTLBPageInvInfo { 558 uint16_t domain_id; 559 uint32_t pasid; 560 uint64_t addr; 561 uint64_t mask; 562 }; 563 typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo; 564 565 /* Pagesize of VTD paging structures, including root and context tables */ 566 #define VTD_PAGE_SHIFT 12 567 #define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT) 568 569 #define VTD_PAGE_SHIFT_4K 12 570 #define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1)) 571 #define VTD_PAGE_SHIFT_2M 21 572 #define VTD_PAGE_MASK_2M (~((1ULL << VTD_PAGE_SHIFT_2M) - 1)) 573 #define VTD_PAGE_SHIFT_1G 30 574 #define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1)) 575 576 struct VTDRootEntry { 577 uint64_t lo; 578 uint64_t hi; 579 }; 580 typedef struct VTDRootEntry VTDRootEntry; 581 582 /* Masks for struct VTDRootEntry */ 583 #define VTD_ROOT_ENTRY_P 1ULL 584 #define VTD_ROOT_ENTRY_CTP (~0xfffULL) 585 586 #define VTD_ROOT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDRootEntry)) 587 #define VTD_ROOT_ENTRY_RSVD(aw) (0xffeULL | ~VTD_HAW_MASK(aw)) 588 589 #define VTD_DEVFN_CHECK_MASK 0x80 590 591 /* Masks for struct VTDContextEntry */ 592 /* lo */ 593 #define VTD_CONTEXT_ENTRY_P (1ULL << 0) 594 #define VTD_CONTEXT_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */ 595 #define VTD_CONTEXT_ENTRY_TT (3ULL << 2) /* Translation Type */ 596 #define VTD_CONTEXT_TT_MULTI_LEVEL 0 597 #define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2) 598 #define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2) 599 /* Second Level Page Translation Pointer*/ 600 #define VTD_CONTEXT_ENTRY_SLPTPTR (~0xfffULL) 601 #define VTD_CONTEXT_ENTRY_RSVD_LO(aw) (0xff0ULL | ~VTD_HAW_MASK(aw)) 602 /* hi */ 603 #define VTD_CONTEXT_ENTRY_AW 7ULL /* Adjusted guest-address-width */ 604 #define VTD_CONTEXT_ENTRY_DID(val) (((val) >> 8) & VTD_DOMAIN_ID_MASK) 605 #define VTD_CONTEXT_ENTRY_RSVD_HI 0xffffffffff000080ULL 606 607 #define VTD_CONTEXT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDContextEntry)) 608 609 #define VTD_CTX_ENTRY_LEGACY_SIZE 16 610 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 611 612 #define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff 613 #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) 614 #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL 615 #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL 616 617 typedef struct VTDPASIDCacheInfo { 618 uint8_t type; 619 uint16_t did; 620 uint32_t pasid; 621 } VTDPASIDCacheInfo; 622 623 /* PASID Table Related Definitions */ 624 #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) 625 #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) 626 #define VTD_PASID_DIR_ENTRY_SIZE 8 627 #define VTD_PASID_ENTRY_SIZE 64 628 #define VTD_PASID_DIR_BITS_MASK (0x3fffULL) 629 #define VTD_PASID_DIR_INDEX(pasid) (((pasid) >> 6) & VTD_PASID_DIR_BITS_MASK) 630 #define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disable */ 631 #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) 632 #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) 633 #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */ 634 635 /* PASID Granular Translation Type Mask */ 636 #define VTD_PASID_ENTRY_P 1ULL 637 #define VTD_SM_PASID_ENTRY_PGTT (7ULL << 6) 638 #define VTD_SM_PASID_ENTRY_FLT (1ULL << 6) 639 #define VTD_SM_PASID_ENTRY_SLT (2ULL << 6) 640 #define VTD_SM_PASID_ENTRY_NESTED (3ULL << 6) 641 #define VTD_SM_PASID_ENTRY_PT (4ULL << 6) 642 643 #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */ 644 #define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) 645 646 #define VTD_SM_PASID_ENTRY_FLPM 3ULL 647 #define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) 648 649 /* First Level Paging Structure */ 650 /* Masks for First Level Paging Entry */ 651 #define VTD_FL_P 1ULL 652 #define VTD_FL_RW (1ULL << 1) 653 #define VTD_FL_US (1ULL << 2) 654 #define VTD_FL_A (1ULL << 5) 655 #define VTD_FL_D (1ULL << 6) 656 657 /* Second Level Page Translation Pointer*/ 658 #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) 659 660 /* Second Level Paging Structure */ 661 /* Masks for Second Level Paging Entry */ 662 #define VTD_SL_RW_MASK 3ULL 663 #define VTD_SL_R 1ULL 664 #define VTD_SL_W (1ULL << 1) 665 #define VTD_SL_IGN_COM 0xbff0000000000000ULL 666 #define VTD_SL_TM (1ULL << 62) 667 668 /* Common for both First Level and Second Level */ 669 #define VTD_PML4_LEVEL 4 670 #define VTD_PDP_LEVEL 3 671 #define VTD_PD_LEVEL 2 672 #define VTD_PT_LEVEL 1 673 #define VTD_PT_ENTRY_NR 512 674 #define VTD_PT_PAGE_SIZE_MASK (1ULL << 7) 675 #define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw)) 676 677 /* Bits to decide the offset for each level */ 678 #define VTD_LEVEL_BITS 9 679 680 #endif 681