1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #ifndef _AMPHION_VPU_DEFS_H 7 #define _AMPHION_VPU_DEFS_H 8 9 enum MSG_TYPE { 10 INIT_DONE = 1, 11 PRC_BUF_OFFSET, 12 BOOT_ADDRESS, 13 COMMAND, 14 EVENT, 15 }; 16 17 enum { 18 VPU_IRQ_CODE_BOOT_DONE = 0x55, 19 VPU_IRQ_CODE_SNAPSHOT_DONE = 0xa5, 20 VPU_IRQ_CODE_SYNC = 0xaa, 21 }; 22 23 enum { 24 VPU_CMD_ID_NOOP = 0x0, 25 VPU_CMD_ID_CONFIGURE_CODEC, 26 VPU_CMD_ID_START, 27 VPU_CMD_ID_STOP, 28 VPU_CMD_ID_ABORT, 29 VPU_CMD_ID_RST_BUF, 30 VPU_CMD_ID_SNAPSHOT, 31 VPU_CMD_ID_FIRM_RESET, 32 VPU_CMD_ID_UPDATE_PARAMETER, 33 VPU_CMD_ID_FRAME_ENCODE, 34 VPU_CMD_ID_SKIP, 35 VPU_CMD_ID_PARSE_NEXT_SEQ, 36 VPU_CMD_ID_PARSE_NEXT_I, 37 VPU_CMD_ID_PARSE_NEXT_IP, 38 VPU_CMD_ID_PARSE_NEXT_ANY, 39 VPU_CMD_ID_DEC_PIC, 40 VPU_CMD_ID_FS_ALLOC, 41 VPU_CMD_ID_FS_RELEASE, 42 VPU_CMD_ID_TIMESTAMP, 43 VPU_CMD_ID_DEBUG 44 }; 45 46 enum { 47 VPU_MSG_ID_NOOP = 0x100, 48 VPU_MSG_ID_RESET_DONE, 49 VPU_MSG_ID_START_DONE, 50 VPU_MSG_ID_STOP_DONE, 51 VPU_MSG_ID_ABORT_DONE, 52 VPU_MSG_ID_BUF_RST, 53 VPU_MSG_ID_MEM_REQUEST, 54 VPU_MSG_ID_PARAM_UPD_DONE, 55 VPU_MSG_ID_FRAME_INPUT_DONE, 56 VPU_MSG_ID_ENC_DONE, 57 VPU_MSG_ID_DEC_DONE, 58 VPU_MSG_ID_FRAME_REQ, 59 VPU_MSG_ID_FRAME_RELEASE, 60 VPU_MSG_ID_SEQ_HDR_FOUND, 61 VPU_MSG_ID_RES_CHANGE, 62 VPU_MSG_ID_PIC_HDR_FOUND, 63 VPU_MSG_ID_PIC_DECODED, 64 VPU_MSG_ID_PIC_EOS, 65 VPU_MSG_ID_FIFO_LOW, 66 VPU_MSG_ID_FIFO_HIGH, 67 VPU_MSG_ID_FIFO_EMPTY, 68 VPU_MSG_ID_FIFO_FULL, 69 VPU_MSG_ID_BS_ERROR, 70 VPU_MSG_ID_UNSUPPORTED, 71 VPU_MSG_ID_TIMESTAMP_INFO, 72 VPU_MSG_ID_FIRMWARE_XCPT, 73 VPU_MSG_ID_PIC_SKIPPED, 74 VPU_MSG_ID_DBG_MSG, 75 }; 76 77 enum VPU_ENC_MEMORY_RESOURSE { 78 MEM_RES_ENC, 79 MEM_RES_REF, 80 MEM_RES_ACT 81 }; 82 83 enum VPU_DEC_MEMORY_RESOURCE { 84 MEM_RES_FRAME, 85 MEM_RES_MBI, 86 MEM_RES_DCP 87 }; 88 89 enum VPU_SCODE_TYPE { 90 SCODE_PADDING_EOS = 1, 91 SCODE_PADDING_BUFFLUSH = 2, 92 SCODE_PADDING_ABORT = 3, 93 SCODE_SEQUENCE = 0x31, 94 SCODE_PICTURE = 0x32, 95 SCODE_SLICE = 0x33 96 }; 97 98 struct vpu_pkt_mem_req_data { 99 u32 enc_frame_size; 100 u32 enc_frame_num; 101 u32 ref_frame_size; 102 u32 ref_frame_num; 103 u32 act_buf_size; 104 u32 act_buf_num; 105 }; 106 107 struct vpu_enc_pic_info { 108 u32 frame_id; 109 u32 pic_type; 110 u32 skipped_frame; 111 u32 error_flag; 112 u32 psnr; 113 u32 frame_size; 114 u32 wptr; 115 u32 crc; 116 s64 timestamp; 117 }; 118 119 struct vpu_dec_codec_info { 120 u32 pixfmt; 121 u32 num_ref_frms; 122 u32 num_dpb_frms; 123 u32 num_dfe_area; 124 u32 color_primaries; 125 u32 transfer_chars; 126 u32 matrix_coeffs; 127 u32 full_range; 128 u32 vui_present; 129 u32 progressive; 130 u32 width; 131 u32 height; 132 u32 decoded_width; 133 u32 decoded_height; 134 struct v4l2_fract frame_rate; 135 u32 dsp_asp_ratio; 136 u32 level_idc; 137 u32 bit_depth_luma; 138 u32 bit_depth_chroma; 139 u32 chroma_fmt; 140 u32 mvc_num_views; 141 u32 offset_x; 142 u32 offset_y; 143 u32 tag; 144 u32 sizeimage[VIDEO_MAX_PLANES]; 145 u32 bytesperline[VIDEO_MAX_PLANES]; 146 u32 mbi_size; 147 u32 dcp_size; 148 u32 stride; 149 }; 150 151 struct vpu_dec_pic_info { 152 u32 id; 153 u32 luma; 154 u32 start; 155 u32 end; 156 u32 pic_size; 157 u32 stride; 158 u32 skipped; 159 s64 timestamp; 160 u32 consumed_count; 161 }; 162 163 struct vpu_fs_info { 164 u32 id; 165 u32 type; 166 u32 tag; 167 u32 luma_addr; 168 u32 luma_size; 169 u32 chroma_addr; 170 u32 chromau_size; 171 u32 chromav_addr; 172 u32 chromav_size; 173 u32 bytesperline; 174 u32 not_displayed; 175 }; 176 177 struct vpu_ts_info { 178 s64 timestamp; 179 u32 size; 180 }; 181 182 #define BITRATE_STEP (1024) 183 #define BITRATE_MIN (16 * BITRATE_STEP) 184 #define BITRATE_MAX (240 * 1024 * BITRATE_STEP) 185 #define BITRATE_DEFAULT (2 * 1024 * BITRATE_STEP) 186 #define BITRATE_DEFAULT_PEAK (BITRATE_DEFAULT * 2) 187 188 #endif 189