1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2020-2023 Intel Corporation
4  */
5 
6 #ifndef __IVPU_HW_40XX_REG_H__
7 #define __IVPU_HW_40XX_REG_H__
8 
9 #include <linux/bits.h>
10 
11 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT				0x00000000u
12 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK		BIT_MASK(0)
13 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK			BIT_MASK(1)
14 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI0_ERR_MASK			BIT_MASK(2)
15 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI1_ERR_MASK			BIT_MASK(3)
16 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR0_ERR_MASK			BIT_MASK(4)
17 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR1_ERR_MASK			BIT_MASK(5)
18 #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_SURV_ERR_MASK			BIT_MASK(6)
19 
20 #define VPU_40XX_BUTTRESS_LOCAL_INT_MASK				0x00000004u
21 #define VPU_40XX_BUTTRESS_GLOBAL_INT_MASK				0x00000008u
22 
23 #define VPU_40XX_BUTTRESS_HM_ATS					0x0000000cu
24 
25 #define VPU_40XX_BUTTRESS_ATS_ERR_LOG1					0x00000010u
26 #define VPU_40XX_BUTTRESS_ATS_ERR_LOG2					0x00000014u
27 #define VPU_40XX_BUTTRESS_ATS_ERR_CLEAR					0x00000018u
28 
29 #define VPU_40XX_BUTTRESS_CFI0_ERR_LOG					0x0000001cu
30 #define VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR				0x00000020u
31 
32 #define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS			0x00000024u
33 
34 #define VPU_40XX_BUTTRESS_CFI1_ERR_LOG					0x00000040u
35 #define VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR				0x00000044u
36 
37 #define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW				0x00000048u
38 #define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH				0x0000004cu
39 #define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR				0x00000050u
40 
41 #define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS			0x00000054u
42 
43 #define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW				0x00000058u
44 #define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH				0x0000005cu
45 #define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR				0x00000060u
46 
47 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0				0x00000130u
48 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK		GENMASK(15, 0)
49 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK		GENMASK(31, 16)
50 
51 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1				0x00000134u
52 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK		GENMASK(15, 0)
53 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK			GENMASK(31, 16)
54 
55 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2				0x00000138u
56 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK			GENMASK(15, 0)
57 #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CDYN_MASK			GENMASK(31, 16)
58 
59 #define VPU_40XX_BUTTRESS_WP_REQ_CMD					0x0000013cu
60 #define VPU_40XX_BUTTRESS_WP_REQ_CMD_SEND_MASK				BIT_MASK(0)
61 
62 #define VPU_40XX_BUTTRESS_PLL_FREQ					0x00000148u
63 #define VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK				GENMASK(15, 0)
64 
65 #define VPU_40XX_BUTTRESS_TILE_FUSE					0x00000150u
66 #define VPU_40XX_BUTTRESS_TILE_FUSE_VALID_MASK				BIT_MASK(0)
67 #define VPU_40XX_BUTTRESS_TILE_FUSE_CONFIG_MASK				GENMASK(6, 1)
68 
69 #define VPU_40XX_BUTTRESS_VPU_STATUS					0x00000154u
70 #define VPU_40XX_BUTTRESS_VPU_STATUS_READY_MASK				BIT_MASK(0)
71 #define VPU_40XX_BUTTRESS_VPU_STATUS_IDLE_MASK				BIT_MASK(1)
72 #define VPU_40XX_BUTTRESS_VPU_STATUS_DUP_IDLE_MASK			BIT_MASK(2)
73 #define VPU_40XX_BUTTRESS_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK	BIT_MASK(6)
74 #define VPU_40XX_BUTTRESS_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK	BIT_MASK(7)
75 #define VPU_40XX_BUTTRESS_VPU_STATUS_PERF_CLK_MASK			BIT_MASK(11)
76 #define VPU_40XX_BUTTRESS_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK        BIT_MASK(12)
77 
78 #define VPU_40XX_BUTTRESS_IP_RESET					0x00000160u
79 #define VPU_40XX_BUTTRESS_IP_RESET_TRIGGER_MASK				BIT_MASK(0)
80 
81 #define VPU_40XX_BUTTRESS_D0I3_CONTROL					0x00000164u
82 #define VPU_40XX_BUTTRESS_D0I3_CONTROL_INPROGRESS_MASK			BIT_MASK(0)
83 #define VPU_40XX_BUTTRESS_D0I3_CONTROL_I3_MASK				BIT_MASK(2)
84 
85 #define VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET				0x00000168u
86 #define VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE				0x0000016cu
87 #define VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE				0x00000170u
88 
89 #define VPU_40XX_BUTTRESS_FMIN_FUSE					0x00000174u
90 #define VPU_40XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK			GENMASK(7, 0)
91 #define VPU_40XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK			GENMASK(15, 8)
92 
93 #define VPU_40XX_BUTTRESS_FMAX_FUSE					0x00000178u
94 #define VPU_40XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK			GENMASK(7, 0)
95 
96 #define VPU_40XX_HOST_SS_CPR_CLK_EN					0x00000080u
97 #define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK			BIT_MASK(1)
98 #define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK			BIT_MASK(10)
99 #define VPU_40XX_HOST_SS_CPR_CLK_EN_CSS_MAS_MASK			BIT_MASK(11)
100 
101 #define VPU_40XX_HOST_SS_CPR_CLK_SET					0x00000084u
102 #define VPU_40XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK			BIT_MASK(1)
103 #define VPU_40XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK			BIT_MASK(10)
104 #define VPU_40XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK			BIT_MASK(11)
105 
106 #define VPU_40XX_HOST_SS_CPR_RST_EN					0x00000090u
107 #define VPU_40XX_HOST_SS_CPR_RST_EN_TOP_NOC_MASK			BIT_MASK(1)
108 #define VPU_40XX_HOST_SS_CPR_RST_EN_DSS_MAS_MASK			BIT_MASK(10)
109 #define VPU_40XX_HOST_SS_CPR_RST_EN_CSS_MAS_MASK			BIT_MASK(11)
110 
111 #define VPU_40XX_HOST_SS_CPR_RST_SET					0x00000094u
112 #define VPU_40XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK			BIT_MASK(1)
113 #define VPU_40XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK			BIT_MASK(10)
114 #define VPU_40XX_HOST_SS_CPR_RST_SET_MSS_MAS_MASK			BIT_MASK(11)
115 
116 #define VPU_40XX_HOST_SS_CPR_RST_CLR					0x00000098u
117 #define VPU_40XX_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK			BIT_MASK(1)
118 #define VPU_40XX_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK			BIT_MASK(10)
119 #define VPU_40XX_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK			BIT_MASK(11)
120 
121 #define VPU_40XX_HOST_SS_HW_VERSION					0x00000108u
122 #define VPU_40XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK			GENMASK(7, 0)
123 #define VPU_40XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK			GENMASK(15, 8)
124 #define VPU_40XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK			GENMASK(23, 16)
125 
126 #define VPU_40XX_HOST_SS_SW_VERSION					0x0000010cu
127 
128 #define VPU_40XX_HOST_SS_GEN_CTRL					0x00000118u
129 #define VPU_40XX_HOST_SS_GEN_CTRL_PS_MASK				GENMASK(31, 29)
130 
131 #define VPU_40XX_HOST_SS_NOC_QREQN					0x00000154u
132 #define VPU_40XX_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK			BIT_MASK(0)
133 
134 #define VPU_40XX_HOST_SS_NOC_QACCEPTN					0x00000158u
135 #define VPU_40XX_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK			BIT_MASK(0)
136 
137 #define VPU_40XX_HOST_SS_NOC_QDENY					0x0000015cu
138 #define VPU_40XX_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK			BIT_MASK(0)
139 
140 #define VPU_40XX_TOP_NOC_QREQN						0x00000160u
141 #define VPU_40XX_TOP_NOC_QREQN_CPU_CTRL_MASK				BIT_MASK(0)
142 #define VPU_40XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK			BIT_MASK(2)
143 
144 #define VPU_40XX_TOP_NOC_QACCEPTN					0x00000164u
145 #define VPU_40XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK				BIT_MASK(0)
146 #define VPU_40XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK			BIT_MASK(2)
147 
148 #define VPU_40XX_TOP_NOC_QDENY						0x00000168u
149 #define VPU_40XX_TOP_NOC_QDENY_CPU_CTRL_MASK				BIT_MASK(0)
150 #define VPU_40XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK			BIT_MASK(2)
151 
152 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN					0x00000170u
153 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK			BIT_MASK(0)
154 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK			BIT_MASK(1)
155 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK			BIT_MASK(2)
156 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK			BIT_MASK(3)
157 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK			BIT_MASK(4)
158 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK			BIT_MASK(5)
159 #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK			BIT_MASK(6)
160 
161 #define VPU_40XX_HOST_SS_ICB_STATUS_0					0x00010210u
162 #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK			BIT_MASK(0)
163 #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK			BIT_MASK(1)
164 #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK			BIT_MASK(2)
165 #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK			BIT_MASK(3)
166 #define VPU_40XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK		BIT_MASK(4)
167 #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK		BIT_MASK(5)
168 #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK		BIT_MASK(6)
169 #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK		BIT_MASK(7)
170 #define VPU_40XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK		BIT_MASK(8)
171 #define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK	BIT_MASK(30)
172 #define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK	BIT_MASK(31)
173 
174 #define VPU_40XX_HOST_SS_ICB_STATUS_1					0x00010214u
175 #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK	BIT_MASK(0)
176 #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK	BIT_MASK(1)
177 #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK	BIT_MASK(2)
178 
179 #define VPU_40XX_HOST_SS_ICB_CLEAR_0					0x00010220u
180 #define VPU_40XX_HOST_SS_ICB_CLEAR_1					0x00010224u
181 #define VPU_40XX_HOST_SS_ICB_ENABLE_0					0x00010240u
182 #define VPU_40XX_HOST_SS_ICB_ENABLE_1					0x00010244u
183 
184 #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM				0x000200f4u
185 
186 #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT				0x000200fcu
187 #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK		GENMASK(23, 16)
188 
189 #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0				0x00030020u
190 #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0_CSS_CPU_MASK			BIT_MASK(3)
191 
192 #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0				0x00030024u
193 #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0_CSS_CPU_MASK		BIT_MASK(3)
194 
195 #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0			0x00030028u
196 #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_CSS_CPU_MASK	BIT_MASK(3)
197 
198 #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0				0x0003002cu
199 #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK		BIT_MASK(3)
200 
201 #define VPU_40XX_HOST_SS_AON_IDLE_GEN					0x00030200u
202 #define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK				BIT_MASK(0)
203 #define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK			BIT_MASK(1)
204 
205 #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE					0x00030204u
206 #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK			BIT_MASK(0)
207 
208 #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO			0x00040040u
209 #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK		BIT_MASK(0)
210 #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK	GENMASK(2, 1)
211 #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK	GENMASK(31, 3)
212 
213 #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR			0x00082020u
214 #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK	GENMASK(15, 0)
215 #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK		GENMASK(31, 16)
216 
217 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES				0x00360000u
218 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK	BIT_MASK(0)
219 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK	BIT_MASK(1)
220 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK	BIT_MASK(2)
221 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_SNOOP_OVERRIDE_EN_MASK	BIT_MASK(3)
222 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AW_SNOOP_OVERRIDE_MASK	BIT_MASK(4)
223 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AR_SNOOP_OVERRIDE_MASK	BIT_MASK(5)
224 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK	GENMASK(10, 6)
225 #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK	GENMASK(15, 11)
226 
227 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV					0x00360004u
228 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK		BIT_MASK(0)
229 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK		BIT_MASK(1)
230 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK		BIT_MASK(2)
231 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK		BIT_MASK(3)
232 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK		BIT_MASK(4)
233 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK		BIT_MASK(5)
234 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK		BIT_MASK(6)
235 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK		BIT_MASK(7)
236 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK		BIT_MASK(8)
237 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK		BIT_MASK(9)
238 
239 #define VPU_40XX_CPU_SS_DSU_LEON_RT_BASE				0x04000000u
240 #define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_CTRL				0x04000000u
241 #define VPU_40XX_CPU_SS_DSU_LEON_RT_PC_REG				0x04400010u
242 #define VPU_40XX_CPU_SS_DSU_LEON_RT_NPC_REG				0x04400014u
243 #define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG			0x04400020u
244 
245 #define VPU_40XX_CPU_SS_TIM_WATCHDOG					0x0102009cu
246 #define VPU_40XX_CPU_SS_TIM_WDOG_EN					0x010200a4u
247 #define VPU_40XX_CPU_SS_TIM_SAFE					0x010200a8u
248 
249 #define VPU_40XX_CPU_SS_TIM_GEN_CONFIG					0x01021008u
250 #define VPU_40XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK		BIT_MASK(9)
251 
252 #define VPU_40XX_CPU_SS_CPR_NOC_QREQN					0x01010030u
253 #define VPU_40XX_CPU_SS_CPR_NOC_QREQN_TOP_MMIO_MASK			BIT_MASK(0)
254 
255 #define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN				0x01010034u
256 #define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN_TOP_MMIO_MASK			BIT_MASK(0)
257 
258 #define VPU_40XX_CPU_SS_CPR_NOC_QDENY					0x01010038u
259 #define VPU_40XX_CPU_SS_CPR_NOC_QDENY_TOP_MMIO_MASK			BIT_MASK(0)
260 
261 #define VPU_40XX_CPU_SS_TIM_IPC_FIFO					0x010200f0u
262 #define VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT				0x01029008u
263 
264 #define VPU_40XX_CPU_SS_DOORBELL_0					0x01300000u
265 #define VPU_40XX_CPU_SS_DOORBELL_0_SET_MASK				BIT_MASK(0)
266 
267 #define VPU_40XX_CPU_SS_DOORBELL_1					0x01301000u
268 
269 #endif /* __IVPU_HW_40XX_REG_H__ */
270