1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TC358775 DSI to LVDS bridge driver 4 * 5 * Copyright (C) 2020 SMART Wireless Computing 6 * Author: Vinay Simha BN <simhavcs@gmail.com> 7 * 8 */ 9 /* #define DEBUG */ 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/kernel.h> 16 #include <linux/media-bus-format.h> 17 #include <linux/module.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/slab.h> 20 21 #include <asm/unaligned.h> 22 23 #include <drm/display/drm_dp_helper.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_mipi_dsi.h> 27 #include <drm/drm_of.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_probe_helper.h> 30 31 #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val) 32 33 /* Registers */ 34 35 /* DSI D-PHY Layer Registers */ 36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */ 37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */ 38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */ 39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */ 40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */ 41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */ 42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */ 43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */ 44 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */ 45 #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */ 46 #define D2W_CNTRL 0x004C /* Data Lane 2 Control */ 47 #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */ 48 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */ 49 50 /* DSI PPI Layer Registers */ 51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */ 52 #define PPI_START_FUNCTION 1 53 54 #define PPI_BUSYPPI 0x0108 55 #define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */ 56 #define PPI_LPTXTIMECNT 0x0114 57 #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */ 58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */ 59 60 /* Analog timer function enable */ 61 #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */ 62 #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */ 63 #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */ 64 #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */ 65 #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */ 66 67 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */ 68 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */ 69 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */ 70 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */ 71 72 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */ 73 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */ 74 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */ 75 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */ 76 #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */ 77 #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */ 78 #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */ 79 #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */ 80 #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */ 81 #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */ 82 #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */ 83 #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */ 84 #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */ 85 #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */ 86 #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */ 87 88 #define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */ 89 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */ 90 #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */ 91 #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */ 92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */ 93 #define DSI_RX_START 1 94 95 #define DSI_BUSYDSI 0x0208 96 #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */ 97 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */ 98 #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */ 99 100 #define DSI_INTSTATUS 0x0220 /* Interrupt Status */ 101 #define DSI_INTMASK 0x0224 /* Interrupt Mask */ 102 #define DSI_INTCLR 0x0228 /* Interrupt Clear */ 103 #define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */ 104 105 #define DSIERRCNT 0x0300 /* DSI Error Count */ 106 #define APLCTRL 0x0400 /* Application Layer Control */ 107 #define RDPKTLN 0x0404 /* Command Read Packet Length */ 108 109 #define VPCTRL 0x0450 /* Video Path Control */ 110 #define HTIM1 0x0454 /* Horizontal Timing Control 1 */ 111 #define HTIM2 0x0458 /* Horizontal Timing Control 2 */ 112 #define VTIM1 0x045C /* Vertical Timing Control 1 */ 113 #define VTIM2 0x0460 /* Vertical Timing Control 2 */ 114 #define VFUEN 0x0464 /* Video Frame Timing Update Enable */ 115 #define VFUEN_EN BIT(0) /* Upload Enable */ 116 117 /* Mux Input Select for LVDS LINK Input */ 118 #define LV_MX0003 0x0480 /* Bit 0 to 3 */ 119 #define LV_MX0407 0x0484 /* Bit 4 to 7 */ 120 #define LV_MX0811 0x0488 /* Bit 8 to 11 */ 121 #define LV_MX1215 0x048C /* Bit 12 to 15 */ 122 #define LV_MX1619 0x0490 /* Bit 16 to 19 */ 123 #define LV_MX2023 0x0494 /* Bit 20 to 23 */ 124 #define LV_MX2427 0x0498 /* Bit 24 to 27 */ 125 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \ 126 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24)) 127 128 /* Input bit numbers used in mux registers */ 129 enum { 130 LVI_R0, 131 LVI_R1, 132 LVI_R2, 133 LVI_R3, 134 LVI_R4, 135 LVI_R5, 136 LVI_R6, 137 LVI_R7, 138 LVI_G0, 139 LVI_G1, 140 LVI_G2, 141 LVI_G3, 142 LVI_G4, 143 LVI_G5, 144 LVI_G6, 145 LVI_G7, 146 LVI_B0, 147 LVI_B1, 148 LVI_B2, 149 LVI_B3, 150 LVI_B4, 151 LVI_B5, 152 LVI_B6, 153 LVI_B7, 154 LVI_HS, 155 LVI_VS, 156 LVI_DE, 157 LVI_L0 158 }; 159 160 #define LVCFG 0x049C /* LVDS Configuration */ 161 #define LVPHY0 0x04A0 /* LVDS PHY 0 */ 162 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ 163 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) 164 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ 165 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ 166 167 #define LVPHY1 0x04A4 /* LVDS PHY 1 */ 168 #define SYSSTAT 0x0500 /* System Status */ 169 #define SYSRST 0x0504 /* System Reset */ 170 171 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ 172 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ 173 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ 174 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ 175 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ 176 #define SYS_RST_REG BIT(5) /* Reset Register module */ 177 178 /* GPIO Registers */ 179 #define GPIOC 0x0520 /* GPIO Control */ 180 #define GPIOO 0x0524 /* GPIO Output */ 181 #define GPIOI 0x0528 /* GPIO Input */ 182 183 /* I2C Registers */ 184 #define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */ 185 #define I2CMADDR 0x0544 /* I2C Master Addressing */ 186 #define WDATAQ 0x0548 /* Write Data Queue */ 187 #define RDATAQ 0x054C /* Read Data Queue */ 188 189 /* Chip ID and Revision ID Register */ 190 #define IDREG 0x0580 191 192 #define LPX_PERIOD 4 193 #define TTA_GET 0x40000 194 #define TTA_SURE 6 195 #define SINGLE_LINK 1 196 #define DUAL_LINK 2 197 198 #define TC358775XBG_ID 0x00007500 199 200 /* Debug Registers */ 201 #define DEBUG00 0x05A0 /* Debug */ 202 #define DEBUG01 0x05A4 /* LVDS Data */ 203 204 #define DSI_CLEN_BIT BIT(0) 205 #define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */ 206 #define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */ 207 #define LVCFG_LVEN_BIT BIT(0) 208 209 #define L0EN BIT(1) 210 211 #define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000 212 #define TC358775_VPCTRL_VSDELAY__SHIFT 20 TC358775_VPCTRL_VSDELAY(uint32_t val)213 static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val) 214 { 215 return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) & 216 TC358775_VPCTRL_VSDELAY__MASK; 217 } 218 219 #define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100 220 #define TC358775_VPCTRL_OPXLFMT__SHIFT 8 TC358775_VPCTRL_OPXLFMT(uint32_t val)221 static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val) 222 { 223 return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) & 224 TC358775_VPCTRL_OPXLFMT__MASK; 225 } 226 227 #define TC358775_VPCTRL_MSF__MASK 0x00000001 228 #define TC358775_VPCTRL_MSF__SHIFT 0 TC358775_VPCTRL_MSF(uint32_t val)229 static inline u32 TC358775_VPCTRL_MSF(uint32_t val) 230 { 231 return ((val) << TC358775_VPCTRL_MSF__SHIFT) & 232 TC358775_VPCTRL_MSF__MASK; 233 } 234 235 #define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0 236 #define TC358775_LVCFG_PCLKDIV__SHIFT 4 TC358775_LVCFG_PCLKDIV(uint32_t val)237 static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val) 238 { 239 return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) & 240 TC358775_LVCFG_PCLKDIV__MASK; 241 } 242 243 #define TC358775_LVCFG_LVDLINK__MASK 0x00000002 244 #define TC358775_LVCFG_LVDLINK__SHIFT 1 TC358775_LVCFG_LVDLINK(uint32_t val)245 static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val) 246 { 247 return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) & 248 TC358775_LVCFG_LVDLINK__MASK; 249 } 250 251 enum tc358775_ports { 252 TC358775_DSI_IN, 253 TC358775_LVDS_OUT0, 254 TC358775_LVDS_OUT1, 255 }; 256 257 struct tc_data { 258 struct i2c_client *i2c; 259 struct device *dev; 260 261 struct drm_bridge bridge; 262 struct drm_bridge *panel_bridge; 263 264 struct device_node *host_node; 265 struct mipi_dsi_device *dsi; 266 u8 num_dsi_lanes; 267 268 struct regulator *vdd; 269 struct regulator *vddio; 270 struct gpio_desc *reset_gpio; 271 struct gpio_desc *stby_gpio; 272 u8 lvds_link; /* single-link or dual-link */ 273 u8 bpc; 274 }; 275 bridge_to_tc(struct drm_bridge * b)276 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 277 { 278 return container_of(b, struct tc_data, bridge); 279 } 280 tc_bridge_pre_enable(struct drm_bridge * bridge)281 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 282 { 283 struct tc_data *tc = bridge_to_tc(bridge); 284 struct device *dev = &tc->dsi->dev; 285 int ret; 286 287 ret = regulator_enable(tc->vddio); 288 if (ret < 0) 289 dev_err(dev, "regulator vddio enable failed, %d\n", ret); 290 usleep_range(10000, 11000); 291 292 ret = regulator_enable(tc->vdd); 293 if (ret < 0) 294 dev_err(dev, "regulator vdd enable failed, %d\n", ret); 295 usleep_range(10000, 11000); 296 297 gpiod_set_value(tc->stby_gpio, 0); 298 usleep_range(10000, 11000); 299 300 gpiod_set_value(tc->reset_gpio, 0); 301 usleep_range(10, 20); 302 } 303 tc_bridge_post_disable(struct drm_bridge * bridge)304 static void tc_bridge_post_disable(struct drm_bridge *bridge) 305 { 306 struct tc_data *tc = bridge_to_tc(bridge); 307 struct device *dev = &tc->dsi->dev; 308 int ret; 309 310 gpiod_set_value(tc->reset_gpio, 1); 311 usleep_range(10, 20); 312 313 gpiod_set_value(tc->stby_gpio, 1); 314 usleep_range(10000, 11000); 315 316 ret = regulator_disable(tc->vdd); 317 if (ret < 0) 318 dev_err(dev, "regulator vdd disable failed, %d\n", ret); 319 usleep_range(10000, 11000); 320 321 ret = regulator_disable(tc->vddio); 322 if (ret < 0) 323 dev_err(dev, "regulator vddio disable failed, %d\n", ret); 324 usleep_range(10000, 11000); 325 } 326 d2l_read(struct i2c_client * i2c,u16 addr,u32 * val)327 static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val) 328 { 329 int ret; 330 u8 buf_addr[2]; 331 332 put_unaligned_be16(addr, buf_addr); 333 ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr)); 334 if (ret < 0) 335 goto fail; 336 337 ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val)); 338 if (ret < 0) 339 goto fail; 340 341 pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val); 342 return; 343 344 fail: 345 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n", 346 ret, addr); 347 } 348 d2l_write(struct i2c_client * i2c,u16 addr,u32 val)349 static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val) 350 { 351 u8 data[6]; 352 int ret; 353 354 put_unaligned_be16(addr, data); 355 put_unaligned_le32(val, data + 2); 356 357 ret = i2c_master_send(i2c, data, ARRAY_SIZE(data)); 358 if (ret < 0) 359 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n", 360 ret, addr); 361 } 362 363 /* helper function to access bus_formats */ get_connector(struct drm_encoder * encoder)364 static struct drm_connector *get_connector(struct drm_encoder *encoder) 365 { 366 struct drm_device *dev = encoder->dev; 367 struct drm_connector *connector; 368 369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 370 if (connector->encoder == encoder) 371 return connector; 372 373 return NULL; 374 } 375 tc_bridge_enable(struct drm_bridge * bridge)376 static void tc_bridge_enable(struct drm_bridge *bridge) 377 { 378 struct tc_data *tc = bridge_to_tc(bridge); 379 u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2; 380 u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2; 381 u32 val = 0; 382 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay; 383 struct drm_display_mode *mode; 384 struct drm_connector *connector = get_connector(bridge->encoder); 385 386 mode = &bridge->encoder->crtc->state->adjusted_mode; 387 388 hback_porch = mode->htotal - mode->hsync_end; 389 hsync_len = mode->hsync_end - mode->hsync_start; 390 vback_porch = mode->vtotal - mode->vsync_end; 391 vsync_len = mode->vsync_end - mode->vsync_start; 392 393 htime1 = (hback_porch << 16) + hsync_len; 394 vtime1 = (vback_porch << 16) + vsync_len; 395 396 hfront_porch = mode->hsync_start - mode->hdisplay; 397 hactive = mode->hdisplay; 398 vfront_porch = mode->vsync_start - mode->vdisplay; 399 vactive = mode->vdisplay; 400 401 htime2 = (hfront_porch << 16) + hactive; 402 vtime2 = (vfront_porch << 16) + vactive; 403 404 d2l_read(tc->i2c, IDREG, &val); 405 406 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n", 407 (val >> 8) & 0xFF, val & 0xFF); 408 409 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM | 410 SYS_RST_LCD | SYS_RST_I2CM); 411 usleep_range(30000, 40000); 412 413 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 414 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD); 415 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3); 416 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3); 417 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3); 418 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3); 419 420 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT; 421 d2l_write(tc->i2c, PPI_LANEENABLE, val); 422 d2l_write(tc->i2c, DSI_LANEENABLE, val); 423 424 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION); 425 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START); 426 427 if (tc->bpc == 8) 428 val = TC358775_VPCTRL_OPXLFMT(1); 429 else /* bpc = 6; */ 430 val = TC358775_VPCTRL_MSF(1); 431 432 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; 433 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); 434 byteclk = dsiclk / 4; 435 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; 436 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000; 437 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / 438 tc->num_dsi_lanes); 439 440 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; 441 442 val |= TC358775_VPCTRL_VSDELAY(vsdelay); 443 d2l_write(tc->i2c, VPCTRL, val); 444 445 d2l_write(tc->i2c, HTIM1, htime1); 446 d2l_write(tc->i2c, VTIM1, vtime1); 447 d2l_write(tc->i2c, HTIM2, htime2); 448 d2l_write(tc->i2c, VTIM2, vtime2); 449 450 d2l_write(tc->i2c, VFUEN, VFUEN_EN); 451 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD); 452 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); 453 454 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", 455 connector->display_info.bus_formats[0], 456 tc->bpc); 457 if (connector->display_info.bus_formats[0] == 458 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) { 459 /* VESA-24 */ 460 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); 461 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); 462 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); 463 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); 464 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); 465 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); 466 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); 467 } else { 468 /* JEIDA-18 and JEIDA-24 */ 469 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5)); 470 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2)); 471 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1)); 472 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2)); 473 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4)); 474 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0)); 475 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0)); 476 } 477 478 d2l_write(tc->i2c, VFUEN, VFUEN_EN); 479 480 val = LVCFG_LVEN_BIT; 481 if (tc->lvds_link == DUAL_LINK) { 482 val |= TC358775_LVCFG_LVDLINK(1); 483 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6); 484 } else { 485 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3); 486 } 487 d2l_write(tc->i2c, LVCFG, val); 488 } 489 490 static enum drm_mode_status tc_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)491 tc_mode_valid(struct drm_bridge *bridge, 492 const struct drm_display_info *info, 493 const struct drm_display_mode *mode) 494 { 495 struct tc_data *tc = bridge_to_tc(bridge); 496 497 /* 498 * Maximum pixel clock speed 135MHz for single-link 499 * 270MHz for dual-link 500 */ 501 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) || 502 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK)) 503 return MODE_CLOCK_HIGH; 504 505 switch (info->bus_formats[0]) { 506 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 507 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 508 /* RGB888 */ 509 tc->bpc = 8; 510 break; 511 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 512 /* RGB666 */ 513 tc->bpc = 6; 514 break; 515 default: 516 dev_warn(tc->dev, 517 "unsupported LVDS bus format 0x%04x\n", 518 info->bus_formats[0]); 519 return MODE_NOMODE; 520 } 521 522 return MODE_OK; 523 } 524 tc358775_parse_dt(struct device_node * np,struct tc_data * tc)525 static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc) 526 { 527 struct device_node *endpoint; 528 struct device_node *parent; 529 struct device_node *remote; 530 int dsi_lanes = -1; 531 532 /* 533 * To get the data-lanes of dsi, we need to access the dsi0_out of port1 534 * of dsi0 endpoint from bridge port0 of d2l_in 535 */ 536 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, 537 TC358775_DSI_IN, -1); 538 if (endpoint) { 539 /* dsi0_out node */ 540 parent = of_graph_get_remote_port_parent(endpoint); 541 of_node_put(endpoint); 542 if (parent) { 543 /* dsi0 port 1 */ 544 dsi_lanes = drm_of_get_data_lanes_count_ep(parent, 1, -1, 1, 4); 545 of_node_put(parent); 546 } 547 } 548 549 if (dsi_lanes < 0) 550 return dsi_lanes; 551 552 tc->num_dsi_lanes = dsi_lanes; 553 554 tc->host_node = of_graph_get_remote_node(np, 0, 0); 555 if (!tc->host_node) 556 return -ENODEV; 557 558 of_node_put(tc->host_node); 559 560 tc->lvds_link = SINGLE_LINK; 561 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, 562 TC358775_LVDS_OUT1, -1); 563 if (endpoint) { 564 remote = of_graph_get_remote_port_parent(endpoint); 565 of_node_put(endpoint); 566 567 if (remote) { 568 if (of_device_is_available(remote)) 569 tc->lvds_link = DUAL_LINK; 570 of_node_put(remote); 571 } 572 } 573 574 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes); 575 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link); 576 577 return 0; 578 } 579 tc_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)580 static int tc_bridge_attach(struct drm_bridge *bridge, 581 enum drm_bridge_attach_flags flags) 582 { 583 struct tc_data *tc = bridge_to_tc(bridge); 584 585 /* Attach the panel-bridge to the dsi bridge */ 586 return drm_bridge_attach(bridge->encoder, tc->panel_bridge, 587 &tc->bridge, flags); 588 } 589 590 static const struct drm_bridge_funcs tc_bridge_funcs = { 591 .attach = tc_bridge_attach, 592 .pre_enable = tc_bridge_pre_enable, 593 .enable = tc_bridge_enable, 594 .mode_valid = tc_mode_valid, 595 .post_disable = tc_bridge_post_disable, 596 }; 597 tc_attach_host(struct tc_data * tc)598 static int tc_attach_host(struct tc_data *tc) 599 { 600 struct device *dev = &tc->i2c->dev; 601 struct mipi_dsi_host *host; 602 struct mipi_dsi_device *dsi; 603 int ret; 604 const struct mipi_dsi_device_info info = { .type = "tc358775", 605 .channel = 0, 606 .node = NULL, 607 }; 608 609 host = of_find_mipi_dsi_host_by_node(tc->host_node); 610 if (!host) 611 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n"); 612 613 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 614 if (IS_ERR(dsi)) { 615 dev_err(dev, "failed to create dsi device\n"); 616 return PTR_ERR(dsi); 617 } 618 619 tc->dsi = dsi; 620 621 dsi->lanes = tc->num_dsi_lanes; 622 dsi->format = MIPI_DSI_FMT_RGB888; 623 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 624 625 ret = devm_mipi_dsi_attach(dev, dsi); 626 if (ret < 0) { 627 dev_err(dev, "failed to attach dsi to host\n"); 628 return ret; 629 } 630 631 return 0; 632 } 633 tc_probe(struct i2c_client * client)634 static int tc_probe(struct i2c_client *client) 635 { 636 struct device *dev = &client->dev; 637 struct tc_data *tc; 638 int ret; 639 640 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 641 if (!tc) 642 return -ENOMEM; 643 644 tc->dev = dev; 645 tc->i2c = client; 646 647 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 648 TC358775_LVDS_OUT0, 0); 649 if (IS_ERR(tc->panel_bridge)) 650 return PTR_ERR(tc->panel_bridge); 651 652 ret = tc358775_parse_dt(dev->of_node, tc); 653 if (ret) 654 return ret; 655 656 tc->vddio = devm_regulator_get(dev, "vddio-supply"); 657 if (IS_ERR(tc->vddio)) { 658 ret = PTR_ERR(tc->vddio); 659 dev_err(dev, "vddio-supply not found\n"); 660 return ret; 661 } 662 663 tc->vdd = devm_regulator_get(dev, "vdd-supply"); 664 if (IS_ERR(tc->vdd)) { 665 ret = PTR_ERR(tc->vdd); 666 dev_err(dev, "vdd-supply not found\n"); 667 return ret; 668 } 669 670 tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH); 671 if (IS_ERR(tc->stby_gpio)) { 672 ret = PTR_ERR(tc->stby_gpio); 673 dev_err(dev, "cannot get stby-gpio %d\n", ret); 674 return ret; 675 } 676 677 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 678 if (IS_ERR(tc->reset_gpio)) { 679 ret = PTR_ERR(tc->reset_gpio); 680 dev_err(dev, "cannot get reset-gpios %d\n", ret); 681 return ret; 682 } 683 684 tc->bridge.funcs = &tc_bridge_funcs; 685 tc->bridge.of_node = dev->of_node; 686 drm_bridge_add(&tc->bridge); 687 688 i2c_set_clientdata(client, tc); 689 690 ret = tc_attach_host(tc); 691 if (ret) 692 goto err_bridge_remove; 693 694 return 0; 695 696 err_bridge_remove: 697 drm_bridge_remove(&tc->bridge); 698 return ret; 699 } 700 tc_remove(struct i2c_client * client)701 static void tc_remove(struct i2c_client *client) 702 { 703 struct tc_data *tc = i2c_get_clientdata(client); 704 705 drm_bridge_remove(&tc->bridge); 706 } 707 708 static const struct i2c_device_id tc358775_i2c_ids[] = { 709 { "tc358775", 0 }, 710 { } 711 }; 712 MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids); 713 714 static const struct of_device_id tc358775_of_ids[] = { 715 { .compatible = "toshiba,tc358775", }, 716 { } 717 }; 718 MODULE_DEVICE_TABLE(of, tc358775_of_ids); 719 720 static struct i2c_driver tc358775_driver = { 721 .driver = { 722 .name = "tc358775", 723 .of_match_table = tc358775_of_ids, 724 }, 725 .id_table = tc358775_i2c_ids, 726 .probe = tc_probe, 727 .remove = tc_remove, 728 }; 729 module_i2c_driver(tc358775_driver); 730 731 MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>"); 732 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver"); 733 MODULE_LICENSE("GPL v2"); 734