xref: /openbmc/u-boot/drivers/ata/sata_sil3114.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
4  * Author: Tor Krill <tor@excito.com>
5  */
6 
7 #ifndef SATA_SIL3114_H
8 #define SATA_SIL3114_H
9 
10 struct sata_ioports {
11 	unsigned long cmd_addr;
12 	unsigned long data_addr;
13 	unsigned long error_addr;
14 	unsigned long feature_addr;
15 	unsigned long nsect_addr;
16 	unsigned long lbal_addr;
17 	unsigned long lbam_addr;
18 	unsigned long lbah_addr;
19 	unsigned long device_addr;
20 	unsigned long status_addr;
21 	unsigned long command_addr;
22 	unsigned long altstatus_addr;
23 	unsigned long ctl_addr;
24 	unsigned long bmdma_addr;
25 	unsigned long scr_addr;
26 };
27 
28 struct sata_port {
29 	unsigned char port_no;	/* primary=0, secondary=1       */
30 	struct sata_ioports ioaddr;	/* ATA cmd/ctl/dma reg blks     */
31 	unsigned char ctl_reg;
32 	unsigned char last_ctl;
33 	unsigned char port_state;	/* 1-port is available and      */
34 	/* 0-port is not available      */
35 	unsigned char dev_mask;
36 };
37 
38 /* Missing ata defines */
39 #define ATA_CMD_STANDBY			0xE2
40 #define ATA_CMD_STANDBYNOW1		0xE0
41 #define ATA_CMD_IDLE			0xE3
42 #define ATA_CMD_IDLEIMMEDIATE	0xE1
43 
44 /* Defines for SIL3114 chip */
45 
46 /* PCI defines */
47 #define SIL_VEND_ID		0x1095
48 #define SIL3114_DEVICE_ID	0x3114
49 
50 /* some vendor specific registers */
51 #define	VND_SYSCONFSTAT	0x88	/* System Configuration Status and Command */
52 #define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
53 #define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
54 #define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
55 #define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
56 
57 /* internal registers mapped by BAR5 */
58 /* SATA Control*/
59 #define VND_SCONTROL_CH0	0x100
60 #define VND_SCONTROL_CH1	0x180
61 #define VND_SCONTROL_CH2	0x300
62 #define VND_SCONTROL_CH3	0x380
63 
64 #define SATA_SC_IPM_T2P		(1<<16)
65 #define SATA_SC_IPM_T2S		(2<<16)
66 #define SATA_SC_SPD_1_5		(1<<4)
67 #define SATA_SC_SPD_3_0		(2<<4)
68 #define SATA_SC_DET_RST		(1)	/* ATA Reset sequence */
69 #define SATA_SC_DET_PDIS	(4)	/* PHY Disable */
70 
71 /* SATA Status */
72 #define VND_SSTATUS_CH0		0x104
73 #define VND_SSTATUS_CH1		0x184
74 #define VND_SSTATUS_CH2		0x304
75 #define VND_SSTATUS_CH3		0x384
76 
77 #define SATA_SS_IPM_ACTIVE	(1<<8)
78 #define SATA_SS_IPM_PARTIAL	(2<<8)
79 #define SATA_SS_IPM_SLUMBER	(6<<8)
80 #define SATA_SS_SPD_1_5		(1<<4)
81 #define SATA_SS_SPD_3_0		(2<<4)
82 #define SATA_DET_P_NOPHY	(1)	/* Device presence but no PHY connection established */
83 #define SATA_DET_PRES		(3)	/* Device presence and active PHY */
84 #define SATA_DET_OFFLINE	(4)	/* Device offline or in loopback mode */
85 
86 /* Task file registers in BAR5 mapping */
87 #define VND_TF0_CH0			0x80
88 #define VND_TF0_CH1			0xc0
89 #define VND_TF0_CH2			0x280
90 #define VND_TF0_CH3			0x2c0
91 #define VND_TF1_CH0			0x88
92 #define VND_TF1_CH1			0xc8
93 #define VND_TF1_CH2			0x288
94 #define VND_TF1_CH3			0x2c8
95 #define VND_TF2_CH0			0x88
96 #define VND_TF2_CH1			0xc8
97 #define VND_TF2_CH2			0x288
98 #define VND_TF2_CH3			0x2c8
99 
100 #define VND_BMDMA_CH0		0x00
101 #define VND_BMDMA_CH1		0x08
102 #define VND_BMDMA_CH2		0x200
103 #define VND_BMDMA_CH3		0x208
104 #define VND_BMDMA2_CH0		0x10
105 #define VND_BMDMA2_CH1		0x18
106 #define VND_BMDMA2_CH2		0x210
107 #define VND_BMDMA2_CH3		0x218
108 
109 /* FIFO control */
110 #define	VND_FIFOCFG_CH0		0x40
111 #define	VND_FIFOCFG_CH1		0x44
112 #define	VND_FIFOCFG_CH2		0x240
113 #define	VND_FIFOCFG_CH3		0x244
114 
115 /* Task File configuration and status */
116 #define VND_TF_CNST_CH0		0xa0
117 #define VND_TF_CNST_CH1		0xe0
118 #define VND_TF_CNST_CH2		0x2a0
119 #define VND_TF_CNST_CH3		0x2e0
120 
121 #define VND_TF_CNST_BFCMD	(1<<1)
122 #define VND_TF_CNST_CHNRST	(1<<2)
123 #define VND_TF_CNST_VDMA	(1<<10)
124 #define VND_TF_CNST_INTST	(1<<11)
125 #define VND_TF_CNST_WDTO	(1<<12)
126 #define VND_TF_CNST_WDEN	(1<<13)
127 #define VND_TF_CNST_WDIEN	(1<<14)
128 
129 /* for testing */
130 #define VND_SSDR			0x04c	/* System Software Data Register */
131 #define VND_FMACS			0x050	/* Flash Memory Address control and status */
132 
133 #endif
134