1 #ifndef QEMU_PCI_DEVICE_H 2 #define QEMU_PCI_DEVICE_H 3 4 #include "hw/pci/pci.h" 5 #include "hw/pci/pcie.h" 6 #include "hw/pci/pcie_doe.h" 7 #include "system/spdm-socket.h" 8 9 #define TYPE_PCI_DEVICE "pci-device" 10 typedef struct PCIDeviceClass PCIDeviceClass; 11 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 12 PCI_DEVICE, TYPE_PCI_DEVICE) 13 14 /* 15 * Implemented by devices that can be plugged on CXL buses. In the spec, this is 16 * actually a "CXL Component, but we name it device to match the PCI naming. 17 */ 18 #define INTERFACE_CXL_DEVICE "cxl-device" 19 20 /* Implemented by devices that can be plugged on PCI Express buses */ 21 #define INTERFACE_PCIE_DEVICE "pci-express-device" 22 23 /* Implemented by devices that can be plugged on Conventional PCI buses */ 24 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 25 26 struct PCIDeviceClass { 27 DeviceClass parent_class; 28 29 void (*realize)(PCIDevice *dev, Error **errp); 30 PCIUnregisterFunc *exit; 31 PCIConfigReadFunc *config_read; 32 PCIConfigWriteFunc *config_write; 33 34 uint16_t vendor_id; 35 uint16_t device_id; 36 uint8_t revision; 37 uint16_t class_id; 38 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 39 uint16_t subsystem_id; /* only for header type = 0 */ 40 41 const char *romfile; /* rom bar */ 42 43 bool sriov_vf_user_creatable; 44 }; 45 46 enum PCIReqIDType { 47 PCI_REQ_ID_INVALID = 0, 48 PCI_REQ_ID_BDF, 49 PCI_REQ_ID_SECONDARY_BUS, 50 PCI_REQ_ID_MAX, 51 }; 52 typedef enum PCIReqIDType PCIReqIDType; 53 54 struct PCIReqIDCache { 55 PCIDevice *dev; 56 PCIReqIDType type; 57 }; 58 typedef struct PCIReqIDCache PCIReqIDCache; 59 60 struct PCIDevice { 61 DeviceState qdev; 62 bool partially_hotplugged; 63 bool enabled; 64 65 /* PCI config space */ 66 uint8_t *config; 67 68 /* 69 * Used to enable config checks on load. Note that writable bits are 70 * never checked even if set in cmask. 71 */ 72 uint8_t *cmask; 73 74 /* Used to implement R/W bytes */ 75 uint8_t *wmask; 76 77 /* Used to implement RW1C(Write 1 to Clear) bytes */ 78 uint8_t *w1cmask; 79 80 /* Used to allocate config space for capabilities. */ 81 uint8_t *used; 82 83 /* the following fields are read only */ 84 int32_t devfn; 85 /* 86 * Cached device to fetch requester ID from, to avoid the PCI tree 87 * walking every time we invoke PCI request (e.g., MSI). For 88 * conventional PCI root complex, this field is meaningless. 89 */ 90 PCIReqIDCache requester_id_cache; 91 char name[64]; 92 PCIIORegion io_regions[PCI_NUM_REGIONS]; 93 AddressSpace bus_master_as; 94 bool is_master; 95 MemoryRegion bus_master_container_region; 96 MemoryRegion bus_master_enable_region; 97 98 /* do not access the following fields */ 99 PCIConfigReadFunc *config_read; 100 PCIConfigWriteFunc *config_write; 101 102 /* Legacy PCI VGA regions */ 103 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 104 bool has_vga; 105 106 /* Current IRQ levels. Used internally by the generic PCI code. */ 107 uint8_t irq_state; 108 109 /* Capability bits */ 110 uint32_t cap_present; 111 112 /* Offset of PM capability in config space */ 113 uint8_t pm_cap; 114 115 /* Offset of MSI-X capability in config space */ 116 uint8_t msix_cap; 117 118 /* MSI-X entries */ 119 int msix_entries_nr; 120 121 /* Space to store MSIX table & pending bit array */ 122 uint8_t *msix_table; 123 uint8_t *msix_pba; 124 125 /* May be used by INTx or MSI during interrupt notification */ 126 void *irq_opaque; 127 128 MSITriggerFunc *msi_trigger; 129 MSIPrepareMessageFunc *msi_prepare_message; 130 MSIxPrepareMessageFunc *msix_prepare_message; 131 132 /* MemoryRegion container for msix exclusive BAR setup */ 133 MemoryRegion msix_exclusive_bar; 134 /* Memory Regions for MSIX table and pending bit entries. */ 135 MemoryRegion msix_table_mmio; 136 MemoryRegion msix_pba_mmio; 137 /* Reference-count for entries actually in use by driver. */ 138 unsigned *msix_entry_used; 139 /* MSIX function mask set or MSIX disabled */ 140 bool msix_function_masked; 141 /* Version id needed for VMState */ 142 int32_t version_id; 143 144 /* Offset of MSI capability in config space */ 145 uint8_t msi_cap; 146 147 /* PCI Express */ 148 PCIExpressDevice exp; 149 150 /* SHPC */ 151 SHPCDevice *shpc; 152 153 /* Location of option rom */ 154 char *romfile; 155 uint32_t romsize; 156 bool has_rom; 157 MemoryRegion rom; 158 int32_t rom_bar; 159 160 /* INTx routing notifier */ 161 PCIINTxRoutingNotifier intx_routing_notifier; 162 163 /* MSI-X notifiers */ 164 MSIVectorUseNotifier msix_vector_use_notifier; 165 MSIVectorReleaseNotifier msix_vector_release_notifier; 166 MSIVectorPollNotifier msix_vector_poll_notifier; 167 168 /* SPDM */ 169 uint16_t spdm_port; 170 SpdmTransportType spdm_trans; 171 172 /* DOE */ 173 DOECap doe_spdm; 174 175 /* ID of standby device in net_failover pair */ 176 char *failover_pair_id; 177 uint32_t acpi_index; 178 179 /* 180 * Indirect DMA region bounce buffer size as configured for the device. This 181 * is a configuration parameter that is reflected into bus_master_as when 182 * realizing the device. 183 */ 184 uint32_t max_bounce_buffer_size; 185 186 char *sriov_pf; 187 }; 188 189 static inline int pci_intx(PCIDevice *pci_dev) 190 { 191 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 192 } 193 194 static inline int pci_is_cxl(const PCIDevice *d) 195 { 196 return d->cap_present & QEMU_PCIE_CAP_CXL; 197 } 198 199 static inline int pci_is_express(const PCIDevice *d) 200 { 201 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 202 } 203 204 static inline int pci_is_express_downstream_port(const PCIDevice *d) 205 { 206 uint8_t type; 207 208 if (!pci_is_express(d) || !d->exp.exp_cap) { 209 return 0; 210 } 211 212 type = pcie_cap_get_type(d); 213 214 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 215 } 216 217 static inline int pci_is_vf(const PCIDevice *d) 218 { 219 return d->sriov_pf || d->exp.sriov_vf.pf != NULL; 220 } 221 222 static inline uint32_t pci_config_size(const PCIDevice *d) 223 { 224 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 225 } 226 227 static inline uint16_t pci_get_bdf(PCIDevice *dev) 228 { 229 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 230 } 231 232 uint16_t pci_requester_id(PCIDevice *dev); 233 234 /* DMA access functions */ 235 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 236 { 237 return &dev->bus_master_as; 238 } 239 240 /** 241 * pci_dma_rw: Read from or write to an address space from PCI device. 242 * 243 * Return a MemTxResult indicating whether the operation succeeded 244 * or failed (eg unassigned memory, device rejected the transaction, 245 * IOMMU fault). 246 * 247 * @dev: #PCIDevice doing the memory access 248 * @addr: address within the #PCIDevice address space 249 * @buf: buffer with the data transferred 250 * @len: the number of bytes to read or write 251 * @dir: indicates the transfer direction 252 */ 253 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 254 void *buf, dma_addr_t len, 255 DMADirection dir, MemTxAttrs attrs) 256 { 257 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, 258 dir, attrs); 259 } 260 261 /** 262 * pci_dma_read: Read from an address space from PCI device. 263 * 264 * Return a MemTxResult indicating whether the operation succeeded 265 * or failed (eg unassigned memory, device rejected the transaction, 266 * IOMMU fault). Called within RCU critical section. 267 * 268 * @dev: #PCIDevice doing the memory access 269 * @addr: address within the #PCIDevice address space 270 * @buf: buffer with the data transferred 271 * @len: length of the data transferred 272 */ 273 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, 274 void *buf, dma_addr_t len) 275 { 276 return pci_dma_rw(dev, addr, buf, len, 277 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 278 } 279 280 /** 281 * pci_dma_write: Write to address space from PCI device. 282 * 283 * Return a MemTxResult indicating whether the operation succeeded 284 * or failed (eg unassigned memory, device rejected the transaction, 285 * IOMMU fault). 286 * 287 * @dev: #PCIDevice doing the memory access 288 * @addr: address within the #PCIDevice address space 289 * @buf: buffer with the data transferred 290 * @len: the number of bytes to write 291 */ 292 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, 293 const void *buf, dma_addr_t len) 294 { 295 return pci_dma_rw(dev, addr, (void *) buf, len, 296 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); 297 } 298 299 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 300 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ 301 dma_addr_t addr, \ 302 uint##_bits##_t *val, \ 303 MemTxAttrs attrs) \ 304 { \ 305 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ 306 } \ 307 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ 308 dma_addr_t addr, \ 309 uint##_bits##_t val, \ 310 MemTxAttrs attrs) \ 311 { \ 312 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ 313 } 314 315 PCI_DMA_DEFINE_LDST(ub, b, 8); 316 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 317 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 318 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 319 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 320 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 321 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 322 323 #undef PCI_DMA_DEFINE_LDST 324 325 /** 326 * pci_dma_map: Map device PCI address space range into host virtual address 327 * @dev: #PCIDevice to be accessed 328 * @addr: address within that device's address space 329 * @plen: pointer to length of buffer; updated on return to indicate 330 * if only a subset of the requested range has been mapped 331 * @dir: indicates the transfer direction 332 * 333 * Return: A host pointer, or %NULL if the resources needed to 334 * perform the mapping are exhausted (in that case *@plen 335 * is set to zero). 336 */ 337 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 338 dma_addr_t *plen, DMADirection dir) 339 { 340 return dma_memory_map(pci_get_address_space(dev), addr, plen, dir, 341 MEMTXATTRS_UNSPECIFIED); 342 } 343 344 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 345 DMADirection dir, dma_addr_t access_len) 346 { 347 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 348 } 349 350 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 351 int alloc_hint) 352 { 353 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 354 } 355 356 extern const VMStateDescription vmstate_pci_device; 357 358 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 359 .name = (stringify(_field)), \ 360 .size = sizeof(PCIDevice), \ 361 .vmsd = &vmstate_pci_device, \ 362 .flags = VMS_STRUCT, \ 363 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 364 } 365 366 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 367 .name = (stringify(_field)), \ 368 .size = sizeof(PCIDevice), \ 369 .vmsd = &vmstate_pci_device, \ 370 .flags = VMS_STRUCT | VMS_POINTER, \ 371 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 372 } 373 374 #endif 375