1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) ASPEED Technology Inc.
4 *
5 */
6
7 #include <malloc.h>
8 #include <asm/io.h>
9 #include <asm/byteorder.h>
10 #include <asm/cache.h>
11 #include <asm/dma-mapping.h>
12 #include <common.h>
13 #include <config.h>
14 #include <dm.h>
15 #include <fdtdec.h>
16 #include <reset.h>
17 #include <linux/usb/ch9.h>
18 #include <linux/usb/gadget.h>
19 #include <linux/usb/otg.h>
20
21 #include "aspeed_udc.h"
22
23 /* number of endpoints on this UDC */
24 #define UDC_MAX_ENDPOINTS 21
25 #define EP_DMA_SIZE 2048
26
27 /* define to use descriptor mode */
28 #define AST_EP_DESC_MODE
29
30 /* could be 32/256 stages */
31 #define AST_EP_NUM_OF_DESC 256
32
33 /*************************************************************************************/
34 #define AST_VHUB_CTRL 0x00
35 #define AST_VHUB_CONF 0x04
36 #define AST_VHUB_IER 0x08
37 #define AST_VHUB_ISR 0x0C
38 #define AST_VHUB_EP_ACK_IER 0x10
39 #define AST_VHUB_EP_NAK_IER 0x14
40 #define AST_VHUB_EP_ACK_ISR 0x18
41 #define AST_VHUB_EP_NAK_ISR 0x1C
42 #define AST_VHUB_DEV_RESET 0x20
43 #define AST_VHUB_USB_STS 0x24
44 #define AST_VHUB_EP_DATA 0x28
45 #define AST_VHUB_ISO_TX_FAIL 0x2C
46 #define AST_VHUB_EP0_CTRL 0x30
47 #define AST_VHUB_EP0_DATA_BUFF 0x34
48 #define AST_VHUB_EP1_CTRL 0x38
49 #define AST_VHUB_EP1_STS_CHG 0x3C
50
51 #define AST_VHUB_SETUP_DATA0 0x80
52 #define AST_VHUB_SETUP_DATA1 0x84
53
54 /* ************************************************************************************/
55 /* AST_VHUB_CTRL 0x00 */
56 #define ROOT_PHY_CLK_EN BIT(31)
57 #define EP_LONG_DESC_MODE BIT(18)
58 #define ROOT_PHY_RESET_DIS BIT(11)
59 #define ROOT_UPSTREAM_EN BIT(0)
60
61 /* AST_VHUB_ISR 0x0C */
62 #define ISR_EP_NAK BIT(17)
63 #define ISR_EP_ACK_STALL BIT(16)
64 #define ISR_DEVICE7 BIT(15)
65 #define ISR_DEVICE6 BIT(14)
66 #define ISR_DEVICE5 BIT(13)
67 #define ISR_DEVICE4 BIT(12)
68 #define ISR_DEVICE3 BIT(11)
69 #define ISR_DEVICE2 BIT(10)
70 #define ISR_DEVICE1 BIT(9)
71 #define ISR_SUSPEND_RESUME BIT(8)
72 #define ISR_BUS_SUSPEND BIT(7)
73 #define ISR_BUS_RESET BIT(6)
74 #define ISR_HUB_EP1_IN_DATA_ACK BIT(5)
75 #define ISR_HUB_EP0_IN_DATA_NAK BIT(4)
76 #define ISR_HUB_EP0_IN_ACK_STALL BIT(3)
77 #define ISR_HUB_EP0_OUT_NAK BIT(2)
78 #define ISR_HUB_EP0_OUT_ACK_STALL BIT(1)
79 #define ISR_HUB_EP0_SETUP BIT(0)
80
81 /* AST_VHUB_USB_STS 0x24 */
82 #define USB_BUS_HIGH_SPEED BIT(27)
83
84 /* AST_VHUB_EP0_CTRL 0x30 */
85 #define EP0_GET_RX_LEN(x) (((x) >> 16) & 0x7f)
86 #define EP0_TX_LEN(x) (((x) & 0x7f) << 8)
87 #define EP0_RX_BUFF_RDY BIT(2)
88 #define EP0_TX_BUFF_RDY BIT(1)
89 #define EP0_STALL BIT(0)
90
91 #define AST_UDC_DEV_CTRL 0x00
92 #define AST_UDC_DEV_ISR 0x04
93 #define AST_UDC_DEV_EP0_CTRL 0x08
94 #define AST_UDC_DEV_EP0_DATA_BUFF 0x0C
95
96 /*************************************************************************************/
97 #define AST_EP_BASE 0x200
98 #define AST_EP_OFFSET 0x10
99 #define AST_EP_CONFIG 0x00
100 #define AST_EP_DMA_CTRL 0x04
101 #define AST_EP_DMA_BUFF 0x08
102 #define AST_EP_DMA_STS 0x0C
103
104 /*************************************************************************************/
105 /* AST_EP_CONFIG 0x00 */
106 #define EP_SET_MAX_PKT(x) (((x) & 0x3ff) << 16)
107 #define EP_SET_EP_STALL BIT(12)
108 #define EP_SET_EP_NUM(x) (((x) & 0xf) << 8)
109 #define EP_TYPE_BULK_IN (0x2 << 4)
110 #define EP_TYPE_BULK_OUT (0x3 << 4)
111 #define EP_TYPE_INT_IN (0x4 << 4)
112 #define EP_TYPE_INT_OUT (0x5 << 4)
113 #define EP_TYPE_ISO_IN (0x6 << 4)
114 #define EP_TYPE_ISO_OUT (0x7 << 4)
115 #define EP_ENABLE BIT(0)
116
117 /* AST_EP_DMA_CTRL 0x04 */
118 #define EP_DMA_IN_LONG_MODE BIT(3)
119 #define EP_RESET_DESC_OP BIT(2)
120 #define EP_SINGLE_DESC_MODE BIT(1)
121 #define EP_DESC_OP_ENABLE BIT(0)
122
123 /* AST_EP_DMA_STS 0x0C */
124 #define AST_EP_TX_DATA_BYTE(x) (((x) & 0x3ff) << 16)
125 #define AST_EP_START_TRANS BIT(0)
126
127 /* Desc W1 IN */
128 #define VHUB_DSC1_IN_INTERRUPT BIT(31)
129 #define VHUB_DSC1_IN_SPID_DATA0 (0 << 14)
130 #define VHUB_DSC1_IN_SPID_DATA2 BIT(14)
131 #define VHUB_DSC1_IN_SPID_DATA1 (2 << 14)
132 #define VHUB_DSC1_IN_SPID_MDATA (3 << 14)
133 #define VHUB_DSC1_IN_SET_LEN(x) ((x) & 0xfff)
134 #define VHUB_DSC1_IN_LEN(x) ((x) & 0xfff)
135 #define VHUB_DSC1_OUT_LEN(x) ((x) & 0x7ff)
136
137 #define AST_SETUP_DEBUG
138 #define AST_UDC_DEBUG
139 #define AST_EP_DEBUG
140
141 #ifdef AST_SETUP_DEBUG
142 #define SETUP_DBG(fmt, args...) pr_debug("%s() " fmt, __func__, ##args)
143 #else
144 #define SETUP_DBG(fmt, args...)
145 #endif
146
147 #ifdef AST_UDC_DEBUG
148 #define UDC_DBG(fmt, args...) pr_debug("%s() " fmt, __func__, ##args)
149 #else
150 #define UDC_DBG(fmt, args...)
151 #endif
152
153 #ifdef AST_EP_DEBUG
154 #define EP_DBG(fmt, args...) pr_debug("%s() " fmt, __func__, ##args)
155 #else
156 #define EP_DBG(fmt, args...)
157 #endif
158
aspeed_udc_done(struct aspeed_udc_ep * ep,struct aspeed_udc_request * req,int status)159 static void aspeed_udc_done(struct aspeed_udc_ep *ep,
160 struct aspeed_udc_request *req, int status)
161 {
162 EP_DBG("%s len: (%d/%d) buf: %p, dir: %s\n",
163 ep->ep.name, req->req.actual, req->req.length, req->req.buf,
164 ep->ep_dir ? "IN" : "OUT");
165
166 list_del(&req->queue);
167
168 if (req->req.status == -EINPROGRESS)
169 req->req.status = status;
170 else
171 status = req->req.status;
172
173 if (status && status != -ESHUTDOWN)
174 EP_DBG("%s done %p, status %d\n", ep->ep.name, req, status);
175
176 usb_gadget_giveback_request(&ep->ep, &req->req);
177 }
178
ast_udc_ep0_data_tx(struct aspeed_udc_priv * udc,u8 * tx_data,u32 len)179 void ast_udc_ep0_data_tx(struct aspeed_udc_priv *udc, u8 *tx_data, u32 len)
180 {
181 u32 reg = udc->udc_base;
182
183 if (len) {
184 memcpy(udc->ep0_ctrl_buf, tx_data, len);
185
186 writel(udc->ep0_ctrl_dma, reg + AST_VHUB_EP0_DATA_BUFF);
187 writel(EP0_TX_LEN(len), reg + AST_VHUB_EP0_CTRL);
188 writel(EP0_TX_LEN(len) | EP0_TX_BUFF_RDY,
189 reg + AST_VHUB_EP0_CTRL);
190
191 udc->is_udc_control_tx = 1;
192
193 } else {
194 writel(EP0_TX_BUFF_RDY, reg + AST_VHUB_EP0_CTRL);
195 }
196 }
197
aspeed_udc_getstatus(struct aspeed_udc_priv * udc)198 static void aspeed_udc_getstatus(struct aspeed_udc_priv *udc)
199 {
200 u32 reg = udc->udc_base;
201 u32 status = 0;
202 int epnum;
203
204 switch (udc->root_setup->bRequestType & USB_RECIP_MASK) {
205 case USB_RECIP_DEVICE:
206 /* Get device status */
207 status = 1 << USB_DEVICE_SELF_POWERED;
208 break;
209 case USB_RECIP_INTERFACE:
210 break;
211 case USB_RECIP_ENDPOINT:
212 epnum = udc->root_setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
213 status = udc->ep[epnum].stopped;
214 break;
215 default:
216 goto stall;
217 }
218
219 EP_DBG("%s: response status: %d\n", __func__, status);
220 ast_udc_ep0_data_tx(udc, (u8 *)&status, sizeof(status));
221
222 return;
223
224 stall:
225 pr_err("Can't respond to %s request\n", __func__);
226 writel(readl(reg + AST_VHUB_EP0_CTRL) | EP0_STALL,
227 reg + AST_VHUB_EP0_CTRL);
228 }
229
aspeed_udc_nuke(struct aspeed_udc_ep * ep,int status)230 static void aspeed_udc_nuke(struct aspeed_udc_ep *ep, int status)
231 {
232 if (!&ep->queue)
233 return;
234
235 while (!list_empty(&ep->queue)) {
236 struct aspeed_udc_request *req;
237
238 req = list_entry(ep->queue.next, struct aspeed_udc_request,
239 queue);
240 aspeed_udc_done(ep, req, status);
241 }
242 }
243
aspeed_udc_setup_handle(struct aspeed_udc_priv * udc)244 static void aspeed_udc_setup_handle(struct aspeed_udc_priv *udc)
245 {
246 u8 bRequestType = udc->root_setup->bRequestType;
247 u8 bRequest = udc->root_setup->bRequest;
248 u16 ep_num = udc->root_setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
249 struct aspeed_udc_request *req;
250 u32 base = udc->udc_base;
251 int i = 0;
252 int ret;
253
254 SETUP_DBG("%s: %x, %s: %x, %s: %x, %s: %x, %s: %d\n",
255 "bRequestType", bRequestType, "bRequest", bRequest,
256 "wValue", udc->root_setup->wValue,
257 "wIndex", udc->root_setup->wIndex,
258 "wLength", udc->root_setup->wLength);
259
260 list_for_each_entry(req, &udc->ep[0].queue, queue) {
261 i++;
262 pr_err("[%d] there is req %x in ep0 queue\n", i, (u32)req);
263 }
264
265 aspeed_udc_nuke(&udc->ep[0], -ETIMEDOUT);
266
267 udc->ep[0].ep_dir = bRequestType & USB_DIR_IN;
268
269 if ((bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
270 switch (bRequest) {
271 case USB_REQ_SET_ADDRESS:
272 SETUP_DBG("Set addr: %x\n", udc->root_setup->wValue);
273
274 if (readl(base + AST_VHUB_USB_STS) &
275 USB_BUS_HIGH_SPEED)
276 udc->gadget.speed = USB_SPEED_HIGH;
277 else
278 udc->gadget.speed = USB_SPEED_FULL;
279
280 writel(udc->root_setup->wValue, base + AST_VHUB_CONF);
281 writel(EP0_TX_BUFF_RDY, base + AST_VHUB_EP0_CTRL);
282 break;
283
284 case USB_REQ_CLEAR_FEATURE:
285 SETUP_DBG("USB_REQ_CLEAR_FEATURE ep: %d\n", ep_num);
286 writel(EP0_TX_BUFF_RDY, base + AST_VHUB_EP0_CTRL);
287 break;
288
289 case USB_REQ_SET_FEATURE:
290 SETUP_DBG("USB_REQ_SET_FEATURE ep: %d\n", ep_num);
291 break;
292
293 case USB_REQ_GET_STATUS:
294 SETUP_DBG("USB_REQ_GET_STATUS\n");
295 aspeed_udc_getstatus(udc);
296 break;
297
298 default:
299 ret = udc->gadget_driver->setup(&udc->gadget,
300 udc->root_setup);
301 if (ret < 0)
302 pr_err("Gadget setup failed, ret: 0x%x\n",
303 ret);
304 break;
305 }
306
307 } else {
308 SETUP_DBG("non-standard request type\n");
309 ret = udc->gadget_driver->setup(&udc->gadget, udc->root_setup);
310 if (ret < 0)
311 pr_err("Gadget setup failed, ret: 0x%x\n", ret);
312 }
313 }
314
aspeed_udc_ep0_queue(struct aspeed_udc_ep * ep,struct aspeed_udc_request * req)315 static void aspeed_udc_ep0_queue(struct aspeed_udc_ep *ep,
316 struct aspeed_udc_request *req)
317 {
318 struct aspeed_udc_priv *udc = ep->udc;
319 u16 tx_len;
320 u32 reg;
321
322 if ((req->req.length - req->req.actual) > ep->ep.maxpacket)
323 tx_len = ep->ep.maxpacket;
324 else
325 tx_len = req->req.length - req->req.actual;
326
327 writel(req->req.dma + req->req.actual,
328 udc->udc_base + AST_VHUB_EP0_DATA_BUFF);
329
330 SETUP_DBG("ep0 REQ buf: %x, dma: %x , txlen: %d (%d/%d) ,dir: %s\n",
331 (u32)req->req.buf, req->req.dma + req->req.actual,
332 tx_len, req->req.actual, req->req.length,
333 ep->ep_dir ? "IN" : "OUT");
334
335 reg = udc->udc_base + AST_VHUB_EP0_CTRL;
336 if (ep->ep_dir) {
337 req->req.actual += tx_len;
338 writel(EP0_TX_LEN(tx_len), reg);
339 writel(EP0_TX_LEN(tx_len) | EP0_TX_BUFF_RDY, reg);
340
341 } else {
342 if (!req->req.length) {
343 writel(EP0_TX_BUFF_RDY, reg);
344 ep->ep_dir = 0x80;
345 } else {
346 writel(EP0_RX_BUFF_RDY, reg);
347 }
348 }
349 }
350
aspeed_udc_ep0_rx(struct aspeed_udc_priv * udc)351 static void aspeed_udc_ep0_rx(struct aspeed_udc_priv *udc)
352 {
353 SETUP_DBG("%s: enter\n", __func__);
354
355 writel(udc->ep0_ctrl_dma, udc->udc_base + AST_VHUB_EP0_DATA_BUFF);
356 writel(EP0_RX_BUFF_RDY, udc->udc_base + AST_VHUB_EP0_CTRL);
357 }
358
aspeed_udc_ep0_tx(struct aspeed_udc_priv * udc)359 static void aspeed_udc_ep0_tx(struct aspeed_udc_priv *udc)
360 {
361 SETUP_DBG("%s: enter\n", __func__);
362
363 writel(udc->ep0_ctrl_dma, udc->udc_base + AST_VHUB_EP0_DATA_BUFF);
364 writel(EP0_TX_BUFF_RDY, udc->udc_base + AST_VHUB_EP0_CTRL);
365 }
366
aspeed_udc_ep0_in(struct aspeed_udc_priv * udc)367 static void aspeed_udc_ep0_in(struct aspeed_udc_priv *udc)
368 {
369 struct aspeed_udc_ep *ep = &udc->ep[0];
370 struct aspeed_udc_request *req;
371
372 if (list_empty(&ep->queue)) {
373 if (udc->is_udc_control_tx) {
374 SETUP_DBG("is_udc_control_tx\n");
375 aspeed_udc_ep0_rx(udc);
376 udc->is_udc_control_tx = 0;
377 }
378 return;
379
380 } else {
381 req = list_entry(ep->queue.next, struct aspeed_udc_request,
382 queue);
383 }
384
385 SETUP_DBG("req=%x (%d/%d)\n", (u32)req, req->req.length,
386 req->req.actual);
387
388 if (req->req.length == req->req.actual) {
389 if (req->req.length)
390 aspeed_udc_ep0_rx(udc);
391
392 if (ep->ep_dir)
393 aspeed_udc_done(ep, req, 0);
394
395 } else {
396 aspeed_udc_ep0_queue(ep, req);
397 }
398 }
399
aspeed_udc_ep0_out(struct aspeed_udc_priv * udc)400 void aspeed_udc_ep0_out(struct aspeed_udc_priv *udc)
401 {
402 struct aspeed_udc_ep *ep = &udc->ep[0];
403 struct aspeed_udc_request *req;
404 u16 rx_len;
405
406 rx_len = EP0_GET_RX_LEN(readl(udc->udc_base + AST_VHUB_EP0_CTRL));
407
408 if (list_empty(&ep->queue))
409 return;
410
411 req = list_entry(ep->queue.next, struct aspeed_udc_request,
412 queue);
413
414 req->req.actual += rx_len;
415
416 SETUP_DBG("req %x (%d/%d)\n", (u32)req, req->req.length,
417 req->req.actual);
418
419 if (rx_len < ep->ep.maxpacket ||
420 req->req.actual == req->req.length) {
421 aspeed_udc_ep0_tx(udc);
422 if (!ep->ep_dir)
423 aspeed_udc_done(ep, req, 0);
424
425 } else {
426 ep->ep_dir = 0;
427 aspeed_udc_ep0_queue(ep, req);
428 }
429 }
430
aspeed_dma_descriptor_setup(struct aspeed_udc_ep * ep,unsigned int dma_address,u32 tx_len,struct aspeed_udc_request * req)431 static int aspeed_dma_descriptor_setup(struct aspeed_udc_ep *ep,
432 unsigned int dma_address, u32 tx_len,
433 struct aspeed_udc_request *req)
434 {
435 u32 packet_len;
436 u32 chunk;
437 int i;
438
439 if (!ep->dma_desc_list) {
440 pr_err("%s: %s %s\n", __func__, ep->ep.name,
441 "failed due to empty DMA descriptor list");
442 return -1;
443 }
444
445 packet_len = tx_len;
446 chunk = ep->chunk_max;
447 i = 0;
448 while (packet_len > 0) {
449 EP_DBG("%s: %s:%d, %s:0x%x, %s:%d %s:%d (%s:0x%x)\n",
450 ep->ep.name,
451 "wptr", ep->dma_desc_list_wptr,
452 "dma_address", dma_address,
453 "packet_len", packet_len,
454 "chunk", chunk,
455 "tx_len", tx_len);
456
457 ep->dma_desc_list[ep->dma_desc_list_wptr].des_0 =
458 (dma_address + (i * chunk));
459
460 /* last packet */
461 if (packet_len <= chunk)
462 ep->dma_desc_list[ep->dma_desc_list_wptr].des_1 =
463 packet_len | VHUB_DSC1_IN_INTERRUPT;
464 else
465 ep->dma_desc_list[ep->dma_desc_list_wptr].des_1 =
466 chunk;
467
468 EP_DBG("wptr:%d, req:%x, dma_desc_list 0x%x 0x%x\n",
469 ep->dma_desc_list_wptr, (u32)req,
470 ep->dma_desc_list[ep->dma_desc_list_wptr].des_0,
471 ep->dma_desc_list[ep->dma_desc_list_wptr].des_1);
472
473 if (i == 0)
474 req->saved_dma_wptr = ep->dma_desc_list_wptr;
475
476 ep->dma_desc_list_wptr++;
477 i++;
478 if (ep->dma_desc_list_wptr >= AST_EP_NUM_OF_DESC)
479 ep->dma_desc_list_wptr = 0;
480 if (packet_len >= chunk)
481 packet_len -= chunk;
482 else
483 break;
484 }
485
486 if (req->req.zero)
487 pr_info("TODO: Send an extra zero length packet\n");
488
489 return 0;
490 }
491
aspeed_udc_ep_dma_desc_mode(struct aspeed_udc_ep * ep,struct aspeed_udc_request * req)492 static void aspeed_udc_ep_dma_desc_mode(struct aspeed_udc_ep *ep,
493 struct aspeed_udc_request *req)
494 {
495 u32 max_req_size;
496 u32 dma_conf;
497 u32 tx_len;
498 int ret;
499
500 max_req_size = ep->chunk_max * (AST_EP_NUM_OF_DESC - 1);
501
502 if ((req->req.length - req->req.actual) > max_req_size)
503 tx_len = max_req_size;
504 else
505 tx_len = req->req.length - req->req.actual;
506
507 EP_DBG("%s: req(0x%x) dma:0x%x, len:0x%x, actual:0x%x, %s:%d, %s:%x\n",
508 ep->ep.name, (u32)req, req->req.dma, req->req.length,
509 req->req.actual, "tx_len", tx_len,
510 "dir", ep->ep_dir);
511
512 if ((req->req.dma % 4) != 0) {
513 pr_err("Not supported=> 1: %s : %x len (%d/%d) dir %x\n",
514 ep->ep.name, req->req.dma, req->req.actual,
515 req->req.length, ep->ep_dir);
516 } else {
517 writel(EP_RESET_DESC_OP, ep->ep_base + AST_EP_DMA_CTRL);
518 ret = aspeed_dma_descriptor_setup(ep, req->req.dma +
519 req->req.actual,
520 tx_len, req);
521 if (!ret)
522 req->actual_dma_length += tx_len;
523
524 writel(ep->dma_desc_dma_handle, ep->ep_base + AST_EP_DMA_BUFF);
525 dma_conf = EP_DESC_OP_ENABLE;
526 if (ep->ep_dir)
527 dma_conf |= EP_DMA_IN_LONG_MODE;
528 writel(dma_conf, ep->ep_base + AST_EP_DMA_CTRL);
529
530 writel(ep->dma_desc_list_wptr,
531 ep->ep_base + AST_EP_DMA_STS);
532 }
533 }
534
aspeed_udc_ep_dma(struct aspeed_udc_ep * ep,struct aspeed_udc_request * req)535 static void aspeed_udc_ep_dma(struct aspeed_udc_ep *ep,
536 struct aspeed_udc_request *req)
537 {
538 u16 tx_len;
539
540 if ((req->req.length - req->req.actual) > ep->ep.maxpacket)
541 tx_len = ep->ep.maxpacket;
542 else
543 tx_len = req->req.length - req->req.actual;
544
545 EP_DBG("req(0x%x) dma: 0x%x, length: 0x%x, actual: 0x%x\n",
546 (u32)req, req->req.dma, req->req.length, req->req.actual);
547
548 EP_DBG("%s: len: %d, dir(0x%x): %s\n",
549 ep->ep.name, tx_len, ep->ep_dir,
550 ep->ep_dir ? "IN" : "OUT");
551
552 writel(req->req.dma + req->req.actual, ep->ep_base + AST_EP_DMA_BUFF);
553 writel(AST_EP_TX_DATA_BYTE(tx_len), ep->ep_base + AST_EP_DMA_STS);
554 writel(AST_EP_TX_DATA_BYTE(tx_len) | AST_EP_START_TRANS,
555 ep->ep_base + AST_EP_DMA_STS);
556 }
557
aspeed_udc_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)558 static int aspeed_udc_ep_enable(struct usb_ep *_ep,
559 const struct usb_endpoint_descriptor *desc)
560 {
561 struct aspeed_udc_ep *ep = container_of(_ep, struct aspeed_udc_ep, ep);
562 u16 nr_trans = ((usb_endpoint_maxp(desc) >> 11) & 3) + 1;
563 u16 maxpacket = usb_endpoint_maxp(desc) & 0x7ff;
564 u8 epnum = usb_endpoint_num(desc);
565 u32 ep_conf = 0;
566 u8 dir_in;
567 u8 type;
568
569 EP_DBG("%s, set ep #%d, maxpacket %d ,wmax %d trans:%d\n", ep->ep.name,
570 epnum, maxpacket, le16_to_cpu(desc->wMaxPacketSize), nr_trans);
571
572 if (!_ep || !ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
573 pr_err("bad ep or descriptor %s %d, %s: %d, %s: %d\n",
574 _ep->name, desc->bDescriptorType,
575 "maxpacket", maxpacket,
576 "ep maxpacket", ep->ep.maxpacket);
577 return -EINVAL;
578 }
579
580 ep->ep.desc = desc;
581 ep->stopped = 0;
582 ep->ep.maxpacket = maxpacket;
583
584 if (maxpacket > 1024) {
585 pr_err("maxpacket is out-of-range: 0x%x\n", maxpacket);
586 maxpacket = 1024;
587 }
588
589 if (maxpacket == 1024)
590 ep_conf = 0;
591 else
592 ep_conf = EP_SET_MAX_PKT(maxpacket);
593
594 ep_conf |= EP_SET_EP_NUM(epnum);
595
596 type = usb_endpoint_type(desc);
597 dir_in = usb_endpoint_dir_in(desc);
598 ep->ep_dir = dir_in;
599
600 ep->chunk_max = ep->ep.maxpacket;
601 if (ep->ep_dir) {
602 ep->chunk_max <<= 3;
603 while (ep->chunk_max > 4095)
604 ep->chunk_max -= ep->ep.maxpacket;
605 }
606
607 EP_DBG("epnum %d, type %d, dir_in %d\n", epnum, type, dir_in);
608 switch (type) {
609 case USB_ENDPOINT_XFER_ISOC:
610 if (dir_in)
611 ep_conf |= EP_TYPE_ISO_IN;
612 else
613 ep_conf |= EP_TYPE_ISO_OUT;
614 break;
615 case USB_ENDPOINT_XFER_BULK:
616 if (dir_in)
617 ep_conf |= EP_TYPE_BULK_IN;
618 else
619 ep_conf |= EP_TYPE_BULK_OUT;
620 break;
621 case USB_ENDPOINT_XFER_INT:
622 if (dir_in)
623 ep_conf |= EP_TYPE_INT_IN;
624 else
625 ep_conf |= EP_TYPE_INT_OUT;
626 break;
627 }
628
629 writel(EP_RESET_DESC_OP, ep->ep_base + AST_EP_DMA_CTRL);
630 writel(EP_SINGLE_DESC_MODE, ep->ep_base + AST_EP_DMA_CTRL);
631 writel(0, ep->ep_base + AST_EP_DMA_STS);
632
633 writel(ep_conf | EP_ENABLE, ep->ep_base + AST_EP_CONFIG);
634
635 EP_DBG("read ep %d seting: 0x%08X\n", epnum,
636 readl(ep->ep_base + AST_EP_CONFIG));
637
638 return 0;
639 }
640
aspeed_udc_ep_disable(struct usb_ep * _ep)641 static int aspeed_udc_ep_disable(struct usb_ep *_ep)
642 {
643 struct aspeed_udc_ep *ep = container_of(_ep, struct aspeed_udc_ep, ep);
644
645 EP_DBG("%s\n", _ep->name);
646
647 ep->ep.desc = NULL;
648 ep->stopped = 1;
649 writel(0, ep->ep_base + AST_EP_CONFIG);
650
651 return 0;
652 }
653
aspeed_udc_ep_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)654 static struct usb_request *aspeed_udc_ep_alloc_request(struct usb_ep *_ep,
655 gfp_t gfp_flags)
656 {
657 struct aspeed_udc_request *req;
658
659 EP_DBG("%s\n", _ep->name);
660 req = kzalloc(sizeof(*req), gfp_flags);
661 if (!req)
662 return NULL;
663
664 INIT_LIST_HEAD(&req->queue);
665 return &req->req;
666 }
667
aspeed_udc_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)668 static void aspeed_udc_ep_free_request(struct usb_ep *_ep,
669 struct usb_request *_req)
670 {
671 struct aspeed_udc_request *req;
672
673 EP_DBG("%s\n", _ep->name);
674 req = container_of(_req, struct aspeed_udc_request, req);
675 kfree(req);
676 }
677
aspeed_udc_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)678 static int aspeed_udc_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
679 gfp_t gfp_flags)
680 {
681 struct aspeed_udc_request *req = req_to_aspeed_udc_req(_req);
682 struct aspeed_udc_ep *ep = ep_to_aspeed_udc_ep(_ep);
683 struct aspeed_udc_priv *udc = ep->udc;
684 unsigned long flags = 0;
685
686 if (unlikely(!_req || !_req->complete || !_req->buf || !_ep))
687 return -EINVAL;
688
689 if (ep->stopped) {
690 pr_err("%s : is stop\n", _ep->name);
691 return -1;
692 }
693
694 spin_lock_irqsave(&udc->lock, flags);
695
696 list_add_tail(&req->queue, &ep->queue);
697
698 req->actual_dma_length = 0;
699 req->req.actual = 0;
700 req->req.status = -EINPROGRESS;
701
702 if (usb_gadget_map_request(&udc->gadget, &req->req, ep->ep_dir)) {
703 pr_err("Map request failed\n");
704 return -1;
705 }
706
707 EP_DBG("%s: req(0x%x) dma:0x%x, len:%d, actual:0x%x\n",
708 ep->name, (u32)req, req->req.dma,
709 req->req.length, req->req.actual);
710
711 if (!ep->ep.desc) { /* ep0 */
712 if ((req->req.dma % 4) != 0) {
713 pr_err("ep0 request dma is not 4 bytes align\n");
714 return -1;
715 }
716 aspeed_udc_ep0_queue(ep, req);
717
718 } else {
719 if (list_is_singular(&ep->queue)) {
720 if (udc->desc_mode)
721 aspeed_udc_ep_dma_desc_mode(ep, req);
722 else
723 aspeed_udc_ep_dma(ep, req);
724 }
725 }
726
727 spin_unlock_irqrestore(&udc->lock, flags);
728
729 return 0;
730 }
731
aspeed_udc_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)732 static int aspeed_udc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
733 {
734 struct aspeed_udc_ep *ep = ep_to_aspeed_udc_ep(_ep);
735 struct aspeed_udc_request *req;
736
737 EP_DBG("%s\n", _ep->name);
738
739 if (!_ep)
740 return -EINVAL;
741
742 list_for_each_entry(req, &ep->queue, queue) {
743 if (&req->req == _req) {
744 list_del_init(&req->queue);
745 _req->status = -ECONNRESET;
746 break;
747 }
748 }
749 if (&req->req != _req) {
750 pr_err("Cannot find REQ in ep queue\n");
751 return -EINVAL;
752 }
753
754 aspeed_udc_done(ep, req, -ESHUTDOWN);
755
756 return 0;
757 }
758
aspeed_udc_ep_set_halt(struct usb_ep * _ep,int value)759 static int aspeed_udc_ep_set_halt(struct usb_ep *_ep, int value)
760 {
761 struct aspeed_udc_ep *ep = ep_to_aspeed_udc_ep(_ep);
762 struct aspeed_udc_priv *udc = ep->udc;
763 u32 reg;
764 u32 val;
765
766 EP_DBG("%s: %d\n", _ep->name, value);
767 if (!_ep)
768 return -EINVAL;
769
770 if (!strncmp(_ep->name, "ep0", 3)) {
771 reg = udc->udc_base + AST_VHUB_EP0_CTRL;
772 if (value)
773 val = readl(reg) | EP0_STALL;
774 else
775 val = readl(reg) & ~EP0_STALL;
776
777 } else {
778 reg = ep->ep_base + AST_EP_CONFIG;
779 if (value)
780 val = readl(reg) | EP_SET_EP_STALL;
781 else
782 val = readl(reg) & ~EP_SET_EP_STALL;
783
784 ep->stopped = value ? 1 : 0;
785 }
786
787 writel(val, reg);
788
789 return 0;
790 }
791
aspeed_udc_ep_handle_desc_mode(struct aspeed_udc_priv * udc,u16 ep_num)792 static void aspeed_udc_ep_handle_desc_mode(struct aspeed_udc_priv *udc,
793 u16 ep_num)
794 {
795 struct aspeed_udc_ep *ep = &udc->ep[ep_num];
796 struct aspeed_udc_request *req;
797 u32 processing_status;
798 u32 wr_ptr, rd_ptr;
799 u16 total_len = 0;
800 u16 len_in_desc;
801 u16 len;
802 int i;
803
804 if (list_empty(&ep->queue)) {
805 pr_err("%s ep req queue is empty!!!\n", ep->ep.name);
806 return;
807 }
808
809 EP_DBG("%s handle\n", ep->ep.name);
810
811 req = list_first_entry(&ep->queue, struct aspeed_udc_request, queue);
812
813 processing_status = (readl(ep->ep_base + AST_EP_DMA_CTRL) >> 4) & 0xf;
814 if (processing_status != 0 && processing_status != 8) {
815 pr_err("Desc process status: 0x%x\n", processing_status);
816 return;
817 }
818
819 rd_ptr = (readl(ep->ep_base + AST_EP_DMA_STS) >> 8) & 0xFF;
820 wr_ptr = (readl(ep->ep_base + AST_EP_DMA_STS)) & 0xFF;
821
822 EP_DBG("req(0x%x) length: 0x%x, actual: 0x%x, rd_ptr:%d, wr_ptr:%d\n",
823 (u32)req, req->req.length, req->req.actual, rd_ptr, wr_ptr);
824
825 if (rd_ptr != wr_ptr) {
826 pr_err("%s: Desc is not empy. %s:%d, %s:%d\n",
827 __func__, "rd_ptr", rd_ptr, "wr_ptr", wr_ptr);
828 return;
829 }
830
831 i = req->saved_dma_wptr;
832 do {
833 if (ep->ep_dir)
834 len_in_desc =
835 VHUB_DSC1_IN_LEN(ep->dma_desc_list[i].des_1);
836 else
837 len_in_desc =
838 VHUB_DSC1_OUT_LEN(ep->dma_desc_list[i].des_1);
839 total_len += len_in_desc;
840 i++;
841 if (i >= AST_EP_NUM_OF_DESC)
842 i = 0;
843 } while (i != wr_ptr);
844
845 len = total_len;
846 req->req.actual += len;
847
848 EP_DBG("%s: total transfer len:0x%x\n", ep->ep.name, len);
849
850 if (req->req.length <= req->req.actual || len < ep->ep.maxpacket) {
851 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->ep_dir);
852 if ((req->req.dma % 4) != 0) {
853 pr_err("Not supported in desc_mode\n");
854 return;
855 }
856
857 aspeed_udc_done(ep, req, 0);
858
859 if (!list_empty(&ep->queue)) {
860 req = list_first_entry(&ep->queue,
861 struct aspeed_udc_request,
862 queue);
863
864 EP_DBG("%s: next req(0x%x) dma 0x%x\n", ep->ep.name,
865 (u32)req, req->req.dma);
866
867 if (req->actual_dma_length == req->req.actual)
868 aspeed_udc_ep_dma_desc_mode(ep, req);
869 else
870 EP_DBG("%s: skip req(0x%x) dma(%d %d)\n",
871 ep->ep.name, (u32)req,
872 req->actual_dma_length,
873 req->req.actual);
874 }
875
876 } else {
877 EP_DBG("%s: not done, keep trigger dma\n", ep->ep.name);
878 if (req->actual_dma_length == req->req.actual)
879 aspeed_udc_ep_dma_desc_mode(ep, req);
880 else
881 EP_DBG("%s: skip req(0x%x) dma (%d %d)\n",
882 ep->ep.name, (u32)req,
883 req->actual_dma_length,
884 req->req.actual);
885 }
886
887 EP_DBG("%s exits\n", ep->ep.name);
888 }
889
aspeed_udc_ep_handle(struct aspeed_udc_priv * udc,u16 ep_num)890 static void aspeed_udc_ep_handle(struct aspeed_udc_priv *udc, u16 ep_num)
891 {
892 struct aspeed_udc_ep *ep = &udc->ep[ep_num];
893 struct aspeed_udc_request *req;
894 u16 len = 0;
895
896 EP_DBG("%s handle\n", ep->ep.name);
897
898 if (list_empty(&ep->queue))
899 return;
900
901 req = list_first_entry(&ep->queue, struct aspeed_udc_request, queue);
902 len = (readl(ep->ep_base + AST_EP_DMA_STS) >> 16) & 0x7ff;
903
904 EP_DBG("%s req: length: 0x%x, actual: 0x%x, len: 0x%x\n",
905 ep->ep.name, req->req.length, req->req.actual, len);
906
907 req->req.actual += len;
908
909 if (req->req.length == req->req.actual || len < ep->ep.maxpacket) {
910 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->ep_dir);
911
912 aspeed_udc_done(ep, req, 0);
913 if (!list_empty(&ep->queue)) {
914 req = list_first_entry(&ep->queue,
915 struct aspeed_udc_request,
916 queue);
917 aspeed_udc_ep_dma(ep, req);
918 }
919
920 } else {
921 aspeed_udc_ep_dma(ep, req);
922 }
923 }
924
aspeed_udc_isr(struct aspeed_udc_priv * udc)925 static void aspeed_udc_isr(struct aspeed_udc_priv *udc)
926 {
927 u32 base = udc->udc_base;
928 u32 isr = readl(base + AST_VHUB_ISR);
929 u32 ep_isr;
930 int i;
931
932 isr &= 0x3ffff;
933 if (!isr)
934 return;
935
936 // pr_info("%s: isr: 0x%x\n", __func__, isr);
937 if (isr & ISR_BUS_RESET) {
938 UDC_DBG("ISR_BUS_RESET\n");
939 writel(ISR_BUS_RESET, base + AST_VHUB_ISR);
940 }
941
942 if (isr & ISR_BUS_SUSPEND) {
943 UDC_DBG("ISR_BUS_SUSPEND\n");
944 writel(ISR_BUS_SUSPEND, base + AST_VHUB_ISR);
945 }
946
947 if (isr & ISR_SUSPEND_RESUME) {
948 UDC_DBG("ISR_SUSPEND_RESUME\n");
949 writel(ISR_SUSPEND_RESUME, base + AST_VHUB_ISR);
950 }
951
952 if (isr & ISR_HUB_EP0_IN_ACK_STALL) {
953 UDC_DBG("ISR_HUB_EP0_IN_ACK_STALL\n");
954 writel(ISR_HUB_EP0_IN_ACK_STALL, base + AST_VHUB_ISR);
955 aspeed_udc_ep0_in(udc);
956 }
957
958 if (isr & ISR_HUB_EP0_OUT_ACK_STALL) {
959 UDC_DBG("ISR_HUB_EP0_OUT_ACK_STALL\n");
960 writel(ISR_HUB_EP0_OUT_ACK_STALL, base + AST_VHUB_ISR);
961 aspeed_udc_ep0_out(udc);
962 }
963
964 if (isr & ISR_HUB_EP0_OUT_NAK) {
965 UDC_DBG("ISR_HUB_EP0_OUT_NAK\n");
966 writel(ISR_HUB_EP0_OUT_NAK, base + AST_VHUB_ISR);
967 }
968
969 if (isr & ISR_HUB_EP0_IN_DATA_NAK) {
970 UDC_DBG("ISR_HUB_EP0_IN_DATA_NAK\n");
971 writel(ISR_HUB_EP0_IN_DATA_NAK, base + AST_VHUB_ISR);
972 }
973
974 if (isr & ISR_HUB_EP0_SETUP) {
975 UDC_DBG("SETUP\n");
976 writel(ISR_HUB_EP0_SETUP, base + AST_VHUB_ISR);
977 aspeed_udc_setup_handle(udc);
978 }
979
980 if (isr & ISR_HUB_EP1_IN_DATA_ACK) {
981 // HUB Bitmap control
982 pr_err("Error: EP1 IN ACK\n");
983 writel(ISR_HUB_EP1_IN_DATA_ACK, base + AST_VHUB_ISR);
984 writel(0x00, base + AST_VHUB_EP1_STS_CHG);
985 }
986
987 if (isr & ISR_EP_ACK_STALL) {
988 ep_isr = readl(base + AST_VHUB_EP_ACK_ISR);
989 UDC_DBG("ISR_EP_ACK_STALL, ep_ack_isr: 0x%x\n", ep_isr);
990
991 for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
992 if (ep_isr & (0x1 << i)) {
993 writel(BIT(i), base + AST_VHUB_EP_ACK_ISR);
994 if (udc->desc_mode)
995 aspeed_udc_ep_handle_desc_mode(udc, i);
996 else
997 aspeed_udc_ep_handle(udc, i);
998 }
999 }
1000 }
1001
1002 if (isr & ISR_EP_NAK) {
1003 UDC_DBG("ISR_EP_NAK\n");
1004 writel(ISR_EP_NAK, base + AST_VHUB_ISR);
1005 }
1006 }
1007
1008 static const struct usb_ep_ops aspeed_udc_ep_ops = {
1009 .enable = aspeed_udc_ep_enable,
1010 .disable = aspeed_udc_ep_disable,
1011 .alloc_request = aspeed_udc_ep_alloc_request,
1012 .free_request = aspeed_udc_ep_free_request,
1013 .queue = aspeed_udc_ep_queue,
1014 .dequeue = aspeed_udc_ep_dequeue,
1015 .set_halt = aspeed_udc_ep_set_halt,
1016 };
1017
aspeed_udc_ep_init(struct aspeed_udc_priv * udc)1018 static void aspeed_udc_ep_init(struct aspeed_udc_priv *udc)
1019 {
1020 struct aspeed_udc_ep *ep;
1021 int i;
1022
1023 for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
1024 ep = &udc->ep[i];
1025 snprintf(ep->name, sizeof(ep->name), "ep%d", i);
1026 ep->ep.name = ep->name;
1027 ep->ep.ops = &aspeed_udc_ep_ops;
1028
1029 if (i) {
1030 ep->ep_buf = udc->ep0_ctrl_buf + (i * EP_DMA_SIZE);
1031 ep->ep_dma = udc->ep0_ctrl_dma + (i * EP_DMA_SIZE);
1032 usb_ep_set_maxpacket_limit(&ep->ep, 1024);
1033 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1034
1035 /* allocate endpoint descrptor list (Note: must be DMA memory) */
1036 if (udc->desc_mode) {
1037 ep->dma_desc_list =
1038 dma_alloc_coherent(AST_EP_NUM_OF_DESC *
1039 sizeof(struct aspeed_ep_desc),
1040 (unsigned long *)
1041 &ep->dma_desc_dma_handle
1042 );
1043 ep->dma_desc_list_wptr = 0;
1044 }
1045
1046 } else {
1047 usb_ep_set_maxpacket_limit(&ep->ep, 64);
1048 }
1049
1050 ep->ep_base = udc->udc_base + AST_EP_BASE + (AST_EP_OFFSET * i);
1051 ep->udc = udc;
1052
1053 INIT_LIST_HEAD(&ep->queue);
1054 }
1055 }
1056
aspeed_gadget_getframe(struct usb_gadget * gadget)1057 static int aspeed_gadget_getframe(struct usb_gadget *gadget)
1058 {
1059 struct aspeed_udc_priv *udc = gadget_to_aspeed_udc(gadget);
1060
1061 return (readl(udc->udc_base + AST_VHUB_USB_STS) >> 16) & 0x7ff;
1062 }
1063
aspeed_gadget_wakeup(struct usb_gadget * gadget)1064 static int aspeed_gadget_wakeup(struct usb_gadget *gadget)
1065 {
1066 UDC_DBG("TODO\n");
1067 return 0;
1068 }
1069
1070 /*
1071 * activate/deactivate link with host; minimize power usage for
1072 * inactive links by cutting clocks and transceiver power.
1073 */
aspeed_gadget_pullup(struct usb_gadget * gadget,int is_on)1074 static int aspeed_gadget_pullup(struct usb_gadget *gadget, int is_on)
1075 {
1076 struct aspeed_udc_priv *udc = gadget_to_aspeed_udc(gadget);
1077 u32 reg = udc->udc_base + AST_VHUB_CTRL;
1078
1079 UDC_DBG("is_on: %d\n", is_on);
1080
1081 if (is_on)
1082 writel(readl(reg) | ROOT_UPSTREAM_EN, reg);
1083 else
1084 writel(readl(reg) & ~ROOT_UPSTREAM_EN, reg);
1085
1086 return 0;
1087 }
1088
aspeed_gadget_start(struct usb_gadget * gadget,struct usb_gadget_driver * driver)1089 static int aspeed_gadget_start(struct usb_gadget *gadget,
1090 struct usb_gadget_driver *driver)
1091 {
1092 struct aspeed_udc_priv *udc = gadget_to_aspeed_udc(gadget);
1093
1094 if (!udc)
1095 return -ENODEV;
1096
1097 udc->gadget_driver = driver;
1098
1099 return 0;
1100 }
1101
aspeed_gadget_stop(struct usb_gadget * gadget)1102 static int aspeed_gadget_stop(struct usb_gadget *gadget)
1103 {
1104 struct aspeed_udc_priv *udc = gadget_to_aspeed_udc(gadget);
1105 u32 reg = udc->udc_base + AST_VHUB_CTRL;
1106
1107 writel(readl(reg) & ~ROOT_UPSTREAM_EN, reg);
1108
1109 udc->gadget.speed = USB_SPEED_UNKNOWN;
1110 udc->gadget_driver = NULL;
1111
1112 usb_gadget_set_state(&udc->gadget, USB_STATE_NOTATTACHED);
1113
1114 return 0;
1115 }
1116
1117 static const struct usb_gadget_ops aspeed_gadget_ops = {
1118 .get_frame = aspeed_gadget_getframe,
1119 .wakeup = aspeed_gadget_wakeup,
1120 .pullup = aspeed_gadget_pullup,
1121 .udc_start = aspeed_gadget_start,
1122 .udc_stop = aspeed_gadget_stop,
1123 };
1124
dm_usb_gadget_handle_interrupts(struct udevice * dev)1125 int dm_usb_gadget_handle_interrupts(struct udevice *dev)
1126 {
1127 struct aspeed_udc_priv *udc = dev_get_priv(dev);
1128
1129 aspeed_udc_isr(udc);
1130
1131 return 0;
1132 }
1133
udc_init(struct aspeed_udc_priv * udc)1134 static int udc_init(struct aspeed_udc_priv *udc)
1135 {
1136 u32 base;
1137
1138 if (!udc) {
1139 dev_err(udc->dev, "Error: udc driver is not init yet");
1140 return -1;
1141 }
1142
1143 base = udc->udc_base;
1144
1145 writel(ROOT_PHY_CLK_EN | ROOT_PHY_RESET_DIS, base + AST_VHUB_CTRL);
1146
1147 writel(0, base + AST_VHUB_DEV_RESET);
1148
1149 writel(~BIT(18), base + AST_VHUB_ISR);
1150 writel(~BIT(18), base + AST_VHUB_IER);
1151
1152 writel(~BIT(UDC_MAX_ENDPOINTS), base + AST_VHUB_EP_ACK_ISR);
1153 writel(~BIT(UDC_MAX_ENDPOINTS), base + AST_VHUB_EP_ACK_IER);
1154
1155 writel(0, base + AST_VHUB_EP0_CTRL);
1156 writel(0, base + AST_VHUB_EP1_CTRL);
1157
1158 #ifdef AST_EP_DESC_MODE
1159 if (AST_EP_NUM_OF_DESC == 256)
1160 writel(readl(base + AST_VHUB_CTRL) | EP_LONG_DESC_MODE,
1161 base + AST_VHUB_CTRL);
1162 #endif
1163
1164 return 0;
1165 }
1166
aspeed_udc_probe(struct udevice * dev)1167 static int aspeed_udc_probe(struct udevice *dev)
1168 {
1169 struct aspeed_udc_priv *udc = dev_get_priv(dev);
1170 struct reset_ctl udc_reset_ctl;
1171 int ret;
1172
1173 dev_info(dev, "Start aspeed udc...\n");
1174
1175 ret = reset_get_by_index(dev, 0, &udc_reset_ctl);
1176 if (ret) {
1177 dev_err(dev, "%s: Failed to get udc reset signal\n", __func__);
1178 return ret;
1179 }
1180
1181 reset_assert(&udc_reset_ctl);
1182
1183 // Wait 10ms for PLL locking
1184 mdelay(10);
1185 reset_deassert(&udc_reset_ctl);
1186
1187 udc->init = 1;
1188 ret = udc_init(udc);
1189 if (ret) {
1190 dev_err(dev, "%s: udc_init failed\n", __func__);
1191 return -EINVAL;
1192 }
1193
1194 udc->gadget.ops = &aspeed_gadget_ops;
1195 udc->gadget.ep0 = &udc->ep[0].ep;
1196 udc->gadget.max_speed = udc->maximum_speed;
1197 udc->gadget.speed = USB_SPEED_UNKNOWN;
1198 udc->root_setup = (struct usb_ctrlrequest *)
1199 (udc->udc_base + AST_VHUB_SETUP_DATA0);
1200 #ifdef AST_EP_DESC_MODE
1201 udc->desc_mode = 1;
1202 #else
1203 udc->desc_mode = 0;
1204 #endif
1205 pr_info("%s: desc_mode: %d\n", __func__, udc->desc_mode);
1206
1207 /*
1208 * Allocate DMA buffers for all EP0s in one chunk,
1209 * one per port and one for the vHub itself
1210 */
1211 udc->ep0_ctrl_buf =
1212 dma_alloc_coherent(EP_DMA_SIZE * UDC_MAX_ENDPOINTS,
1213 (unsigned long *)&udc->ep0_ctrl_dma);
1214
1215 INIT_LIST_HEAD(&udc->gadget.ep_list);
1216
1217 aspeed_udc_ep_init(udc);
1218
1219 ret = usb_add_gadget_udc((struct device *)udc->dev, &udc->gadget);
1220 if (ret) {
1221 dev_err(udc->dev, "failed to register udc\n");
1222 return ret;
1223 }
1224
1225 return 0;
1226 }
1227
aspeed_udc_ofdata_to_platdata(struct udevice * dev)1228 static int aspeed_udc_ofdata_to_platdata(struct udevice *dev)
1229 {
1230 struct aspeed_udc_priv *udc = dev_get_priv(dev);
1231 int node = dev_of_offset(dev);
1232
1233 udc->udc_base = (u32)devfdt_get_addr_index(dev, 0);
1234 udc->dev = dev;
1235
1236 udc->maximum_speed = usb_get_maximum_speed(node);
1237 if (udc->maximum_speed == USB_SPEED_UNKNOWN) {
1238 printf("Invalid usb maximum speed\n");
1239 return -ENODEV;
1240 }
1241
1242 return 0;
1243 }
1244
aspeed_udc_remove(struct udevice * dev)1245 static int aspeed_udc_remove(struct udevice *dev)
1246 {
1247 struct aspeed_udc_priv *udc = dev_get_priv(dev);
1248
1249 usb_del_gadget_udc(&udc->gadget);
1250 if (udc->gadget_driver)
1251 return -EBUSY;
1252
1253 writel(readl(udc->udc_base + AST_VHUB_CTRL) & ~ROOT_UPSTREAM_EN,
1254 udc->udc_base + AST_VHUB_CTRL);
1255
1256 dma_free_coherent(udc->ep0_ctrl_buf);
1257
1258 return 0;
1259 }
1260
1261 static const struct udevice_id aspeed_udc_ids[] = {
1262 { .compatible = "aspeed,ast2600-usb-vhub" },
1263 { }
1264 };
1265
1266 U_BOOT_DRIVER(aspeed_udc_generic) = {
1267 .name = "aspeed_udc_generic",
1268 .id = UCLASS_USB_GADGET_GENERIC,
1269 .of_match = aspeed_udc_ids,
1270 .probe = aspeed_udc_probe,
1271 .remove = aspeed_udc_remove,
1272 .ofdata_to_platdata = aspeed_udc_ofdata_to_platdata,
1273 .priv_auto_alloc_size = sizeof(struct aspeed_udc_priv),
1274 };
1275