1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/reset.c
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #include <linux/errno.h>
12 #include <linux/kernel.h>
13 #include <linux/kvm_host.h>
14 #include <linux/kvm.h>
15 #include <linux/hw_breakpoint.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/types.h>
19
20 #include <kvm/arm_arch_timer.h>
21
22 #include <asm/cpufeature.h>
23 #include <asm/cputype.h>
24 #include <asm/fpsimd.h>
25 #include <asm/ptrace.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_asm.h>
28 #include <asm/kvm_emulate.h>
29 #include <asm/kvm_mmu.h>
30 #include <asm/kvm_nested.h>
31 #include <asm/virt.h>
32
33 /* Maximum phys_shift supported for any VM on this host */
34 static u32 __ro_after_init kvm_ipa_limit;
35
36 /*
37 * ARMv8 Reset Values
38 */
39 #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
40 PSR_F_BIT | PSR_D_BIT)
41
42 #define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \
43 PSR_F_BIT | PSR_D_BIT)
44
45 #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \
46 PSR_AA32_I_BIT | PSR_AA32_F_BIT)
47
48 unsigned int __ro_after_init kvm_sve_max_vl;
49 unsigned int __ro_after_init kvm_host_sve_max_vl;
50
kvm_arm_init_sve(void)51 int __init kvm_arm_init_sve(void)
52 {
53 if (system_supports_sve()) {
54 kvm_sve_max_vl = sve_max_virtualisable_vl();
55 kvm_host_sve_max_vl = sve_max_vl();
56 kvm_nvhe_sym(kvm_host_sve_max_vl) = kvm_host_sve_max_vl;
57
58 /*
59 * The get_sve_reg()/set_sve_reg() ioctl interface will need
60 * to be extended with multiple register slice support in
61 * order to support vector lengths greater than
62 * VL_ARCH_MAX:
63 */
64 if (WARN_ON(kvm_sve_max_vl > VL_ARCH_MAX))
65 kvm_sve_max_vl = VL_ARCH_MAX;
66
67 /*
68 * Don't even try to make use of vector lengths that
69 * aren't available on all CPUs, for now:
70 */
71 if (kvm_sve_max_vl < sve_max_vl())
72 pr_warn("KVM: SVE vector length for guests limited to %u bytes\n",
73 kvm_sve_max_vl);
74 }
75
76 return 0;
77 }
78
kvm_vcpu_enable_sve(struct kvm_vcpu * vcpu)79 static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
80 {
81 if (!system_supports_sve())
82 return -EINVAL;
83
84 vcpu->arch.sve_max_vl = kvm_sve_max_vl;
85
86 /*
87 * Userspace can still customize the vector lengths by writing
88 * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until
89 * kvm_arm_vcpu_finalize(), which freezes the configuration.
90 */
91 vcpu_set_flag(vcpu, GUEST_HAS_SVE);
92
93 return 0;
94 }
95
96 /*
97 * Finalize vcpu's maximum SVE vector length, allocating
98 * vcpu->arch.sve_state as necessary.
99 */
kvm_vcpu_finalize_sve(struct kvm_vcpu * vcpu)100 static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu)
101 {
102 void *buf;
103 unsigned int vl;
104 size_t reg_sz;
105 int ret;
106
107 vl = vcpu->arch.sve_max_vl;
108
109 /*
110 * Responsibility for these properties is shared between
111 * kvm_arm_init_sve(), kvm_vcpu_enable_sve() and
112 * set_sve_vls(). Double-check here just to be sure:
113 */
114 if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() ||
115 vl > VL_ARCH_MAX))
116 return -EIO;
117
118 reg_sz = vcpu_sve_state_size(vcpu);
119 buf = kzalloc(reg_sz, GFP_KERNEL_ACCOUNT);
120 if (!buf)
121 return -ENOMEM;
122
123 ret = kvm_share_hyp(buf, buf + reg_sz);
124 if (ret) {
125 kfree(buf);
126 return ret;
127 }
128
129 vcpu->arch.sve_state = buf;
130 vcpu_set_flag(vcpu, VCPU_SVE_FINALIZED);
131 return 0;
132 }
133
kvm_arm_vcpu_finalize(struct kvm_vcpu * vcpu,int feature)134 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
135 {
136 switch (feature) {
137 case KVM_ARM_VCPU_SVE:
138 if (!vcpu_has_sve(vcpu))
139 return -EINVAL;
140
141 if (kvm_arm_vcpu_sve_finalized(vcpu))
142 return -EPERM;
143
144 return kvm_vcpu_finalize_sve(vcpu);
145 }
146
147 return -EINVAL;
148 }
149
kvm_arm_vcpu_is_finalized(struct kvm_vcpu * vcpu)150 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
151 {
152 if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu))
153 return false;
154
155 return true;
156 }
157
kvm_arm_vcpu_destroy(struct kvm_vcpu * vcpu)158 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu)
159 {
160 void *sve_state = vcpu->arch.sve_state;
161
162 kvm_vcpu_unshare_task_fp(vcpu);
163 kvm_unshare_hyp(vcpu, vcpu + 1);
164 if (sve_state)
165 kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu));
166 kfree(sve_state);
167 kfree(vcpu->arch.ccsidr);
168 }
169
kvm_vcpu_reset_sve(struct kvm_vcpu * vcpu)170 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu)
171 {
172 if (vcpu_has_sve(vcpu))
173 memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu));
174 }
175
kvm_vcpu_enable_ptrauth(struct kvm_vcpu * vcpu)176 static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu)
177 {
178 /*
179 * For now make sure that both address/generic pointer authentication
180 * features are requested by the userspace together and the system
181 * supports these capabilities.
182 */
183 if (!test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
184 !test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features) ||
185 !system_has_full_ptr_auth())
186 return -EINVAL;
187
188 vcpu_set_flag(vcpu, GUEST_HAS_PTRAUTH);
189 return 0;
190 }
191
192 /**
193 * kvm_reset_vcpu - sets core registers and sys_regs to reset value
194 * @vcpu: The VCPU pointer
195 *
196 * This function sets the registers on the virtual CPU struct to their
197 * architecturally defined reset values, except for registers whose reset is
198 * deferred until kvm_arm_vcpu_finalize().
199 *
200 * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
201 * ioctl or as part of handling a request issued by another VCPU in the PSCI
202 * handling code. In the first case, the VCPU will not be loaded, and in the
203 * second case the VCPU will be loaded. Because this function operates purely
204 * on the memory-backed values of system registers, we want to do a full put if
205 * we were loaded (handling a request) and load the values back at the end of
206 * the function. Otherwise we leave the state alone. In both cases, we
207 * disable preemption around the vcpu reset as we would otherwise race with
208 * preempt notifiers which also call put/load.
209 */
kvm_reset_vcpu(struct kvm_vcpu * vcpu)210 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
211 {
212 struct vcpu_reset_state reset_state;
213 int ret;
214 bool loaded;
215 u32 pstate;
216
217 spin_lock(&vcpu->arch.mp_state_lock);
218 reset_state = vcpu->arch.reset_state;
219 vcpu->arch.reset_state.reset = false;
220 spin_unlock(&vcpu->arch.mp_state_lock);
221
222 /* Reset PMU outside of the non-preemptible section */
223 kvm_pmu_vcpu_reset(vcpu);
224
225 preempt_disable();
226 loaded = (vcpu->cpu != -1);
227 if (loaded)
228 kvm_arch_vcpu_put(vcpu);
229
230 /* Disallow NV+SVE for the time being */
231 if (vcpu_has_nv(vcpu) && vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) {
232 ret = -EINVAL;
233 goto out;
234 }
235
236 if (!kvm_arm_vcpu_sve_finalized(vcpu)) {
237 if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) {
238 ret = kvm_vcpu_enable_sve(vcpu);
239 if (ret)
240 goto out;
241 }
242 } else {
243 kvm_vcpu_reset_sve(vcpu);
244 }
245
246 if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
247 test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) {
248 if (kvm_vcpu_enable_ptrauth(vcpu)) {
249 ret = -EINVAL;
250 goto out;
251 }
252 }
253
254 if (vcpu_el1_is_32bit(vcpu))
255 pstate = VCPU_RESET_PSTATE_SVC;
256 else if (vcpu_has_nv(vcpu))
257 pstate = VCPU_RESET_PSTATE_EL2;
258 else
259 pstate = VCPU_RESET_PSTATE_EL1;
260
261 if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) {
262 ret = -EINVAL;
263 goto out;
264 }
265
266 /* Reset core registers */
267 memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu)));
268 memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs));
269 vcpu->arch.ctxt.spsr_abt = 0;
270 vcpu->arch.ctxt.spsr_und = 0;
271 vcpu->arch.ctxt.spsr_irq = 0;
272 vcpu->arch.ctxt.spsr_fiq = 0;
273 vcpu_gp_regs(vcpu)->pstate = pstate;
274
275 /* Reset system registers */
276 kvm_reset_sys_regs(vcpu);
277
278 /*
279 * Additional reset state handling that PSCI may have imposed on us.
280 * Must be done after all the sys_reg reset.
281 */
282 if (reset_state.reset) {
283 unsigned long target_pc = reset_state.pc;
284
285 /* Gracefully handle Thumb2 entry point */
286 if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
287 target_pc &= ~1UL;
288 vcpu_set_thumb(vcpu);
289 }
290
291 /* Propagate caller endianness */
292 if (reset_state.be)
293 kvm_vcpu_set_be(vcpu);
294
295 *vcpu_pc(vcpu) = target_pc;
296 vcpu_set_reg(vcpu, 0, reset_state.r0);
297 }
298
299 /* Reset timer */
300 ret = kvm_timer_vcpu_reset(vcpu);
301 out:
302 if (loaded)
303 kvm_arch_vcpu_load(vcpu, smp_processor_id());
304 preempt_enable();
305 return ret;
306 }
307
get_kvm_ipa_limit(void)308 u32 get_kvm_ipa_limit(void)
309 {
310 return kvm_ipa_limit;
311 }
312
kvm_set_ipa_limit(void)313 int __init kvm_set_ipa_limit(void)
314 {
315 unsigned int parange;
316 u64 mmfr0;
317
318 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
319 parange = cpuid_feature_extract_unsigned_field(mmfr0,
320 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
321 /*
322 * IPA size beyond 48 bits could not be supported
323 * on either 4K or 16K page size. Hence let's cap
324 * it to 48 bits, in case it's reported as larger
325 * on the system.
326 */
327 if (PAGE_SIZE != SZ_64K)
328 parange = min(parange, (unsigned int)ID_AA64MMFR0_EL1_PARANGE_48);
329
330 /*
331 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
332 * Stage-2. If not, things will stop very quickly.
333 */
334 switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_TGRAN_2_SHIFT)) {
335 case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE:
336 kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
337 return -EINVAL;
338 case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT:
339 kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
340 break;
341 case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX:
342 kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
343 break;
344 default:
345 kvm_err("Unsupported value for TGRAN_2, giving up\n");
346 return -EINVAL;
347 }
348
349 kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange);
350 kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit,
351 ((kvm_ipa_limit < KVM_PHYS_SHIFT) ?
352 " (Reduced IPA size, limited VM/VMM compatibility)" : ""));
353
354 return 0;
355 }
356