xref: /openbmc/linux/drivers/gpu/drm/vc4/vc4_packet.h (revision d5b1a78a)
1 /*
2  * Copyright © 2014 Broadcom
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #ifndef VC4_PACKET_H
25 #define VC4_PACKET_H
26 
27 #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */
28 
29 enum vc4_packet {
30 	VC4_PACKET_HALT = 0,
31 	VC4_PACKET_NOP = 1,
32 
33 	VC4_PACKET_FLUSH = 4,
34 	VC4_PACKET_FLUSH_ALL = 5,
35 	VC4_PACKET_START_TILE_BINNING = 6,
36 	VC4_PACKET_INCREMENT_SEMAPHORE = 7,
37 	VC4_PACKET_WAIT_ON_SEMAPHORE = 8,
38 
39 	VC4_PACKET_BRANCH = 16,
40 	VC4_PACKET_BRANCH_TO_SUB_LIST = 17,
41 
42 	VC4_PACKET_STORE_MS_TILE_BUFFER = 24,
43 	VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25,
44 	VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26,
45 	VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27,
46 	VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28,
47 	VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29,
48 
49 	VC4_PACKET_GL_INDEXED_PRIMITIVE = 32,
50 	VC4_PACKET_GL_ARRAY_PRIMITIVE = 33,
51 
52 	VC4_PACKET_COMPRESSED_PRIMITIVE = 48,
53 	VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49,
54 
55 	VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56,
56 
57 	VC4_PACKET_GL_SHADER_STATE = 64,
58 	VC4_PACKET_NV_SHADER_STATE = 65,
59 	VC4_PACKET_VG_SHADER_STATE = 66,
60 
61 	VC4_PACKET_CONFIGURATION_BITS = 96,
62 	VC4_PACKET_FLAT_SHADE_FLAGS = 97,
63 	VC4_PACKET_POINT_SIZE = 98,
64 	VC4_PACKET_LINE_WIDTH = 99,
65 	VC4_PACKET_RHT_X_BOUNDARY = 100,
66 	VC4_PACKET_DEPTH_OFFSET = 101,
67 	VC4_PACKET_CLIP_WINDOW = 102,
68 	VC4_PACKET_VIEWPORT_OFFSET = 103,
69 	VC4_PACKET_Z_CLIPPING = 104,
70 	VC4_PACKET_CLIPPER_XY_SCALING = 105,
71 	VC4_PACKET_CLIPPER_Z_SCALING = 106,
72 
73 	VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112,
74 	VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113,
75 	VC4_PACKET_CLEAR_COLORS = 114,
76 	VC4_PACKET_TILE_COORDINATES = 115,
77 
78 	/* Not an actual hardware packet -- this is what we use to put
79 	 * references to GEM bos in the command stream, since we need the u32
80 	 * int the actual address packet in order to store the offset from the
81 	 * start of the BO.
82 	 */
83 	VC4_PACKET_GEM_HANDLES = 254,
84 } __attribute__ ((__packed__));
85 
86 #define VC4_PACKET_HALT_SIZE						1
87 #define VC4_PACKET_NOP_SIZE						1
88 #define VC4_PACKET_FLUSH_SIZE						1
89 #define VC4_PACKET_FLUSH_ALL_SIZE					1
90 #define VC4_PACKET_START_TILE_BINNING_SIZE				1
91 #define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE				1
92 #define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE				1
93 #define VC4_PACKET_BRANCH_SIZE						5
94 #define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE				5
95 #define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE				1
96 #define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE			1
97 #define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE			5
98 #define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE			5
99 #define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE			7
100 #define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE			7
101 #define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE				14
102 #define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE				10
103 #define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE				1
104 #define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE			1
105 #define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE				2
106 #define VC4_PACKET_GL_SHADER_STATE_SIZE					5
107 #define VC4_PACKET_NV_SHADER_STATE_SIZE					5
108 #define VC4_PACKET_VG_SHADER_STATE_SIZE					5
109 #define VC4_PACKET_CONFIGURATION_BITS_SIZE				4
110 #define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE				5
111 #define VC4_PACKET_POINT_SIZE_SIZE					5
112 #define VC4_PACKET_LINE_WIDTH_SIZE					5
113 #define VC4_PACKET_RHT_X_BOUNDARY_SIZE					3
114 #define VC4_PACKET_DEPTH_OFFSET_SIZE					5
115 #define VC4_PACKET_CLIP_WINDOW_SIZE					9
116 #define VC4_PACKET_VIEWPORT_OFFSET_SIZE					5
117 #define VC4_PACKET_Z_CLIPPING_SIZE					9
118 #define VC4_PACKET_CLIPPER_XY_SCALING_SIZE				9
119 #define VC4_PACKET_CLIPPER_Z_SCALING_SIZE				9
120 #define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE			16
121 #define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE			11
122 #define VC4_PACKET_CLEAR_COLORS_SIZE					14
123 #define VC4_PACKET_TILE_COORDINATES_SIZE				3
124 #define VC4_PACKET_GEM_HANDLES_SIZE					9
125 
126 /* Number of multisamples supported. */
127 #define VC4_MAX_SAMPLES							4
128 /* Size of a full resolution color or Z tile buffer load/store. */
129 #define VC4_TILE_BUFFER_SIZE			(64 * 64 * 4)
130 
131 /** @{
132  * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
133  * VC4_PACKET_TILE_RENDERING_MODE_CONFIG.
134 */
135 #define VC4_TILING_FORMAT_LINEAR    0
136 #define VC4_TILING_FORMAT_T         1
137 #define VC4_TILING_FORMAT_LT        2
138 /** @} */
139 
140 /** @{
141  *
142  * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and
143  * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.
144  */
145 #define VC4_LOADSTORE_FULL_RES_EOF                     BIT(3)
146 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL       BIT(2)
147 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS              BIT(1)
148 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR           BIT(0)
149 
150 /** @{
151  *
152  * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and
153  * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.
154  */
155 #define VC4_LOADSTORE_FULL_RES_EOF                     BIT(3)
156 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL       BIT(2)
157 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS              BIT(1)
158 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR           BIT(0)
159 
160 /** @{
161  *
162  * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
163  * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address)
164  */
165 
166 #define VC4_LOADSTORE_TILE_BUFFER_EOF                  BIT(3)
167 #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK BIT(2)
168 #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS      BIT(1)
169 #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR   BIT(0)
170 
171 /** @} */
172 
173 /** @{
174  *
175  * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
176  * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
177  */
178 #define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR BIT(15)
179 #define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     BIT(14)
180 #define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  BIT(13)
181 #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         BIT(12)
182 
183 #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK      VC4_MASK(9, 8)
184 #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT     8
185 #define VC4_LOADSTORE_TILE_BUFFER_RGBA8888         0
186 #define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER    1
187 #define VC4_LOADSTORE_TILE_BUFFER_BGR565           2
188 /** @} */
189 
190 /** @{
191  *
192  * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
193  * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
194  */
195 #define VC4_STORE_TILE_BUFFER_MODE_MASK            VC4_MASK(7, 6)
196 #define VC4_STORE_TILE_BUFFER_MODE_SHIFT           6
197 #define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0         (0 << 6)
198 #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4     (1 << 6)
199 #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16    (2 << 6)
200 
201 /** The values of the field are VC4_TILING_FORMAT_* */
202 #define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK      VC4_MASK(5, 4)
203 #define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT     4
204 
205 #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK      VC4_MASK(2, 0)
206 #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT     0
207 #define VC4_LOADSTORE_TILE_BUFFER_NONE             0
208 #define VC4_LOADSTORE_TILE_BUFFER_COLOR            1
209 #define VC4_LOADSTORE_TILE_BUFFER_ZS               2
210 #define VC4_LOADSTORE_TILE_BUFFER_Z                3
211 #define VC4_LOADSTORE_TILE_BUFFER_VG_MASK          4
212 #define VC4_LOADSTORE_TILE_BUFFER_FULL             5
213 /** @} */
214 
215 #define VC4_INDEX_BUFFER_U8                        (0 << 4)
216 #define VC4_INDEX_BUFFER_U16                       (1 << 4)
217 
218 /* This flag is only present in NV shader state. */
219 #define VC4_SHADER_FLAG_SHADED_CLIP_COORDS         BIT(3)
220 #define VC4_SHADER_FLAG_ENABLE_CLIPPING            BIT(2)
221 #define VC4_SHADER_FLAG_VS_POINT_SIZE              BIT(1)
222 #define VC4_SHADER_FLAG_FS_SINGLE_THREAD           BIT(0)
223 
224 /** @{ byte 2 of config bits. */
225 #define VC4_CONFIG_BITS_EARLY_Z_UPDATE             BIT(1)
226 #define VC4_CONFIG_BITS_EARLY_Z                    BIT(0)
227 /** @} */
228 
229 /** @{ byte 1 of config bits. */
230 #define VC4_CONFIG_BITS_Z_UPDATE                   BIT(7)
231 /** same values in this 3-bit field as PIPE_FUNC_* */
232 #define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT           4
233 #define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE        BIT(3)
234 
235 #define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO    (0 << 1)
236 #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD        (1 << 1)
237 #define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR         (2 << 1)
238 #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO       (3 << 1)
239 
240 #define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT       BIT(0)
241 /** @} */
242 
243 /** @{ byte 0 of config bits. */
244 #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6)
245 #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X   (1 << 6)
246 #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X  (2 << 6)
247 
248 #define VC4_CONFIG_BITS_AA_POINTS_AND_LINES        BIT(4)
249 #define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET        BIT(3)
250 #define VC4_CONFIG_BITS_CW_PRIMITIVES              BIT(2)
251 #define VC4_CONFIG_BITS_ENABLE_PRIM_BACK           BIT(1)
252 #define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT          BIT(0)
253 /** @} */
254 
255 /** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */
256 #define VC4_BIN_CONFIG_DB_NON_MS                   BIT(7)
257 
258 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK       VC4_MASK(6, 5)
259 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT      5
260 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32         0
261 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64         1
262 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128        2
263 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256        3
264 
265 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK  VC4_MASK(4, 3)
266 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3
267 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32    0
268 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64    1
269 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128   2
270 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256   3
271 
272 #define VC4_BIN_CONFIG_AUTO_INIT_TSDA              BIT(2)
273 #define VC4_BIN_CONFIG_TILE_BUFFER_64BIT           BIT(1)
274 #define VC4_BIN_CONFIG_MS_MODE_4X                  BIT(0)
275 /** @} */
276 
277 /** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */
278 #define VC4_RENDER_CONFIG_DB_NON_MS                BIT(12)
279 #define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE BIT(11)
280 #define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G      BIT(10)
281 #define VC4_RENDER_CONFIG_COVERAGE_MODE            BIT(9)
282 #define VC4_RENDER_CONFIG_ENABLE_VG_MASK           BIT(8)
283 
284 /** The values of the field are VC4_TILING_FORMAT_* */
285 #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK       VC4_MASK(7, 6)
286 #define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT      6
287 
288 #define VC4_RENDER_CONFIG_DECIMATE_MODE_1X         (0 << 4)
289 #define VC4_RENDER_CONFIG_DECIMATE_MODE_4X         (1 << 4)
290 #define VC4_RENDER_CONFIG_DECIMATE_MODE_16X        (2 << 4)
291 
292 #define VC4_RENDER_CONFIG_FORMAT_MASK              VC4_MASK(3, 2)
293 #define VC4_RENDER_CONFIG_FORMAT_SHIFT             2
294 #define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED   0
295 #define VC4_RENDER_CONFIG_FORMAT_RGBA8888          1
296 #define VC4_RENDER_CONFIG_FORMAT_BGR565            2
297 
298 #define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT        BIT(1)
299 #define VC4_RENDER_CONFIG_MS_MODE_4X               BIT(0)
300 
301 #define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX         (1 << 4)
302 #define VC4_PRIMITIVE_LIST_FORMAT_32_XY            (3 << 4)
303 #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS      (0 << 0)
304 #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES       (1 << 0)
305 #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES   (2 << 0)
306 #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT         (3 << 0)
307 
308 enum vc4_texture_data_type {
309 	VC4_TEXTURE_TYPE_RGBA8888 = 0,
310 	VC4_TEXTURE_TYPE_RGBX8888 = 1,
311 	VC4_TEXTURE_TYPE_RGBA4444 = 2,
312 	VC4_TEXTURE_TYPE_RGBA5551 = 3,
313 	VC4_TEXTURE_TYPE_RGB565 = 4,
314 	VC4_TEXTURE_TYPE_LUMINANCE = 5,
315 	VC4_TEXTURE_TYPE_ALPHA = 6,
316 	VC4_TEXTURE_TYPE_LUMALPHA = 7,
317 	VC4_TEXTURE_TYPE_ETC1 = 8,
318 	VC4_TEXTURE_TYPE_S16F = 9,
319 	VC4_TEXTURE_TYPE_S8 = 10,
320 	VC4_TEXTURE_TYPE_S16 = 11,
321 	VC4_TEXTURE_TYPE_BW1 = 12,
322 	VC4_TEXTURE_TYPE_A4 = 13,
323 	VC4_TEXTURE_TYPE_A1 = 14,
324 	VC4_TEXTURE_TYPE_RGBA64 = 15,
325 	VC4_TEXTURE_TYPE_RGBA32R = 16,
326 	VC4_TEXTURE_TYPE_YUV422R = 17,
327 };
328 
329 #define VC4_TEX_P0_OFFSET_MASK                     VC4_MASK(31, 12)
330 #define VC4_TEX_P0_OFFSET_SHIFT                    12
331 #define VC4_TEX_P0_CSWIZ_MASK                      VC4_MASK(11, 10)
332 #define VC4_TEX_P0_CSWIZ_SHIFT                     10
333 #define VC4_TEX_P0_CMMODE_MASK                     VC4_MASK(9, 9)
334 #define VC4_TEX_P0_CMMODE_SHIFT                    9
335 #define VC4_TEX_P0_FLIPY_MASK                      VC4_MASK(8, 8)
336 #define VC4_TEX_P0_FLIPY_SHIFT                     8
337 #define VC4_TEX_P0_TYPE_MASK                       VC4_MASK(7, 4)
338 #define VC4_TEX_P0_TYPE_SHIFT                      4
339 #define VC4_TEX_P0_MIPLVLS_MASK                    VC4_MASK(3, 0)
340 #define VC4_TEX_P0_MIPLVLS_SHIFT                   0
341 
342 #define VC4_TEX_P1_TYPE4_MASK                      VC4_MASK(31, 31)
343 #define VC4_TEX_P1_TYPE4_SHIFT                     31
344 #define VC4_TEX_P1_HEIGHT_MASK                     VC4_MASK(30, 20)
345 #define VC4_TEX_P1_HEIGHT_SHIFT                    20
346 #define VC4_TEX_P1_ETCFLIP_MASK                    VC4_MASK(19, 19)
347 #define VC4_TEX_P1_ETCFLIP_SHIFT                   19
348 #define VC4_TEX_P1_WIDTH_MASK                      VC4_MASK(18, 8)
349 #define VC4_TEX_P1_WIDTH_SHIFT                     8
350 
351 #define VC4_TEX_P1_MAGFILT_MASK                    VC4_MASK(7, 7)
352 #define VC4_TEX_P1_MAGFILT_SHIFT                   7
353 # define VC4_TEX_P1_MAGFILT_LINEAR                 0
354 # define VC4_TEX_P1_MAGFILT_NEAREST                1
355 
356 #define VC4_TEX_P1_MINFILT_MASK                    VC4_MASK(6, 4)
357 #define VC4_TEX_P1_MINFILT_SHIFT                   4
358 # define VC4_TEX_P1_MINFILT_LINEAR                 0
359 # define VC4_TEX_P1_MINFILT_NEAREST                1
360 # define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR          2
361 # define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN           3
362 # define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR           4
363 # define VC4_TEX_P1_MINFILT_LIN_MIP_LIN            5
364 
365 #define VC4_TEX_P1_WRAP_T_MASK                     VC4_MASK(3, 2)
366 #define VC4_TEX_P1_WRAP_T_SHIFT                    2
367 #define VC4_TEX_P1_WRAP_S_MASK                     VC4_MASK(1, 0)
368 #define VC4_TEX_P1_WRAP_S_SHIFT                    0
369 # define VC4_TEX_P1_WRAP_REPEAT                    0
370 # define VC4_TEX_P1_WRAP_CLAMP                     1
371 # define VC4_TEX_P1_WRAP_MIRROR                    2
372 # define VC4_TEX_P1_WRAP_BORDER                    3
373 
374 #define VC4_TEX_P2_PTYPE_MASK                      VC4_MASK(31, 30)
375 #define VC4_TEX_P2_PTYPE_SHIFT                     30
376 # define VC4_TEX_P2_PTYPE_IGNORED                  0
377 # define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE          1
378 # define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS   2
379 # define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS      3
380 
381 /* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */
382 #define VC4_TEX_P2_CMST_MASK                       VC4_MASK(29, 12)
383 #define VC4_TEX_P2_CMST_SHIFT                      12
384 #define VC4_TEX_P2_BSLOD_MASK                      VC4_MASK(0, 0)
385 #define VC4_TEX_P2_BSLOD_SHIFT                     0
386 
387 /* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */
388 #define VC4_TEX_P2_CHEIGHT_MASK                    VC4_MASK(22, 12)
389 #define VC4_TEX_P2_CHEIGHT_SHIFT                   12
390 #define VC4_TEX_P2_CWIDTH_MASK                     VC4_MASK(10, 0)
391 #define VC4_TEX_P2_CWIDTH_SHIFT                    0
392 
393 /* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */
394 #define VC4_TEX_P2_CYOFF_MASK                      VC4_MASK(22, 12)
395 #define VC4_TEX_P2_CYOFF_SHIFT                     12
396 #define VC4_TEX_P2_CXOFF_MASK                      VC4_MASK(10, 0)
397 #define VC4_TEX_P2_CXOFF_SHIFT                     0
398 
399 #endif /* VC4_PACKET_H */
400