1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <errno.h>
11 #include <asm/io.h>
12 #include <asm/arch/ddr.h>
13 #include <asm/arch/imx8mq_pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/gpio.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <fsl_esdhc.h>
20 #include <mmc.h>
21 #include <power/pmic.h>
22 #include <power/pfuze100_pmic.h>
23 #include <spl.h>
24 #include "../common/pfuze.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 extern struct dram_timing_info dram_timing_b0;
29
spl_dram_init(void)30 void spl_dram_init(void)
31 {
32 /* ddr init */
33 if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
34 ddr_init(&dram_timing);
35 else
36 ddr_init(&dram_timing_b0);
37 }
38
39 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
40 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
41 struct i2c_pads_info i2c_pad_info1 = {
42 .scl = {
43 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
44 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
45 .gp = IMX_GPIO_NR(5, 14),
46 },
47 .sda = {
48 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
49 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
50 .gp = IMX_GPIO_NR(5, 15),
51 },
52 };
53
54 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
55 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
56 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
57
board_mmc_getcd(struct mmc * mmc)58 int board_mmc_getcd(struct mmc *mmc)
59 {
60 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
61 int ret = 0;
62
63 switch (cfg->esdhc_base) {
64 case USDHC1_BASE_ADDR:
65 ret = 1;
66 break;
67 case USDHC2_BASE_ADDR:
68 ret = !gpio_get_value(USDHC2_CD_GPIO);
69 return ret;
70 }
71
72 return 1;
73 }
74
75 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
76 PAD_CTL_FSEL2)
77 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
78
79 static iomux_v3_cfg_t const usdhc1_pads[] = {
80 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
91 };
92
93 static iomux_v3_cfg_t const usdhc2_pads[] = {
94 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
95 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
96 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
97 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
98 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
99 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
100 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
101 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
102 };
103
104 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
105 {USDHC1_BASE_ADDR, 0, 8},
106 {USDHC2_BASE_ADDR, 0, 4},
107 };
108
board_mmc_init(bd_t * bis)109 int board_mmc_init(bd_t *bis)
110 {
111 int i, ret;
112 /*
113 * According to the board_mmc_init() the following map is done:
114 * (U-Boot device node) (Physical Port)
115 * mmc0 USDHC1
116 * mmc1 USDHC2
117 */
118 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
119 switch (i) {
120 case 0:
121 init_clk_usdhc(0);
122 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
123 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
124 ARRAY_SIZE(usdhc1_pads));
125 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
126 gpio_direction_output(USDHC1_PWR_GPIO, 0);
127 udelay(500);
128 gpio_direction_output(USDHC1_PWR_GPIO, 1);
129 break;
130 case 1:
131 init_clk_usdhc(1);
132 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
133 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
134 ARRAY_SIZE(usdhc2_pads));
135 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
136 gpio_direction_output(USDHC2_PWR_GPIO, 0);
137 udelay(500);
138 gpio_direction_output(USDHC2_PWR_GPIO, 1);
139 break;
140 default:
141 printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
142 return -EINVAL;
143 }
144
145 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
146 if (ret)
147 return ret;
148 }
149
150 return 0;
151 }
152
153 #ifdef CONFIG_POWER
154 #define I2C_PMIC 0
power_init_board(void)155 int power_init_board(void)
156 {
157 struct pmic *p;
158 int ret;
159 unsigned int reg;
160
161 ret = power_pfuze100_init(I2C_PMIC);
162 if (ret)
163 return -ENODEV;
164
165 p = pmic_get("PFUZE100");
166 ret = pmic_probe(p);
167 if (ret)
168 return -ENODEV;
169
170 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
171 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
172
173 pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
174 if ((reg & 0x3f) != 0x18) {
175 reg &= ~0x3f;
176 reg |= 0x18;
177 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
178 }
179
180 ret = pfuze_mode_init(p, APS_PFM);
181 if (ret < 0)
182 return ret;
183
184 /* set SW3A standby mode to off */
185 pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
186 reg &= ~0xf;
187 reg |= APS_OFF;
188 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
189
190 return 0;
191 }
192 #endif
193
spl_board_init(void)194 void spl_board_init(void)
195 {
196 puts("Normal Boot\n");
197 }
198
199 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)200 int board_fit_config_name_match(const char *name)
201 {
202 /* Just empty function now - can't decide what to choose */
203 debug("%s: %s\n", __func__, name);
204
205 return 0;
206 }
207 #endif
208
board_init_f(ulong dummy)209 void board_init_f(ulong dummy)
210 {
211 int ret;
212
213 /* Clear global data */
214 memset((void *)gd, 0, sizeof(gd_t));
215
216 arch_cpu_init();
217
218 init_uart_clk(0);
219
220 board_early_init_f();
221
222 timer_init();
223
224 preloader_console_init();
225
226 /* Clear the BSS. */
227 memset(__bss_start, 0, __bss_end - __bss_start);
228
229 ret = spl_init();
230 if (ret) {
231 debug("spl_init() failed: %d\n", ret);
232 hang();
233 }
234
235 enable_tzc380();
236
237 /* Adjust pmic voltage to 1.0V for 800M */
238 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
239
240 power_init_board();
241
242 /* DDR initialization */
243 spl_dram_init();
244
245 board_init_r(NULL, 0);
246 }
247