1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
4 *
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
6 */
7
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/clk.h>
17 #include <linux/regmap.h>
18 #include <linux/pinctrl/consumer.h>
19
20 #include "core.h"
21
22 /* USB WRAPPER register offsets */
23 #define USBSS_PID 0x0
24 #define USBSS_OVERCURRENT_CTRL 0x4
25 #define USBSS_PHY_CONFIG 0x8
26 #define USBSS_PHY_TEST 0xc
27 #define USBSS_CORE_STAT 0x14
28 #define USBSS_HOST_VBUS_CTRL 0x18
29 #define USBSS_MODE_CONTROL 0x1c
30 #define USBSS_WAKEUP_CONFIG 0x30
31 #define USBSS_WAKEUP_STAT 0x34
32 #define USBSS_OVERRIDE_CONFIG 0x38
33 #define USBSS_IRQ_MISC_STATUS_RAW 0x430
34 #define USBSS_IRQ_MISC_STATUS 0x434
35 #define USBSS_IRQ_MISC_ENABLE_SET 0x438
36 #define USBSS_IRQ_MISC_ENABLE_CLR 0x43c
37 #define USBSS_IRQ_MISC_EOI 0x440
38 #define USBSS_INTR_TEST 0x490
39 #define USBSS_VBUS_FILTER 0x614
40 #define USBSS_VBUS_STAT 0x618
41 #define USBSS_DEBUG_CFG 0x708
42 #define USBSS_DEBUG_DATA 0x70c
43 #define USBSS_HOST_HUB_CTRL 0x714
44
45 /* PHY CONFIG register bits */
46 #define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1)
47 #define USBSS_PHY_VBUS_SEL_SHIFT 1
48 #define USBSS_PHY_LANE_REVERSE BIT(0)
49
50 /* CORE STAT register bits */
51 #define USBSS_CORE_OPERATIONAL_MODE_MASK GENMASK(13, 12)
52 #define USBSS_CORE_OPERATIONAL_MODE_SHIFT 12
53
54 /* MODE CONTROL register bits */
55 #define USBSS_MODE_VALID BIT(0)
56
57 /* WAKEUP CONFIG register bits */
58 #define USBSS_WAKEUP_CFG_OVERCURRENT_EN BIT(3)
59 #define USBSS_WAKEUP_CFG_LINESTATE_EN BIT(2)
60 #define USBSS_WAKEUP_CFG_SESSVALID_EN BIT(1)
61 #define USBSS_WAKEUP_CFG_VBUSVALID_EN BIT(0)
62
63 #define USBSS_WAKEUP_CFG_ALL (USBSS_WAKEUP_CFG_VBUSVALID_EN | \
64 USBSS_WAKEUP_CFG_SESSVALID_EN | \
65 USBSS_WAKEUP_CFG_LINESTATE_EN | \
66 USBSS_WAKEUP_CFG_OVERCURRENT_EN)
67
68 #define USBSS_WAKEUP_CFG_NONE 0
69
70 /* WAKEUP STAT register bits */
71 #define USBSS_WAKEUP_STAT_OVERCURRENT BIT(4)
72 #define USBSS_WAKEUP_STAT_LINESTATE BIT(3)
73 #define USBSS_WAKEUP_STAT_SESSVALID BIT(2)
74 #define USBSS_WAKEUP_STAT_VBUSVALID BIT(1)
75 #define USBSS_WAKEUP_STAT_CLR BIT(0)
76
77 /* IRQ_MISC_STATUS_RAW register bits */
78 #define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22)
79 #define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20)
80
81 /* IRQ_MISC_STATUS register bits */
82 #define USBSS_IRQ_MISC_VBUSVALID BIT(22)
83 #define USBSS_IRQ_MISC_SESSVALID BIT(20)
84
85 /* IRQ_MISC_ENABLE_SET register bits */
86 #define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID BIT(22)
87 #define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID BIT(20)
88
89 /* IRQ_MISC_ENABLE_CLR register bits */
90 #define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID BIT(22)
91 #define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID BIT(20)
92
93 /* IRQ_MISC_EOI register bits */
94 #define USBSS_IRQ_MISC_EOI_VECTOR BIT(0)
95
96 /* VBUS_STAT register bits */
97 #define USBSS_VBUS_STAT_SESSVALID BIT(2)
98 #define USBSS_VBUS_STAT_VBUSVALID BIT(0)
99
100 /* Mask for PHY PLL REFCLK */
101 #define PHY_PLL_REFCLK_MASK GENMASK(3, 0)
102
103 #define DWC3_AM62_AUTOSUSPEND_DELAY 100
104
105 struct dwc3_am62 {
106 struct device *dev;
107 void __iomem *usbss;
108 struct clk *usb2_refclk;
109 int rate_code;
110 struct regmap *syscon;
111 unsigned int offset;
112 unsigned int vbus_divider;
113 u32 wakeup_stat;
114 };
115
116 static const int dwc3_ti_rate_table[] = { /* in KHZ */
117 9600,
118 10000,
119 12000,
120 19200,
121 20000,
122 24000,
123 25000,
124 26000,
125 38400,
126 40000,
127 58000,
128 50000,
129 52000,
130 };
131
dwc3_ti_readl(struct dwc3_am62 * am62,u32 offset)132 static inline u32 dwc3_ti_readl(struct dwc3_am62 *am62, u32 offset)
133 {
134 return readl((am62->usbss) + offset);
135 }
136
dwc3_ti_writel(struct dwc3_am62 * am62,u32 offset,u32 value)137 static inline void dwc3_ti_writel(struct dwc3_am62 *am62, u32 offset, u32 value)
138 {
139 writel(value, (am62->usbss) + offset);
140 }
141
phy_syscon_pll_refclk(struct dwc3_am62 * am62)142 static int phy_syscon_pll_refclk(struct dwc3_am62 *am62)
143 {
144 struct device *dev = am62->dev;
145 struct device_node *node = dev->of_node;
146 struct of_phandle_args args;
147 struct regmap *syscon;
148 int ret;
149
150 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-phy-pll-refclk");
151 if (IS_ERR(syscon)) {
152 dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n");
153 return PTR_ERR(syscon);
154 }
155
156 am62->syscon = syscon;
157
158 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-phy-pll-refclk", 1,
159 0, &args);
160 if (ret)
161 return ret;
162
163 of_node_put(args.np);
164 am62->offset = args.args[0];
165
166 ret = regmap_update_bits(am62->syscon, am62->offset, PHY_PLL_REFCLK_MASK, am62->rate_code);
167 if (ret) {
168 dev_err(dev, "failed to set phy pll reference clock rate\n");
169 return ret;
170 }
171
172 return 0;
173 }
174
dwc3_ti_probe(struct platform_device * pdev)175 static int dwc3_ti_probe(struct platform_device *pdev)
176 {
177 struct device *dev = &pdev->dev;
178 struct device_node *node = pdev->dev.of_node;
179 struct dwc3_am62 *am62;
180 int i, ret;
181 unsigned long rate;
182 u32 reg;
183
184 am62 = devm_kzalloc(dev, sizeof(*am62), GFP_KERNEL);
185 if (!am62)
186 return -ENOMEM;
187
188 am62->dev = dev;
189 platform_set_drvdata(pdev, am62);
190
191 am62->usbss = devm_platform_ioremap_resource(pdev, 0);
192 if (IS_ERR(am62->usbss)) {
193 dev_err(dev, "can't map IOMEM resource\n");
194 return PTR_ERR(am62->usbss);
195 }
196
197 am62->usb2_refclk = devm_clk_get(dev, "ref");
198 if (IS_ERR(am62->usb2_refclk)) {
199 dev_err(dev, "can't get usb2_refclk\n");
200 return PTR_ERR(am62->usb2_refclk);
201 }
202
203 /* Calculate the rate code */
204 rate = clk_get_rate(am62->usb2_refclk);
205 rate /= 1000; // To KHz
206 for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) {
207 if (dwc3_ti_rate_table[i] == rate)
208 break;
209 }
210
211 if (i == ARRAY_SIZE(dwc3_ti_rate_table)) {
212 dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
213 return -EINVAL;
214 }
215
216 am62->rate_code = i;
217
218 /* Read the syscon property and set the rate code */
219 ret = phy_syscon_pll_refclk(am62);
220 if (ret)
221 return ret;
222
223 /* VBUS divider select */
224 am62->vbus_divider = device_property_read_bool(dev, "ti,vbus-divider");
225 reg = dwc3_ti_readl(am62, USBSS_PHY_CONFIG);
226 if (am62->vbus_divider)
227 reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT;
228
229 dwc3_ti_writel(am62, USBSS_PHY_CONFIG, reg);
230
231 pm_runtime_set_active(dev);
232 pm_runtime_enable(dev);
233 /*
234 * Don't ignore its dependencies with its children
235 */
236 pm_suspend_ignore_children(dev, false);
237 clk_prepare_enable(am62->usb2_refclk);
238 pm_runtime_get_noresume(dev);
239
240 ret = of_platform_populate(node, NULL, NULL, dev);
241 if (ret) {
242 dev_err(dev, "failed to create dwc3 core: %d\n", ret);
243 goto err_pm_disable;
244 }
245
246 /* Set mode valid bit to indicate role is valid */
247 reg = dwc3_ti_readl(am62, USBSS_MODE_CONTROL);
248 reg |= USBSS_MODE_VALID;
249 dwc3_ti_writel(am62, USBSS_MODE_CONTROL, reg);
250
251 /* Device has capability to wakeup system from sleep */
252 device_set_wakeup_capable(dev, true);
253 ret = device_wakeup_enable(dev);
254 if (ret)
255 dev_err(dev, "couldn't enable device as a wakeup source: %d\n", ret);
256
257 /* Setting up autosuspend */
258 pm_runtime_set_autosuspend_delay(dev, DWC3_AM62_AUTOSUSPEND_DELAY);
259 pm_runtime_use_autosuspend(dev);
260 pm_runtime_mark_last_busy(dev);
261 pm_runtime_put_autosuspend(dev);
262 return 0;
263
264 err_pm_disable:
265 clk_disable_unprepare(am62->usb2_refclk);
266 pm_runtime_disable(dev);
267 pm_runtime_set_suspended(dev);
268 return ret;
269 }
270
dwc3_ti_remove(struct platform_device * pdev)271 static void dwc3_ti_remove(struct platform_device *pdev)
272 {
273 struct device *dev = &pdev->dev;
274 struct dwc3_am62 *am62 = platform_get_drvdata(pdev);
275 u32 reg;
276
277 pm_runtime_get_sync(dev);
278 device_init_wakeup(dev, false);
279 of_platform_depopulate(dev);
280
281 /* Clear mode valid bit */
282 reg = dwc3_ti_readl(am62, USBSS_MODE_CONTROL);
283 reg &= ~USBSS_MODE_VALID;
284 dwc3_ti_writel(am62, USBSS_MODE_CONTROL, reg);
285
286 pm_runtime_put_sync(dev);
287 pm_runtime_disable(dev);
288 pm_runtime_dont_use_autosuspend(dev);
289 pm_runtime_set_suspended(dev);
290 }
291
292 #ifdef CONFIG_PM
dwc3_ti_suspend_common(struct device * dev)293 static int dwc3_ti_suspend_common(struct device *dev)
294 {
295 struct dwc3_am62 *am62 = dev_get_drvdata(dev);
296 u32 reg, current_prtcap_dir;
297
298 if (device_may_wakeup(dev)) {
299 reg = dwc3_ti_readl(am62, USBSS_CORE_STAT);
300 current_prtcap_dir = (reg & USBSS_CORE_OPERATIONAL_MODE_MASK)
301 >> USBSS_CORE_OPERATIONAL_MODE_SHIFT;
302 /* Set wakeup config enable bits */
303 reg = dwc3_ti_readl(am62, USBSS_WAKEUP_CONFIG);
304 if (current_prtcap_dir == DWC3_GCTL_PRTCAP_HOST) {
305 reg = USBSS_WAKEUP_CFG_LINESTATE_EN | USBSS_WAKEUP_CFG_OVERCURRENT_EN;
306 } else {
307 reg = USBSS_WAKEUP_CFG_VBUSVALID_EN | USBSS_WAKEUP_CFG_SESSVALID_EN;
308 /*
309 * Enable LINESTATE wake up only if connected to bus
310 * and in U2/L3 state else it causes spurious wake-up.
311 */
312 }
313 dwc3_ti_writel(am62, USBSS_WAKEUP_CONFIG, reg);
314 /* clear wakeup status so we know what caused the wake up */
315 dwc3_ti_writel(am62, USBSS_WAKEUP_STAT, USBSS_WAKEUP_STAT_CLR);
316 }
317
318 clk_disable_unprepare(am62->usb2_refclk);
319
320 return 0;
321 }
322
dwc3_ti_resume_common(struct device * dev)323 static int dwc3_ti_resume_common(struct device *dev)
324 {
325 struct dwc3_am62 *am62 = dev_get_drvdata(dev);
326 u32 reg;
327
328 clk_prepare_enable(am62->usb2_refclk);
329
330 if (device_may_wakeup(dev)) {
331 /* Clear wakeup config enable bits */
332 dwc3_ti_writel(am62, USBSS_WAKEUP_CONFIG, USBSS_WAKEUP_CFG_NONE);
333 }
334
335 reg = dwc3_ti_readl(am62, USBSS_WAKEUP_STAT);
336 am62->wakeup_stat = reg;
337
338 return 0;
339 }
340
341 static UNIVERSAL_DEV_PM_OPS(dwc3_ti_pm_ops, dwc3_ti_suspend_common,
342 dwc3_ti_resume_common, NULL);
343
344 #define DEV_PM_OPS (&dwc3_ti_pm_ops)
345 #else
346 #define DEV_PM_OPS NULL
347 #endif /* CONFIG_PM */
348
349 static const struct of_device_id dwc3_ti_of_match[] = {
350 { .compatible = "ti,am62-usb"},
351 {},
352 };
353 MODULE_DEVICE_TABLE(of, dwc3_ti_of_match);
354
355 static struct platform_driver dwc3_ti_driver = {
356 .probe = dwc3_ti_probe,
357 .remove_new = dwc3_ti_remove,
358 .driver = {
359 .name = "dwc3-am62",
360 .pm = DEV_PM_OPS,
361 .of_match_table = dwc3_ti_of_match,
362 },
363 };
364
365 module_platform_driver(dwc3_ti_driver);
366
367 MODULE_ALIAS("platform:dwc3-am62");
368 MODULE_AUTHOR("Aswath Govindraju <a-govindraju@ti.com>");
369 MODULE_LICENSE("GPL");
370 MODULE_DESCRIPTION("DesignWare USB3 TI Glue Layer");
371