1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for Compulab CM-FX6 board
4 *
5 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 *
7 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 */
9
10 #include <common.h>
11 #include <ahci.h>
12 #include <dm.h>
13 #include <dwc_ahsata.h>
14 #include <environment.h>
15 #include <fsl_esdhc.h>
16 #include <miiphy.h>
17 #include <mtd_node.h>
18 #include <netdev.h>
19 #include <errno.h>
20 #include <usb.h>
21 #include <fdt_support.h>
22 #include <sata.h>
23 #include <splash.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/iomux.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/mach-imx/mxc_i2c.h>
29 #include <asm/mach-imx/sata.h>
30 #include <asm/mach-imx/video.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <dm/platform_data/serial_mxc.h>
34 #include <dm/device-internal.h>
35 #include <jffs2/load_kernel.h>
36 #include "common.h"
37 #include "../common/eeprom.h"
38 #include "../common/common.h"
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #ifdef CONFIG_SPLASH_SCREEN
43 static struct splash_location cm_fx6_splash_locations[] = {
44 {
45 .name = "sf",
46 .storage = SPLASH_STORAGE_SF,
47 .flags = SPLASH_STORAGE_RAW,
48 .offset = 0x100000,
49 },
50 {
51 .name = "mmc_fs",
52 .storage = SPLASH_STORAGE_MMC,
53 .flags = SPLASH_STORAGE_FS,
54 .devpart = "2:1",
55 },
56 {
57 .name = "usb_fs",
58 .storage = SPLASH_STORAGE_USB,
59 .flags = SPLASH_STORAGE_FS,
60 .devpart = "0:1",
61 },
62 {
63 .name = "sata_fs",
64 .storage = SPLASH_STORAGE_SATA,
65 .flags = SPLASH_STORAGE_FS,
66 .devpart = "0:1",
67 },
68 };
69
splash_screen_prepare(void)70 int splash_screen_prepare(void)
71 {
72 return splash_source_load(cm_fx6_splash_locations,
73 ARRAY_SIZE(cm_fx6_splash_locations));
74 }
75 #endif
76
77 #ifdef CONFIG_IMX_HDMI
cm_fx6_enable_hdmi(struct display_info_t const * dev)78 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
79 {
80 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
81 imx_setup_hdmi();
82 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
83 imx_enable_hdmi_phy();
84 }
85
86 static struct display_info_t preset_hdmi_1024X768 = {
87 .bus = -1,
88 .addr = 0,
89 .pixfmt = IPU_PIX_FMT_RGB24,
90 .enable = cm_fx6_enable_hdmi,
91 .mode = {
92 .name = "HDMI",
93 .refresh = 60,
94 .xres = 1024,
95 .yres = 768,
96 .pixclock = 40385,
97 .left_margin = 220,
98 .right_margin = 40,
99 .upper_margin = 21,
100 .lower_margin = 7,
101 .hsync_len = 60,
102 .vsync_len = 10,
103 .sync = FB_SYNC_EXT,
104 .vmode = FB_VMODE_NONINTERLACED,
105 }
106 };
107
cm_fx6_setup_display(void)108 static void cm_fx6_setup_display(void)
109 {
110 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
111
112 enable_ipu_clock();
113 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
114 }
115
board_video_skip(void)116 int board_video_skip(void)
117 {
118 int ret;
119 struct display_info_t *preset;
120 char const *panel = env_get("displaytype");
121
122 if (!panel) /* Also accept panel for backward compatibility */
123 panel = env_get("panel");
124
125 if (!panel)
126 return -ENOENT;
127
128 if (!strcmp(panel, "HDMI"))
129 preset = &preset_hdmi_1024X768;
130 else
131 return -EINVAL;
132
133 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
134 if (ret) {
135 printf("Can't init display %s: %d\n", preset->mode.name, ret);
136 return ret;
137 }
138
139 preset->enable(preset);
140 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
141 preset->mode.yres);
142
143 return 0;
144 }
145 #else
cm_fx6_setup_display(void)146 static inline void cm_fx6_setup_display(void) {}
147 #endif /* CONFIG_VIDEO_IPUV3 */
148
149 #ifdef CONFIG_DWC_AHSATA
150 static int cm_fx6_issd_gpios[] = {
151 /* The order of the GPIOs in the array is important! */
152 CM_FX6_SATA_LDO_EN,
153 CM_FX6_SATA_PHY_SLP,
154 CM_FX6_SATA_NRSTDLY,
155 CM_FX6_SATA_PWREN,
156 CM_FX6_SATA_NSTANDBY1,
157 CM_FX6_SATA_NSTANDBY2,
158 };
159
cm_fx6_sata_power(int on)160 static void cm_fx6_sata_power(int on)
161 {
162 int i;
163
164 if (!on) { /* tell the iSSD that the power will be removed */
165 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
166 mdelay(10);
167 }
168
169 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
170 gpio_direction_output(cm_fx6_issd_gpios[i], on);
171 udelay(100);
172 }
173
174 if (!on) /* for compatibility lower the power loss interrupt */
175 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
176 }
177
178 static iomux_v3_cfg_t const sata_pads[] = {
179 /* SATA PWR */
180 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
184 /* SATA CTRL */
185 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
190 };
191
cm_fx6_setup_issd(void)192 static int cm_fx6_setup_issd(void)
193 {
194 int ret, i;
195
196 SETUP_IOMUX_PADS(sata_pads);
197
198 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
199 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
200 if (ret)
201 return ret;
202 }
203
204 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
205 if (ret)
206 return ret;
207
208 return 0;
209 }
210
211 #define CM_FX6_SATA_INIT_RETRIES 10
212
213 #else
cm_fx6_setup_issd(void)214 static int cm_fx6_setup_issd(void) { return 0; }
215 #endif
216
217 #ifdef CONFIG_SYS_I2C_MXC
218 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
219 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
220 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
221
222 I2C_PADS(i2c0_pads,
223 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
224 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
225 IMX_GPIO_NR(3, 21),
226 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
227 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
228 IMX_GPIO_NR(3, 28));
229
230 I2C_PADS(i2c1_pads,
231 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
232 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
233 IMX_GPIO_NR(4, 12),
234 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
235 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
236 IMX_GPIO_NR(4, 13));
237
238 I2C_PADS(i2c2_pads,
239 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
240 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
241 IMX_GPIO_NR(1, 3),
242 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
243 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
244 IMX_GPIO_NR(1, 6));
245
246
cm_fx6_setup_one_i2c(int busnum,struct i2c_pads_info * pads)247 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
248 {
249 int ret;
250
251 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
252 if (ret)
253 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
254
255 return ret;
256 }
257
cm_fx6_setup_i2c(void)258 static int cm_fx6_setup_i2c(void)
259 {
260 int ret = 0, err;
261
262 /* i2c<x>_pads are wierd macro variables; we can't use an array */
263 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
264 if (err)
265 ret = err;
266 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
267 if (err)
268 ret = err;
269 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
270 if (err)
271 ret = err;
272
273 return ret;
274 }
275 #else
cm_fx6_setup_i2c(void)276 static int cm_fx6_setup_i2c(void) { return 0; }
277 #endif
278
279 #ifdef CONFIG_USB_EHCI_MX6
280 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
281 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
282 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
283 #define MX6_USBNC_BASEADDR 0x2184800
284 #define USBNC_USB_H1_PWR_POL (1 << 9)
285
cm_fx6_setup_usb_host(void)286 static int cm_fx6_setup_usb_host(void)
287 {
288 int err;
289
290 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
291 if (err)
292 return err;
293
294 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
295 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
296
297 return 0;
298 }
299
cm_fx6_setup_usb_otg(void)300 static int cm_fx6_setup_usb_otg(void)
301 {
302 int err;
303 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
304
305 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
306 if (err) {
307 printf("USB OTG pwr gpio request failed: %d\n", err);
308 return err;
309 }
310
311 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
312 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
313 MUX_PAD_CTRL(WEAK_PULLDOWN));
314 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
315 /* disable ext. charger detect, or it'll affect signal quality at dp. */
316 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
317 }
318
board_usb_phy_mode(int port)319 int board_usb_phy_mode(int port)
320 {
321 return USB_INIT_HOST;
322 }
323
board_ehci_hcd_init(int port)324 int board_ehci_hcd_init(int port)
325 {
326 int ret;
327 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
328
329 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
330 if (port != 1)
331 return 0;
332
333 /* Set PWR polarity to match power switch's enable polarity */
334 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
335 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
336 if (ret)
337 return ret;
338
339 udelay(10);
340 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
341 if (ret)
342 return ret;
343
344 mdelay(1);
345
346 return 0;
347 }
348
board_ehci_power(int port,int on)349 int board_ehci_power(int port, int on)
350 {
351 if (port == 0)
352 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
353
354 return 0;
355 }
356 #else
cm_fx6_setup_usb_otg(void)357 static int cm_fx6_setup_usb_otg(void) { return 0; }
cm_fx6_setup_usb_host(void)358 static int cm_fx6_setup_usb_host(void) { return 0; }
359 #endif
360
361 #ifdef CONFIG_FEC_MXC
362 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
363 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
364
mx6_rgmii_rework(struct phy_device * phydev)365 static int mx6_rgmii_rework(struct phy_device *phydev)
366 {
367 unsigned short val;
368
369 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
370 * which cause ethernet link down/up issue, so disable SmartEEE
371 */
372 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
373 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
374 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
375 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
376 val &= ~(0x1 << 8);
377 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
378
379 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
380 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
381 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
382 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
383
384 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
385 val &= 0xffe3;
386 val |= 0x18;
387 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
388
389 /* introduce tx clock delay */
390 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
391 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
392 val |= 0x0100;
393 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
394
395 return 0;
396 }
397
board_phy_config(struct phy_device * phydev)398 int board_phy_config(struct phy_device *phydev)
399 {
400 mx6_rgmii_rework(phydev);
401
402 if (phydev->drv->config)
403 return phydev->drv->config(phydev);
404
405 return 0;
406 }
407
408 static iomux_v3_cfg_t const enet_pads[] = {
409 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
410 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
411 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
412 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
413 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
414 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
415 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
416 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
417 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
418 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
419 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
420 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
421 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
422 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
423 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
424 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
425 MUX_PAD_CTRL(ENET_PAD_CTRL)),
426 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
427 MUX_PAD_CTRL(ENET_PAD_CTRL)),
428 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
429 MUX_PAD_CTRL(ENET_PAD_CTRL)),
430 };
431
handle_mac_address(char * env_var,uint eeprom_bus)432 static int handle_mac_address(char *env_var, uint eeprom_bus)
433 {
434 unsigned char enetaddr[6];
435 int rc;
436
437 rc = eth_env_get_enetaddr(env_var, enetaddr);
438 if (rc)
439 return 0;
440
441 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
442 if (rc)
443 return rc;
444
445 if (!is_valid_ethaddr(enetaddr))
446 return -1;
447
448 return eth_env_set_enetaddr(env_var, enetaddr);
449 }
450
451 #define SB_FX6_I2C_EEPROM_BUS 0
452 #define NO_MAC_ADDR "No MAC address found for %s\n"
board_eth_init(bd_t * bis)453 int board_eth_init(bd_t *bis)
454 {
455 int err;
456
457 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
458 printf(NO_MAC_ADDR, "primary NIC");
459
460 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
461 printf(NO_MAC_ADDR, "secondary NIC");
462
463 SETUP_IOMUX_PADS(enet_pads);
464 /* phy reset */
465 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
466 if (err)
467 printf("Etnernet NRST gpio request failed: %d\n", err);
468 gpio_direction_output(CM_FX6_ENET_NRST, 0);
469 udelay(500);
470 gpio_set_value(CM_FX6_ENET_NRST, 1);
471 enable_enet_clk(1);
472 return cpu_eth_init(bis);
473 }
474 #endif
475
476 #ifdef CONFIG_NAND_MXS
477 static iomux_v3_cfg_t const nand_pads[] = {
478 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
479 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
480 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
481 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
482 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
483 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
484 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
485 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
486 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
487 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
488 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
489 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
490 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
491 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
492 };
493
cm_fx6_setup_gpmi_nand(void)494 static void cm_fx6_setup_gpmi_nand(void)
495 {
496 SETUP_IOMUX_PADS(nand_pads);
497 /* Enable clock roots */
498 enable_usdhc_clk(1, 3);
499 enable_usdhc_clk(1, 4);
500
501 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
502 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
503 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
504 }
505 #else
cm_fx6_setup_gpmi_nand(void)506 static void cm_fx6_setup_gpmi_nand(void) {}
507 #endif
508
509 #ifdef CONFIG_MXC_SPI
cm_fx6_setup_ecspi(void)510 int cm_fx6_setup_ecspi(void)
511 {
512 cm_fx6_set_ecspi_iomux();
513 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
514 }
515 #else
cm_fx6_setup_ecspi(void)516 int cm_fx6_setup_ecspi(void) { return 0; }
517 #endif
518
519 #ifdef CONFIG_OF_BOARD_SETUP
520 #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
521
522 static const struct node_info nodes[] = {
523 /*
524 * Both entries target the same flash chip. The st,m25p compatible
525 * is used in the vendor device trees, while upstream uses (the
526 * documented) jedec,spi-nor compatible.
527 */
528 { "st,m25p", MTD_DEV_TYPE_NOR, },
529 { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
530 };
531
ft_board_setup(void * blob,bd_t * bd)532 int ft_board_setup(void *blob, bd_t *bd)
533 {
534 u32 baseboard_rev;
535 int nodeoffset;
536 uint8_t enetaddr[6];
537 char baseboard_name[16];
538 int err;
539
540 fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
541
542 /* MAC addr */
543 if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
544 fdt_find_and_setprop(blob,
545 "/soc/aips-bus@02100000/ethernet@02188000",
546 "local-mac-address", enetaddr, 6, 1);
547 }
548
549 if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
550 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
551 enetaddr, 6, 1);
552 }
553
554 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
555
556 baseboard_rev = cl_eeprom_get_board_rev(0);
557 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
558 if (err || baseboard_rev == 0)
559 return 0; /* Assume not an early revision SB-FX6m baseboard */
560
561 if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
562 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
563 fdt_delprop(blob, nodeoffset, "cd-gpios");
564 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
565 NULL, 0, 1);
566 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
567 NULL, 0, 1);
568 }
569
570 return 0;
571 }
572 #endif
573
board_init(void)574 int board_init(void)
575 {
576 int ret;
577
578 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
579 cm_fx6_setup_gpmi_nand();
580
581 ret = cm_fx6_setup_ecspi();
582 if (ret)
583 printf("Warning: ECSPI setup failed: %d\n", ret);
584
585 ret = cm_fx6_setup_usb_otg();
586 if (ret)
587 printf("Warning: USB OTG setup failed: %d\n", ret);
588
589 ret = cm_fx6_setup_usb_host();
590 if (ret)
591 printf("Warning: USB host setup failed: %d\n", ret);
592
593 /*
594 * cm-fx6 may have iSSD not assembled and in this case it has
595 * bypasses for a (m)SATA socket on the baseboard. The socketed
596 * device is not controlled by those GPIOs. So just print a warning
597 * if the setup fails.
598 */
599 ret = cm_fx6_setup_issd();
600 if (ret)
601 printf("Warning: iSSD setup failed: %d\n", ret);
602
603 /* Warn on failure but do not abort boot */
604 ret = cm_fx6_setup_i2c();
605 if (ret)
606 printf("Warning: I2C setup failed: %d\n", ret);
607
608 cm_fx6_setup_display();
609
610 /* This should be done in the MMC driver when MX6 has a clock driver */
611 #ifdef CONFIG_FSL_ESDHC
612 if (IS_ENABLED(CONFIG_BLK)) {
613 int i;
614
615 cm_fx6_set_usdhc_iomux();
616 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
617 enable_usdhc_clk(1, i);
618 }
619 #endif
620
621 return 0;
622 }
623
board_late_init(void)624 int board_late_init(void)
625 {
626 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
627 char baseboard_name[16];
628 int err;
629
630 if (is_mx6dq())
631 env_set("board_rev", "MX6Q");
632 else if (is_mx6dl())
633 env_set("board_rev", "MX6DL");
634
635 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
636 if (err)
637 return 0;
638
639 if (!strncmp("SB-FX6m", baseboard_name, 7))
640 env_set("board_name", "Utilite");
641 #endif
642 return 0;
643 }
644
checkboard(void)645 int checkboard(void)
646 {
647 puts("Board: CM-FX6\n");
648 return 0;
649 }
650
misc_init_r(void)651 int misc_init_r(void)
652 {
653 cl_print_pcb_info();
654
655 return 0;
656 }
657
dram_init_banksize(void)658 int dram_init_banksize(void)
659 {
660 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
661 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
662
663 switch (gd->ram_size) {
664 case 0x10000000: /* DDR_16BIT_256MB */
665 gd->bd->bi_dram[0].size = 0x10000000;
666 gd->bd->bi_dram[1].size = 0;
667 break;
668 case 0x20000000: /* DDR_32BIT_512MB */
669 gd->bd->bi_dram[0].size = 0x20000000;
670 gd->bd->bi_dram[1].size = 0;
671 break;
672 case 0x40000000:
673 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
674 gd->bd->bi_dram[0].size = 0x20000000;
675 gd->bd->bi_dram[1].size = 0x20000000;
676 } else { /* DDR_64BIT_1GB */
677 gd->bd->bi_dram[0].size = 0x40000000;
678 gd->bd->bi_dram[1].size = 0;
679 }
680 break;
681 case 0x80000000: /* DDR_64BIT_2GB */
682 gd->bd->bi_dram[0].size = 0x40000000;
683 gd->bd->bi_dram[1].size = 0x40000000;
684 break;
685 case 0xEFF00000: /* DDR_64BIT_4GB */
686 gd->bd->bi_dram[0].size = 0x70000000;
687 gd->bd->bi_dram[1].size = 0x7FF00000;
688 break;
689 }
690
691 return 0;
692 }
693
dram_init(void)694 int dram_init(void)
695 {
696 gd->ram_size = imx_ddr_size();
697 switch (gd->ram_size) {
698 case 0x10000000:
699 case 0x20000000:
700 case 0x40000000:
701 case 0x80000000:
702 break;
703 case 0xF0000000:
704 gd->ram_size -= 0x100000;
705 break;
706 default:
707 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
708 return -1;
709 }
710
711 return 0;
712 }
713
get_board_rev(void)714 u32 get_board_rev(void)
715 {
716 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
717 }
718
719 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
720 .reg = (struct mxc_uart *)UART4_BASE,
721 };
722
723 U_BOOT_DEVICE(cm_fx6_serial) = {
724 .name = "serial_mxc",
725 .platdata = &cm_fx6_mxc_serial_plat,
726 };
727
728 #if CONFIG_IS_ENABLED(AHCI)
sata_imx_probe(struct udevice * dev)729 static int sata_imx_probe(struct udevice *dev)
730 {
731 int i, err;
732
733 /* Make sure this gpio has logical 0 value */
734 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
735 udelay(100);
736 cm_fx6_sata_power(1);
737
738 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
739 err = setup_sata();
740 if (err) {
741 printf("SATA setup failed: %d\n", err);
742 return err;
743 }
744
745 udelay(100);
746
747 err = dwc_ahsata_probe(dev);
748 if (!err)
749 break;
750
751 /* There is no device on the SATA port */
752 if (sata_dm_port_status(0, 0) == 0)
753 break;
754
755 /* There's a device, but link not established. Retry */
756 device_remove(dev, DM_REMOVE_NORMAL);
757 }
758
759 return 0;
760 }
761
sata_imx_remove(struct udevice * dev)762 static int sata_imx_remove(struct udevice *dev)
763 {
764 cm_fx6_sata_power(0);
765 mdelay(250);
766
767 return 0;
768 }
769
770 struct ahci_ops sata_imx_ops = {
771 .port_status = dwc_ahsata_port_status,
772 .reset = dwc_ahsata_bus_reset,
773 .scan = dwc_ahsata_scan,
774 };
775
776 static const struct udevice_id sata_imx_ids[] = {
777 { .compatible = "fsl,imx6q-ahci" },
778 { }
779 };
780
781 U_BOOT_DRIVER(sata_imx) = {
782 .name = "dwc_ahci",
783 .id = UCLASS_AHCI,
784 .of_match = sata_imx_ids,
785 .ops = &sata_imx_ops,
786 .probe = sata_imx_probe,
787 .remove = sata_imx_remove, /* reset bus to stop it */
788 };
789 #endif /* AHCI */
790