xref: /openbmc/u-boot/drivers/usb/host/ehci-mx6.c (revision beff8e34)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4  * Copyright (C) 2010 Freescale Semiconductor, Inc.
5  */
6 
7 #include <common.h>
8 #include <usb.h>
9 #include <errno.h>
10 #include <wait_bit.h>
11 #include <linux/compiler.h>
12 #include <usb/ehci-ci.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sys_proto.h>
18 #include <dm.h>
19 #include <asm/mach-types.h>
20 #include <power/regulator.h>
21 
22 #include "ehci.h"
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 #define USB_OTGREGS_OFFSET	0x000
27 #define USB_H1REGS_OFFSET	0x200
28 #define USB_H2REGS_OFFSET	0x400
29 #define USB_H3REGS_OFFSET	0x600
30 #define USB_OTHERREGS_OFFSET	0x800
31 
32 #define USB_H1_CTRL_OFFSET	0x04
33 
34 #define USBPHY_CTRL				0x00000030
35 #define USBPHY_CTRL_SET				0x00000034
36 #define USBPHY_CTRL_CLR				0x00000038
37 #define USBPHY_CTRL_TOG				0x0000003c
38 
39 #define USBPHY_PWD				0x00000000
40 #define USBPHY_CTRL_SFTRST			0x80000000
41 #define USBPHY_CTRL_CLKGATE			0x40000000
42 #define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
43 #define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
44 #define USBPHY_CTRL_OTG_ID			0x08000000
45 
46 #define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
47 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
48 
49 #define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
50 #define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
51 #define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
52 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
53 
54 #define USBNC_OFFSET		0x200
55 #define USBNC_PHY_STATUS_OFFSET	0x23C
56 #define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
57 #define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
58 #define UCTRL_PWR_POL		(1 << 9) /* OTG Polarity of Power Pin */
59 #define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
60 #define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
61 
62 /* USBCMD */
63 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
64 #define UCMD_RESET		(1 << 1) /* controller reset */
65 
66 #if defined(CONFIG_MX6)
67 static const unsigned phy_bases[] = {
68 	USB_PHY0_BASE_ADDR,
69 	USB_PHY1_BASE_ADDR,
70 };
71 
usb_internal_phy_clock_gate(int index,int on)72 static void usb_internal_phy_clock_gate(int index, int on)
73 {
74 	void __iomem *phy_reg;
75 
76 	if (index >= ARRAY_SIZE(phy_bases))
77 		return;
78 
79 	phy_reg = (void __iomem *)phy_bases[index];
80 	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
81 	writel(USBPHY_CTRL_CLKGATE, phy_reg);
82 }
83 
usb_power_config(int index)84 static void usb_power_config(int index)
85 {
86 	struct anatop_regs __iomem *anatop =
87 		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
88 	void __iomem *chrg_detect;
89 	void __iomem *pll_480_ctrl_clr;
90 	void __iomem *pll_480_ctrl_set;
91 
92 	switch (index) {
93 	case 0:
94 		chrg_detect = &anatop->usb1_chrg_detect;
95 		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
96 		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
97 		break;
98 	case 1:
99 		chrg_detect = &anatop->usb2_chrg_detect;
100 		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
101 		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
102 		break;
103 	default:
104 		return;
105 	}
106 	/*
107 	 * Some phy and power's special controls
108 	 * 1. The external charger detector needs to be disabled
109 	 * or the signal at DP will be poor
110 	 * 2. The PLL's power and output to usb
111 	 * is totally controlled by IC, so the Software only needs
112 	 * to enable them at initializtion.
113 	 */
114 	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
115 		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
116 		     chrg_detect);
117 
118 	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
119 		     pll_480_ctrl_clr);
120 
121 	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
122 		     ANADIG_USB2_PLL_480_CTRL_POWER |
123 		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
124 		     pll_480_ctrl_set);
125 }
126 
127 /* Return 0 : host node, <>0 : device mode */
usb_phy_enable(int index,struct usb_ehci * ehci)128 static int usb_phy_enable(int index, struct usb_ehci *ehci)
129 {
130 	void __iomem *phy_reg;
131 	void __iomem *phy_ctrl;
132 	void __iomem *usb_cmd;
133 	int ret;
134 
135 	if (index >= ARRAY_SIZE(phy_bases))
136 		return 0;
137 
138 	phy_reg = (void __iomem *)phy_bases[index];
139 	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
140 	usb_cmd = (void __iomem *)&ehci->usbcmd;
141 
142 	/* Stop then Reset */
143 	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
144 	ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
145 	if (ret)
146 		return ret;
147 
148 	setbits_le32(usb_cmd, UCMD_RESET);
149 	ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
150 	if (ret)
151 		return ret;
152 
153 	/* Reset USBPHY module */
154 	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
155 	udelay(10);
156 
157 	/* Remove CLKGATE and SFTRST */
158 	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
159 	udelay(10);
160 
161 	/* Power up the PHY */
162 	writel(0, phy_reg + USBPHY_PWD);
163 	/* enable FS/LS device */
164 	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
165 			USBPHY_CTRL_ENUTMILEVEL3);
166 
167 	return 0;
168 }
169 
usb_phy_mode(int port)170 int usb_phy_mode(int port)
171 {
172 	void __iomem *phy_reg;
173 	void __iomem *phy_ctrl;
174 	u32 val;
175 
176 	phy_reg = (void __iomem *)phy_bases[port];
177 	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
178 
179 	val = readl(phy_ctrl);
180 
181 	if (val & USBPHY_CTRL_OTG_ID)
182 		return USB_INIT_DEVICE;
183 	else
184 		return USB_INIT_HOST;
185 }
186 
187 /* Base address for this IP block is 0x02184800 */
188 struct usbnc_regs {
189 	u32	ctrl[4];	/* otg/host1-3 */
190 	u32	uh2_hsic_ctrl;
191 	u32	uh3_hsic_ctrl;
192 	u32	otg_phy_ctrl_0;
193 	u32	uh1_phy_ctrl_0;
194 };
195 #elif defined(CONFIG_MX7)
196 struct usbnc_regs {
197 	u32 ctrl1;
198 	u32 ctrl2;
199 	u32 reserve1[10];
200 	u32 phy_cfg1;
201 	u32 phy_cfg2;
202 	u32 reserve2;
203 	u32 phy_status;
204 	u32 reserve3[4];
205 	u32 adp_cfg1;
206 	u32 adp_cfg2;
207 	u32 adp_status;
208 };
209 
usb_power_config(int index)210 static void usb_power_config(int index)
211 {
212 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
213 			(0x10000 * index) + USBNC_OFFSET);
214 	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
215 	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
216 
217 	/*
218 	 * Clear the ACAENB to enable usb_otg_id detection,
219 	 * otherwise it is the ACA detection enabled.
220 	 */
221 	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
222 
223 	/* Set power polarity to high active */
224 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
225 	setbits_le32(ctrl, UCTRL_PWR_POL);
226 #else
227 	clrbits_le32(ctrl, UCTRL_PWR_POL);
228 #endif
229 }
230 
usb_phy_mode(int port)231 int usb_phy_mode(int port)
232 {
233 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
234 			(0x10000 * port) + USBNC_OFFSET);
235 	void __iomem *status = (void __iomem *)(&usbnc->phy_status);
236 	u32 val;
237 
238 	val = readl(status);
239 
240 	if (val & USBNC_PHYSTATUS_ID_DIG)
241 		return USB_INIT_DEVICE;
242 	else
243 		return USB_INIT_HOST;
244 }
245 #endif
246 
usb_oc_config(int index)247 static void usb_oc_config(int index)
248 {
249 #if defined(CONFIG_MX6)
250 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
251 			USB_OTHERREGS_OFFSET);
252 	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
253 #elif defined(CONFIG_MX7)
254 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
255 			(0x10000 * index) + USBNC_OFFSET);
256 	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
257 #endif
258 
259 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
260 	/* mx6qarm2 seems to required a different setting*/
261 	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
262 #else
263 	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
264 #endif
265 
266 	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
267 }
268 
269 /**
270  * board_usb_phy_mode - override usb phy mode
271  * @port:	usb host/otg port
272  *
273  * Target board specific, override usb_phy_mode.
274  * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
275  * left disconnected in this case usb_phy_mode will not be able to identify
276  * the phy mode that usb port is used.
277  * Machine file overrides board_usb_phy_mode.
278  *
279  * Return: USB_INIT_DEVICE or USB_INIT_HOST
280  */
board_usb_phy_mode(int port)281 int __weak board_usb_phy_mode(int port)
282 {
283 	return usb_phy_mode(port);
284 }
285 
286 /**
287  * board_ehci_hcd_init - set usb vbus voltage
288  * @port:      usb otg port
289  *
290  * Target board specific, setup iomux pad to setup supply vbus voltage
291  * for usb otg port. Machine board file overrides board_ehci_hcd_init
292  *
293  * Return: 0 Success
294  */
board_ehci_hcd_init(int port)295 int __weak board_ehci_hcd_init(int port)
296 {
297 	return 0;
298 }
299 
300 /**
301  * board_ehci_power - enables/disables usb vbus voltage
302  * @port:      usb otg port
303  * @on:        on/off vbus voltage
304  *
305  * Enables/disables supply vbus voltage for usb otg port.
306  * Machine board file overrides board_ehci_power
307  *
308  * Return: 0 Success
309  */
board_ehci_power(int port,int on)310 int __weak board_ehci_power(int port, int on)
311 {
312 	return 0;
313 }
314 
ehci_mx6_common_init(struct usb_ehci * ehci,int index)315 int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
316 {
317 	int ret;
318 
319 	enable_usboh3_clk(1);
320 	mdelay(1);
321 
322 	/* Do board specific initialization */
323 	ret = board_ehci_hcd_init(index);
324 	if (ret)
325 		return ret;
326 
327 	usb_power_config(index);
328 	usb_oc_config(index);
329 
330 #if defined(CONFIG_MX6)
331 	usb_internal_phy_clock_gate(index, 1);
332 	usb_phy_enable(index, ehci);
333 #endif
334 
335 	return 0;
336 }
337 
338 #if !CONFIG_IS_ENABLED(DM_USB)
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)339 int ehci_hcd_init(int index, enum usb_init_type init,
340 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
341 {
342 	enum usb_init_type type;
343 #if defined(CONFIG_MX6)
344 	u32 controller_spacing = 0x200;
345 #elif defined(CONFIG_MX7)
346 	u32 controller_spacing = 0x10000;
347 #endif
348 	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
349 		(controller_spacing * index));
350 	int ret;
351 
352 	if (index > 3)
353 		return -EINVAL;
354 
355 	ret = ehci_mx6_common_init(ehci, index);
356 	if (ret)
357 		return ret;
358 
359 	type = board_usb_phy_mode(index);
360 
361 	if (hccr && hcor) {
362 		*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
363 		*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
364 				HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
365 	}
366 
367 	if ((type == init) || (type == USB_INIT_DEVICE))
368 		board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
369 	if (type != init)
370 		return -ENODEV;
371 	if (type == USB_INIT_DEVICE)
372 		return 0;
373 
374 	setbits_le32(&ehci->usbmode, CM_HOST);
375 	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
376 	setbits_le32(&ehci->portsc, USB_EN);
377 
378 	mdelay(10);
379 
380 	return 0;
381 }
382 
ehci_hcd_stop(int index)383 int ehci_hcd_stop(int index)
384 {
385 	return 0;
386 }
387 #else
388 struct ehci_mx6_priv_data {
389 	struct ehci_ctrl ctrl;
390 	struct usb_ehci *ehci;
391 	struct udevice *vbus_supply;
392 	enum usb_init_type init_type;
393 	int portnr;
394 };
395 
mx6_init_after_reset(struct ehci_ctrl * dev)396 static int mx6_init_after_reset(struct ehci_ctrl *dev)
397 {
398 	struct ehci_mx6_priv_data *priv = dev->priv;
399 	enum usb_init_type type = priv->init_type;
400 	struct usb_ehci *ehci = priv->ehci;
401 	int ret;
402 
403 	ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
404 	if (ret)
405 		return ret;
406 
407 #if CONFIG_IS_ENABLED(DM_REGULATOR)
408 	if (priv->vbus_supply) {
409 		ret = regulator_set_enable(priv->vbus_supply,
410 					   (type == USB_INIT_DEVICE) ?
411 					   false : true);
412 		if (ret) {
413 			puts("Error enabling VBUS supply\n");
414 			return ret;
415 		}
416 	}
417 #endif
418 
419 	if (type == USB_INIT_DEVICE)
420 		return 0;
421 
422 	setbits_le32(&ehci->usbmode, CM_HOST);
423 	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
424 	setbits_le32(&ehci->portsc, USB_EN);
425 
426 	mdelay(10);
427 
428 	return 0;
429 }
430 
431 static const struct ehci_ops mx6_ehci_ops = {
432 	.init_after_reset = mx6_init_after_reset
433 };
434 
ehci_usb_phy_mode(struct udevice * dev)435 static int ehci_usb_phy_mode(struct udevice *dev)
436 {
437 	struct usb_platdata *plat = dev_get_platdata(dev);
438 	void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
439 	void *__iomem phy_ctrl, *__iomem phy_status;
440 	const void *blob = gd->fdt_blob;
441 	int offset = dev_of_offset(dev), phy_off;
442 	u32 val;
443 
444 	/*
445 	 * About fsl,usbphy, Refer to
446 	 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
447 	 */
448 	if (is_mx6()) {
449 		phy_off = fdtdec_lookup_phandle(blob,
450 						offset,
451 						"fsl,usbphy");
452 		if (phy_off < 0)
453 			return -EINVAL;
454 
455 		addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
456 						       "reg");
457 		if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
458 			return -EINVAL;
459 
460 		phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
461 		val = readl(phy_ctrl);
462 
463 		if (val & USBPHY_CTRL_OTG_ID)
464 			plat->init_type = USB_INIT_DEVICE;
465 		else
466 			plat->init_type = USB_INIT_HOST;
467 	} else if (is_mx7()) {
468 		phy_status = (void __iomem *)(addr +
469 					      USBNC_PHY_STATUS_OFFSET);
470 		val = readl(phy_status);
471 
472 		if (val & USBNC_PHYSTATUS_ID_DIG)
473 			plat->init_type = USB_INIT_DEVICE;
474 		else
475 			plat->init_type = USB_INIT_HOST;
476 	} else {
477 		return -EINVAL;
478 	}
479 
480 	return 0;
481 }
482 
ehci_usb_ofdata_to_platdata(struct udevice * dev)483 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
484 {
485 	struct usb_platdata *plat = dev_get_platdata(dev);
486 	const char *mode;
487 
488 	mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
489 	if (mode) {
490 		if (strcmp(mode, "peripheral") == 0)
491 			plat->init_type = USB_INIT_DEVICE;
492 		else if (strcmp(mode, "host") == 0)
493 			plat->init_type = USB_INIT_HOST;
494 		else if (strcmp(mode, "otg") == 0)
495 			return ehci_usb_phy_mode(dev);
496 		else
497 			return -EINVAL;
498 
499 		return 0;
500 	}
501 
502 	return ehci_usb_phy_mode(dev);
503 }
504 
ehci_usb_probe(struct udevice * dev)505 static int ehci_usb_probe(struct udevice *dev)
506 {
507 	struct usb_platdata *plat = dev_get_platdata(dev);
508 	struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
509 	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
510 	enum usb_init_type type = plat->init_type;
511 	struct ehci_hccr *hccr;
512 	struct ehci_hcor *hcor;
513 	int ret;
514 
515 	priv->ehci = ehci;
516 	priv->portnr = dev->seq;
517 	priv->init_type = type;
518 
519 #if CONFIG_IS_ENABLED(DM_REGULATOR)
520 	ret = device_get_supply_regulator(dev, "vbus-supply",
521 					  &priv->vbus_supply);
522 	if (ret)
523 		debug("%s: No vbus supply\n", dev->name);
524 #endif
525 	ret = ehci_mx6_common_init(ehci, priv->portnr);
526 	if (ret)
527 		return ret;
528 
529 #if CONFIG_IS_ENABLED(DM_REGULATOR)
530 	if (priv->vbus_supply) {
531 		ret = regulator_set_enable(priv->vbus_supply,
532 					   (type == USB_INIT_DEVICE) ?
533 					   false : true);
534 		if (ret) {
535 			puts("Error enabling VBUS supply\n");
536 			return ret;
537 		}
538 	}
539 #endif
540 
541 	if (priv->init_type == USB_INIT_HOST) {
542 		setbits_le32(&ehci->usbmode, CM_HOST);
543 		writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
544 		setbits_le32(&ehci->portsc, USB_EN);
545 	}
546 
547 	mdelay(10);
548 
549 	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
550 	hcor = (struct ehci_hcor *)((uint32_t)hccr +
551 			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
552 
553 	return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
554 }
555 
556 static const struct udevice_id mx6_usb_ids[] = {
557 	{ .compatible = "fsl,imx27-usb" },
558 	{ }
559 };
560 
561 U_BOOT_DRIVER(usb_mx6) = {
562 	.name	= "ehci_mx6",
563 	.id	= UCLASS_USB,
564 	.of_match = mx6_usb_ids,
565 	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
566 	.probe	= ehci_usb_probe,
567 	.remove = ehci_deregister,
568 	.ops	= &ehci_usb_ops,
569 	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
570 	.priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
571 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
572 };
573 #endif
574