1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Register definition for Atmel USBA high speed USB device controller
4 * [Original from Linux kernel: drivers/usb/gadget/atmel_usba_udc.h]
5 *
6 * Copyright (C) 2005-2013 Atmel Corporation
7 * Bo Shen <voice.shen@atmel.com>
8 */
9
10 #ifndef __LINUX_USB_GADGET_USBA_UDC_H__
11 #define __LINUX_USB_GADGET_USBA_UDC_H__
12
13 /* USB register offsets */
14 #define USBA_CTRL 0x0000
15 #define USBA_FNUM 0x0004
16 #define USBA_INT_ENB 0x0010
17 #define USBA_INT_STA 0x0014
18 #define USBA_INT_CLR 0x0018
19 #define USBA_EPT_RST 0x001c
20 #define USBA_TST 0x00e0
21
22 /* USB endpoint register offsets */
23 #define USBA_EPT_CFG 0x0000
24 #define USBA_EPT_CTL_ENB 0x0004
25 #define USBA_EPT_CTL_DIS 0x0008
26 #define USBA_EPT_CTL 0x000c
27 #define USBA_EPT_SET_STA 0x0014
28 #define USBA_EPT_CLR_STA 0x0018
29 #define USBA_EPT_STA 0x001c
30
31 /* USB DMA register offsets */
32 #define USBA_DMA_NXT_DSC 0x0000
33 #define USBA_DMA_ADDRESS 0x0004
34 #define USBA_DMA_CONTROL 0x0008
35 #define USBA_DMA_STATUS 0x000c
36
37 /* Bitfields in CTRL */
38 #define USBA_DEV_ADDR_OFFSET 0
39 #define USBA_DEV_ADDR_SIZE 7
40 #define USBA_FADDR_EN (1 << 7)
41 #define USBA_EN_USBA (1 << 8)
42 #define USBA_DETACH (1 << 9)
43 #define USBA_REMOTE_WAKE_UP (1 << 10)
44 #define USBA_PULLD_DIS (1 << 11)
45
46 #define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
47 #define USBA_DISABLE_MASK USBA_DETACH
48
49 /* Bitfields in FNUM */
50 #define USBA_MICRO_FRAME_NUM_OFFSET 0
51 #define USBA_MICRO_FRAME_NUM_SIZE 3
52 #define USBA_FRAME_NUMBER_OFFSET 3
53 #define USBA_FRAME_NUMBER_SIZE 11
54 #define USBA_FRAME_NUM_ERROR (1 << 31)
55
56 /* Bitfields in INT_ENB/INT_STA/INT_CLR */
57 #define USBA_HIGH_SPEED (1 << 0)
58 #define USBA_DET_SUSPEND (1 << 1)
59 #define USBA_MICRO_SOF (1 << 2)
60 #define USBA_SOF (1 << 3)
61 #define USBA_END_OF_RESET (1 << 4)
62 #define USBA_WAKE_UP (1 << 5)
63 #define USBA_END_OF_RESUME (1 << 6)
64 #define USBA_UPSTREAM_RESUME (1 << 7)
65 #define USBA_EPT_INT_OFFSET 8
66 #define USBA_EPT_INT_SIZE 16
67 #define USBA_DMA_INT_OFFSET 24
68 #define USBA_DMA_INT_SIZE 8
69
70 /* Bitfields in EPT_RST */
71 #define USBA_RST_OFFSET 0
72 #define USBA_RST_SIZE 16
73
74 /* Bitfields in USBA_TST */
75 #define USBA_SPEED_CFG_OFFSET 0
76 #define USBA_SPEED_CFG_SIZE 2
77 #define USBA_TST_J_MODE (1 << 2)
78 #define USBA_TST_K_MODE (1 << 3)
79 #define USBA_TST_PKT_MODE (1 << 4)
80 #define USBA_OPMODE2 (1 << 5)
81
82 /* Bitfields in EPT_CFG */
83 #define USBA_EPT_SIZE_OFFSET 0
84 #define USBA_EPT_SIZE_SIZE 3
85 #define USBA_EPT_DIR_IN (1 << 3)
86 #define USBA_EPT_TYPE_OFFSET 4
87 #define USBA_EPT_TYPE_SIZE 2
88 #define USBA_BK_NUMBER_OFFSET 6
89 #define USBA_BK_NUMBER_SIZE 2
90 #define USBA_NB_TRANS_OFFSET 8
91 #define USBA_NB_TRANS_SIZE 2
92 #define USBA_EPT_MAPPED (1 << 31)
93
94 /* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
95 #define USBA_EPT_ENABLE (1 << 0)
96 #define USBA_AUTO_VALID (1 << 1)
97 #define USBA_INTDIS_DMA (1 << 3)
98 #define USBA_NYET_DIS (1 << 4)
99 #define USBA_DATAX_RX (1 << 6)
100 #define USBA_MDATA_RX (1 << 7)
101 /* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
102 #define USBA_BUSY_BANK_IE (1 << 18)
103
104 /* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
105 #define USBA_FORCE_STALL (1 << 5)
106 #define USBA_TOGGLE_CLR (1 << 6)
107 #define USBA_TOGGLE_SEQ_OFFSET 6
108 #define USBA_TOGGLE_SEQ_SIZE 2
109 #define USBA_ERR_OVFLW (1 << 8)
110 #define USBA_RX_BK_RDY (1 << 9)
111 #define USBA_KILL_BANK (1 << 9)
112 #define USBA_TX_COMPLETE (1 << 10)
113 #define USBA_TX_PK_RDY (1 << 11)
114 #define USBA_ISO_ERR_TRANS (1 << 11)
115 #define USBA_RX_SETUP (1 << 12)
116 #define USBA_ISO_ERR_FLOW (1 << 12)
117 #define USBA_STALL_SENT (1 << 13)
118 #define USBA_ISO_ERR_CRC (1 << 13)
119 #define USBA_ISO_ERR_NBTRANS (1 << 13)
120 #define USBA_NAK_IN (1 << 14)
121 #define USBA_ISO_ERR_FLUSH (1 << 14)
122 #define USBA_NAK_OUT (1 << 15)
123 #define USBA_CURRENT_BANK_OFFSET 16
124 #define USBA_CURRENT_BANK_SIZE 2
125 #define USBA_BUSY_BANKS_OFFSET 18
126 #define USBA_BUSY_BANKS_SIZE 2
127 #define USBA_BYTE_COUNT_OFFSET 20
128 #define USBA_BYTE_COUNT_SIZE 11
129 #define USBA_SHORT_PACKET (1 << 31)
130
131 /* Bitfields in DMA_CONTROL */
132 #define USBA_DMA_CH_EN (1 << 0)
133 #define USBA_DMA_LINK (1 << 1)
134 #define USBA_DMA_END_TR_EN (1 << 2)
135 #define USBA_DMA_END_BUF_EN (1 << 3)
136 #define USBA_DMA_END_TR_IE (1 << 4)
137 #define USBA_DMA_END_BUF_IE (1 << 5)
138 #define USBA_DMA_DESC_LOAD_IE (1 << 6)
139 #define USBA_DMA_BURST_LOCK (1 << 7)
140 #define USBA_DMA_BUF_LEN_OFFSET 16
141 #define USBA_DMA_BUF_LEN_SIZE 16
142
143 /* Bitfields in DMA_STATUS */
144 #define USBA_DMA_CH_ACTIVE (1 << 1)
145 #define USBA_DMA_END_TR_ST (1 << 4)
146 #define USBA_DMA_END_BUF_ST (1 << 5)
147 #define USBA_DMA_DESC_LOAD_ST (1 << 6)
148
149 /* Constants for SPEED_CFG */
150 #define USBA_SPEED_CFG_NORMAL 0
151 #define USBA_SPEED_CFG_FORCE_HIGH 2
152 #define USBA_SPEED_CFG_FORCE_FULL 3
153
154 /* Constants for EPT_SIZE */
155 #define USBA_EPT_SIZE_8 0
156 #define USBA_EPT_SIZE_16 1
157 #define USBA_EPT_SIZE_32 2
158 #define USBA_EPT_SIZE_64 3
159 #define USBA_EPT_SIZE_128 4
160 #define USBA_EPT_SIZE_256 5
161 #define USBA_EPT_SIZE_512 6
162 #define USBA_EPT_SIZE_1024 7
163
164 /* Constants for EPT_TYPE */
165 #define USBA_EPT_TYPE_CONTROL 0
166 #define USBA_EPT_TYPE_ISO 1
167 #define USBA_EPT_TYPE_BULK 2
168 #define USBA_EPT_TYPE_INT 3
169
170 /* Constants for BK_NUMBER */
171 #define USBA_BK_NUMBER_ZERO 0
172 #define USBA_BK_NUMBER_ONE 1
173 #define USBA_BK_NUMBER_DOUBLE 2
174 #define USBA_BK_NUMBER_TRIPLE 3
175
176 /* Bit manipulation macros */
177 #define USBA_BF(name, value) \
178 (((value) & ((1 << USBA_##name##_SIZE) - 1)) \
179 << USBA_##name##_OFFSET)
180 #define USBA_BFEXT(name, value) \
181 (((value) >> USBA_##name##_OFFSET) \
182 & ((1 << USBA_##name##_SIZE) - 1))
183 #define USBA_BFINS(name, value, old) \
184 (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
185 << USBA_##name##_OFFSET)) \
186 | USBA_BF(name, value))
187
188 /* Register access macros */
189 #define usba_readl(udc, reg) \
190 __raw_readl((udc)->regs + USBA_##reg)
191 #define usba_writel(udc, reg, value) \
192 __raw_writel((value), (udc)->regs + USBA_##reg)
193 #define usba_ep_readl(ep, reg) \
194 __raw_readl((ep)->ep_regs + USBA_EPT_##reg)
195 #define usba_ep_writel(ep, reg, value) \
196 __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
197 #define usba_dma_readl(ep, reg) \
198 __raw_readl((ep)->dma_regs + USBA_DMA_##reg)
199 #define usba_dma_writel(ep, reg, value) \
200 __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
201
202 /* Calculate base address for a given endpoint or DMA controller */
203 #define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
204 #define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
205 #define USBA_FIFO_BASE(x) ((x) << 16)
206
207 /* Synth parameters */
208 #define USBA_NR_ENDPOINTS 7
209
210 #define EP0_FIFO_SIZE 64
211 #define EP0_EPT_SIZE USBA_EPT_SIZE_64
212 #define EP0_NR_BANKS 1
213
214 #define DBG_ERR 0x0001 /* report all error returns */
215 #define DBG_HW 0x0002 /* debug hardware initialization */
216 #define DBG_GADGET 0x0004 /* calls to/from gadget driver */
217 #define DBG_INT 0x0008 /* interrupts */
218 #define DBG_BUS 0x0010 /* report changes in bus state */
219 #define DBG_QUEUE 0x0020 /* debug request queue processing */
220 #define DBG_FIFO 0x0040 /* debug FIFO contents */
221 #define DBG_DMA 0x0080 /* debug DMA handling */
222 #define DBG_REQ 0x0100 /* print out queued request length */
223 #define DBG_ALL 0xffff
224 #define DBG_NONE 0x0000
225
226 #define DEBUG_LEVEL (DBG_ERR)
227
228 #define DBG(level, fmt, ...) \
229 do { \
230 if ((level) & DEBUG_LEVEL) \
231 debug("udc: " fmt, ## __VA_ARGS__); \
232 } while (0)
233
234 enum usba_ctrl_state {
235 WAIT_FOR_SETUP,
236 DATA_STAGE_IN,
237 DATA_STAGE_OUT,
238 STATUS_STAGE_IN,
239 STATUS_STAGE_OUT,
240 STATUS_STAGE_ADDR,
241 STATUS_STAGE_TEST,
242 };
243
244 struct usba_dma_desc {
245 dma_addr_t next;
246 dma_addr_t addr;
247 u32 ctrl;
248 };
249
250 struct usba_ep {
251 int state;
252 void *ep_regs;
253 void *dma_regs;
254 void *fifo;
255 struct usb_ep ep;
256 struct usba_udc *udc;
257
258 struct list_head queue;
259
260 u16 fifo_size;
261 u8 nr_banks;
262 u8 index;
263 unsigned int can_dma:1;
264 unsigned int can_isoc:1;
265 unsigned int is_isoc:1;
266 unsigned int is_in:1;
267
268 const struct usb_endpoint_descriptor *desc;
269 };
270
271 struct usba_request {
272 struct usb_request req;
273 struct list_head queue;
274
275 u32 ctrl;
276
277 unsigned int submitted:1;
278 unsigned int last_transaction:1;
279 unsigned int using_dma:1;
280 unsigned int mapped:1;
281 };
282
283 struct usba_udc {
284 void *regs;
285 void *fifo;
286
287 struct usb_gadget gadget;
288 struct usb_gadget_driver *driver;
289 struct platform_device *pdev;
290 int irq;
291 int vbus_pin;
292 int vbus_pin_inverted;
293 int num_ep;
294 struct usba_ep *usba_ep;
295
296 u16 devstatus;
297
298 u16 test_mode;
299 int vbus_prev;
300 };
301
to_usba_ep(struct usb_ep * ep)302 static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
303 {
304 return container_of(ep, struct usba_ep, ep);
305 }
306
to_usba_req(struct usb_request * req)307 static inline struct usba_request *to_usba_req(struct usb_request *req)
308 {
309 return container_of(req, struct usba_request, req);
310 }
311
to_usba_udc(struct usb_gadget * gadget)312 static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
313 {
314 return container_of(gadget, struct usba_udc, gadget);
315 }
316
317 #define ep_is_control(ep) ((ep)->index == 0)
318 #define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
319
320 #endif /* __LINUX_USB_GADGET_USBA_UDC_H */
321