1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 */
6
7 #ifndef __PINCTRL_UNIPHIER_H__
8 #define __PINCTRL_UNIPHIER_H__
9
10 #include <linux/bitops.h>
11 #include <linux/build_bug.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14
15 /* drive strength control register number */
16 #define UNIPHIER_PIN_DRVCTRL_SHIFT 0
17 #define UNIPHIER_PIN_DRVCTRL_BITS 9
18 #define UNIPHIER_PIN_DRVCTRL_MASK ((1U << (UNIPHIER_PIN_DRVCTRL_BITS)) \
19 - 1)
20
21 /* drive control type */
22 #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
23 (UNIPHIER_PIN_DRVCTRL_BITS))
24 #define UNIPHIER_PIN_DRV_TYPE_BITS 2
25 #define UNIPHIER_PIN_DRV_TYPE_MASK ((1U << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
26 - 1)
27
28 /* drive control type */
29 enum uniphier_pin_drv_type {
30 UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
31 UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
32 UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
33 };
34
35 #define UNIPHIER_PIN_DRVCTRL(x) \
36 (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
37 #define UNIPHIER_PIN_DRV_TYPE(x) \
38 (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
39
40 #define UNIPHIER_PIN_ATTR_PACKED(drvctrl, drv_type) \
41 UNIPHIER_PIN_DRVCTRL(drvctrl) | \
42 UNIPHIER_PIN_DRV_TYPE(drv_type)
43
uniphier_pin_get_drvctrl(unsigned int data)44 static inline unsigned int uniphier_pin_get_drvctrl(unsigned int data)
45 {
46 return (data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & UNIPHIER_PIN_DRVCTRL_MASK;
47 }
48
uniphier_pin_get_drv_type(unsigned int data)49 static inline unsigned int uniphier_pin_get_drv_type(unsigned int data)
50 {
51 return (data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
52 UNIPHIER_PIN_DRV_TYPE_MASK;
53 }
54
55 /**
56 * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
57 *
58 * @number: pin number
59 * @data: additional per-pin data
60 */
61 struct uniphier_pinctrl_pin {
62 unsigned number;
63 const char *name;
64 unsigned int data;
65 };
66
67 /**
68 * struct uniphier_pinctrl_group - pin group data for UniPhier SoC
69 *
70 * @name: pin group name
71 * @pins: array of pins that belong to the group
72 * @num_pins: number of pins in the group
73 * @muxvals: array of values to be set to pinmux registers
74 */
75 struct uniphier_pinctrl_group {
76 const char *name;
77 const unsigned *pins;
78 unsigned num_pins;
79 const int *muxvals;
80 };
81
82 /**
83 * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller
84 *
85 * @pins: array of pin data
86 * @pins_count: number of pin data
87 * @groups: array of pin group data
88 * @groups_count: number of pin group data
89 * @functions: array of pinmux function names
90 * @functions_count: number of pinmux functions
91 * @mux_bits: bit width of each pinmux register
92 * @reg_stride: stride of pinmux register address
93 * @caps: SoC-specific capability flag
94 */
95 struct uniphier_pinctrl_socdata {
96 const struct uniphier_pinctrl_pin *pins;
97 int pins_count;
98 const struct uniphier_pinctrl_group *groups;
99 int groups_count;
100 const char * const *functions;
101 int functions_count;
102 unsigned caps;
103 #define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE BIT(3)
104 #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
105 #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
106 #define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
107 };
108
109 #define UNIPHIER_PINCTRL_PIN(a, b, c, d) \
110 { \
111 .number = a, \
112 .name = b, \
113 .data = UNIPHIER_PIN_ATTR_PACKED(c, d), \
114 }
115
116 #define __UNIPHIER_PINCTRL_GROUP(grp) \
117 { \
118 .name = #grp, \
119 .pins = grp##_pins, \
120 .num_pins = ARRAY_SIZE(grp##_pins), \
121 .muxvals = grp##_muxvals + \
122 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
123 ARRAY_SIZE(grp##_muxvals)), \
124 }
125
126 #define __UNIPHIER_PINMUX_FUNCTION(func) #func
127
128 #ifdef CONFIG_SPL_BUILD
129 /*
130 * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
131 * suppressing "defined but not used" warnings.
132 */
133 #define UNIPHIER_PINCTRL_GROUP(grp) \
134 { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
135 #define UNIPHIER_PINMUX_FUNCTION(func) NULL
136 #else
137 #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp)
138 #define UNIPHIER_PINMUX_FUNCTION(func) __UNIPHIER_PINMUX_FUNCTION(func)
139 #endif
140
141 #define UNIPHIER_PINCTRL_GROUP_SPL(grp) __UNIPHIER_PINCTRL_GROUP(grp)
142 #define UNIPHIER_PINMUX_FUNCTION_SPL(func) __UNIPHIER_PINMUX_FUNCTION(func)
143
144 /**
145 * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
146 *
147 * @base: base address of the pinctrl device
148 * @socdata: SoC specific data
149 */
150 struct uniphier_pinctrl_priv {
151 void __iomem *base;
152 struct uniphier_pinctrl_socdata *socdata;
153 };
154
155 extern const struct pinctrl_ops uniphier_pinctrl_ops;
156
157 int uniphier_pinctrl_probe(struct udevice *dev,
158 struct uniphier_pinctrl_socdata *socdata);
159
160 #endif /* __PINCTRL_UNIPHIER_H__ */
161