xref: /openbmc/linux/drivers/ufs/host/ufs-qcom.h (revision 8f01dda1)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef UFS_QCOM_H_
6 #define UFS_QCOM_H_
7 
8 #include <linux/reset-controller.h>
9 #include <linux/reset.h>
10 #include <soc/qcom/ice.h>
11 #include <ufs/ufshcd.h>
12 
13 #define MAX_UFS_QCOM_HOSTS	1
14 #define MAX_U32                 (~(u32)0)
15 #define MPHY_TX_FSM_STATE       0x41
16 #define TX_FSM_HIBERN8          0x1
17 #define HBRN8_POLL_TOUT_MS      100
18 #define DEFAULT_CLK_RATE_HZ     1000000
19 #define BUS_VECTOR_NAME_LEN     32
20 #define MAX_SUPP_MAC		64
21 
22 #define UFS_HW_VER_MAJOR_MASK	GENMASK(31, 28)
23 #define UFS_HW_VER_MINOR_MASK	GENMASK(27, 16)
24 #define UFS_HW_VER_STEP_MASK	GENMASK(15, 0)
25 
26 /* vendor specific pre-defined parameters */
27 #define SLOW 1
28 #define FAST 2
29 
30 #define UFS_QCOM_LIMIT_HS_RATE		PA_HS_MODE_B
31 
32 /* QCOM UFS host controller vendor specific registers */
33 enum {
34 	REG_UFS_SYS1CLK_1US                 = 0xC0,
35 	REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
36 	REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
37 	REG_UFS_PA_ERR_CODE                 = 0xCC,
38 	/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
39 	REG_UFS_PARAM0                      = 0xD0,
40 	/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
41 	REG_UFS_CFG0                        = 0xD8,
42 	REG_UFS_CFG1                        = 0xDC,
43 	REG_UFS_CFG2                        = 0xE0,
44 	REG_UFS_HW_VERSION                  = 0xE4,
45 
46 	UFS_TEST_BUS				= 0xE8,
47 	UFS_TEST_BUS_CTRL_0			= 0xEC,
48 	UFS_TEST_BUS_CTRL_1			= 0xF0,
49 	UFS_TEST_BUS_CTRL_2			= 0xF4,
50 	UFS_UNIPRO_CFG				= 0xF8,
51 
52 	/*
53 	 * QCOM UFS host controller vendor specific registers
54 	 * added in HW Version 3.0.0
55 	 */
56 	UFS_AH8_CFG				= 0xFC,
57 
58 	REG_UFS_CFG3				= 0x271C,
59 };
60 
61 /* QCOM UFS host controller vendor specific debug registers */
62 enum {
63 	UFS_DBG_RD_REG_UAWM			= 0x100,
64 	UFS_DBG_RD_REG_UARM			= 0x200,
65 	UFS_DBG_RD_REG_TXUC			= 0x300,
66 	UFS_DBG_RD_REG_RXUC			= 0x400,
67 	UFS_DBG_RD_REG_DFC			= 0x500,
68 	UFS_DBG_RD_REG_TRLUT			= 0x600,
69 	UFS_DBG_RD_REG_TMRLUT			= 0x700,
70 	UFS_UFS_DBG_RD_REG_OCSC			= 0x800,
71 
72 	UFS_UFS_DBG_RD_DESC_RAM			= 0x1500,
73 	UFS_UFS_DBG_RD_PRDT_RAM			= 0x1700,
74 	UFS_UFS_DBG_RD_RESP_RAM			= 0x1800,
75 	UFS_UFS_DBG_RD_EDTL_RAM			= 0x1900,
76 };
77 
78 enum {
79 	UFS_MEM_CQIS_VS		= 0x8,
80 };
81 
82 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)	(0x000 + x)
83 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
84 
85 /* bit definitions for REG_UFS_CFG0 register */
86 #define QUNIPRO_G4_SEL		BIT(5)
87 
88 /* bit definitions for REG_UFS_CFG1 register */
89 #define QUNIPRO_SEL		BIT(0)
90 #define UFS_PHY_SOFT_RESET	BIT(1)
91 #define UTP_DBG_RAMS_EN		BIT(17)
92 #define TEST_BUS_EN		BIT(18)
93 #define TEST_BUS_SEL		GENMASK(22, 19)
94 #define UFS_REG_TEST_BUS_EN	BIT(30)
95 
96 #define UFS_PHY_RESET_ENABLE	1
97 #define UFS_PHY_RESET_DISABLE	0
98 
99 /* bit definitions for REG_UFS_CFG2 register */
100 #define UAWM_HW_CGC_EN		BIT(0)
101 #define UARM_HW_CGC_EN		BIT(1)
102 #define TXUC_HW_CGC_EN		BIT(2)
103 #define RXUC_HW_CGC_EN		BIT(3)
104 #define DFC_HW_CGC_EN		BIT(4)
105 #define TRLUT_HW_CGC_EN		BIT(5)
106 #define TMRLUT_HW_CGC_EN	BIT(6)
107 #define OCSC_HW_CGC_EN		BIT(7)
108 
109 /* bit definitions for REG_UFS_PARAM0 */
110 #define MAX_HS_GEAR_MASK	GENMASK(6, 4)
111 #define UFS_QCOM_MAX_GEAR(x)	FIELD_GET(MAX_HS_GEAR_MASK, (x))
112 
113 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
114 #define TEST_BUS_SUB_SEL_MASK	GENMASK(4, 0)  /* All XXX_SEL fields are 5 bits wide */
115 
116 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
117 				 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
118 				 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
119 				 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
120 
121 /* bit offset */
122 #define OFFSET_CLK_NS_REG		0xa
123 
124 /* bit masks */
125 #define MASK_TX_SYMBOL_CLK_1US_REG	GENMASK(9, 0)
126 #define MASK_CLK_NS_REG			GENMASK(23, 10)
127 
128 /* QUniPro Vendor specific attributes */
129 #define PA_VS_CONFIG_REG1	0x9000
130 #define DME_VS_CORE_CLK_CTRL	0xD002
131 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
132 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT		BIT(8)
133 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK	0xFF
134 
135 static inline void
ufs_qcom_get_controller_revision(struct ufs_hba * hba,u8 * major,u16 * minor,u16 * step)136 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
137 				 u8 *major, u16 *minor, u16 *step)
138 {
139 	u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
140 
141 	*major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
142 	*minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
143 	*step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
144 };
145 
ufs_qcom_assert_reset(struct ufs_hba * hba)146 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
147 {
148 	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
149 		    REG_UFS_CFG1);
150 
151 	/*
152 	 * Dummy read to ensure the write takes effect before doing any sort
153 	 * of delay
154 	 */
155 	ufshcd_readl(hba, REG_UFS_CFG1);
156 }
157 
ufs_qcom_deassert_reset(struct ufs_hba * hba)158 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
159 {
160 	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
161 		    REG_UFS_CFG1);
162 
163 	/*
164 	 * Dummy read to ensure the write takes effect before doing any sort
165 	 * of delay
166 	 */
167 	ufshcd_readl(hba, REG_UFS_CFG1);
168 }
169 
170 /* Host controller hardware version: major.minor.step */
171 struct ufs_hw_version {
172 	u16 step;
173 	u16 minor;
174 	u8 major;
175 };
176 
177 struct ufs_qcom_testbus {
178 	u8 select_major;
179 	u8 select_minor;
180 };
181 
182 struct gpio_desc;
183 
184 struct ufs_qcom_host {
185 	/*
186 	 * Set this capability if host controller supports the QUniPro mode
187 	 * and if driver wants the Host controller to operate in QUniPro mode.
188 	 * Note: By default this capability will be kept enabled if host
189 	 * controller supports the QUniPro mode.
190 	 */
191 	#define UFS_QCOM_CAP_QUNIPRO	0x1
192 
193 	/*
194 	 * Set this capability if host controller can retain the secure
195 	 * configuration even after UFS controller core power collapse.
196 	 */
197 	#define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE	0x2
198 	u32 caps;
199 
200 	struct phy *generic_phy;
201 	struct ufs_hba *hba;
202 	struct ufs_pa_layer_attr dev_req_params;
203 	struct clk *rx_l0_sync_clk;
204 	struct clk *tx_l0_sync_clk;
205 	struct clk *rx_l1_sync_clk;
206 	struct clk *tx_l1_sync_clk;
207 	bool is_lane_clks_enabled;
208 
209 	struct icc_path *icc_ddr;
210 	struct icc_path *icc_cpu;
211 
212 #ifdef CONFIG_SCSI_UFS_CRYPTO
213 	struct qcom_ice *ice;
214 #endif
215 
216 	void __iomem *dev_ref_clk_ctrl_mmio;
217 	bool is_dev_ref_clk_enabled;
218 	struct ufs_hw_version hw_ver;
219 
220 	u32 dev_ref_clk_en_mask;
221 
222 	struct ufs_qcom_testbus testbus;
223 
224 	/* Reset control of HCI */
225 	struct reset_control *core_reset;
226 	struct reset_controller_dev rcdev;
227 
228 	struct gpio_desc *device_reset;
229 
230 	u32 hs_gear;
231 
232 	bool esi_enabled;
233 };
234 
235 static inline u32
ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host * host,u32 reg)236 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
237 {
238 	if (host->hw_ver.major <= 0x02)
239 		return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
240 
241 	return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
242 };
243 
244 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
245 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
246 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
247 
248 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
249 
ufs_qcom_cap_qunipro(struct ufs_qcom_host * host)250 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
251 {
252 	return host->caps & UFS_QCOM_CAP_QUNIPRO;
253 }
254 
255 #endif /* UFS_QCOM_H_ */
256