1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/io.h>
29 #include <linux/iopoll.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/dma/imx-dma.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
123 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
124 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
127 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
128 #define USR1_RTSS (1<<14) /* RTS pin status */
129 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
130 #define USR1_RTSD (1<<12) /* RTS delta */
131 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
132 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
133 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
134 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
135 #define USR1_DTRD (1<<7) /* DTR Delta */
136 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
137 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
138 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
139 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
140 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
141 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
142 #define USR2_IDLE (1<<12) /* Idle condition */
143 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
144 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
145 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
146 #define USR2_WAKE (1<<7) /* Wake */
147 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
148 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
149 #define USR2_TXDC (1<<3) /* Transmitter complete */
150 #define USR2_BRCD (1<<2) /* Break condition */
151 #define USR2_ORE (1<<1) /* Overrun error */
152 #define USR2_RDR (1<<0) /* Recv data ready */
153 #define UTS_FRCPERR (1<<13) /* Force parity error */
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
155 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
156 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
157 #define UTS_TXFULL (1<<4) /* TxFIFO full */
158 #define UTS_RXFULL (1<<3) /* RxFIFO full */
159 #define UTS_SOFTRST (1<<0) /* Software reset */
160
161 /* We've been assigned a range on the "Low-density serial ports" major */
162 #define SERIAL_IMX_MAJOR 207
163 #define MINOR_START 16
164 #define DEV_NAME "ttymxc"
165
166 /*
167 * This determines how often we check the modem status signals
168 * for any change. They generally aren't connected to an IRQ
169 * so we have to poll them. We also check immediately before
170 * filling the TX fifo incase CTS has been dropped.
171 */
172 #define MCTRL_TIMEOUT (250*HZ/1000)
173
174 #define DRIVER_NAME "IMX-uart"
175
176 #define UART_NR 8
177
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
179 enum imx_uart_type {
180 IMX1_UART,
181 IMX21_UART,
182 IMX53_UART,
183 IMX6Q_UART,
184 };
185
186 /* device type dependent stuff */
187 struct imx_uart_data {
188 unsigned uts_reg;
189 enum imx_uart_type devtype;
190 };
191
192 enum imx_tx_state {
193 OFF,
194 WAIT_AFTER_RTS,
195 SEND,
196 WAIT_AFTER_SEND,
197 };
198
199 struct imx_port {
200 struct uart_port port;
201 struct timer_list timer;
202 unsigned int old_status;
203 unsigned int have_rtscts:1;
204 unsigned int have_rtsgpio:1;
205 unsigned int dte_mode:1;
206 unsigned int inverted_tx:1;
207 unsigned int inverted_rx:1;
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211
212 struct mctrl_gpios *gpios;
213
214 /* counter to stop 0xff flood */
215 int idle_counter;
216
217 /* DMA fields */
218 unsigned int dma_is_enabled:1;
219 unsigned int dma_is_rxing:1;
220 unsigned int dma_is_txing:1;
221 struct dma_chan *dma_chan_rx, *dma_chan_tx;
222 struct scatterlist rx_sgl, tx_sgl[2];
223 void *rx_buf;
224 struct circ_buf rx_ring;
225 unsigned int rx_buf_size;
226 unsigned int rx_period_length;
227 unsigned int rx_periods;
228 dma_cookie_t rx_cookie;
229 unsigned int tx_bytes;
230 unsigned int dma_tx_nents;
231 unsigned int saved_reg[10];
232 bool context_saved;
233
234 enum imx_tx_state tx_state;
235 struct hrtimer trigger_start_tx;
236 struct hrtimer trigger_stop_tx;
237 };
238
239 struct imx_port_ucrs {
240 unsigned int ucr1;
241 unsigned int ucr2;
242 unsigned int ucr3;
243 };
244
245 static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
254 [IMX53_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX53_UART,
257 },
258 [IMX6Q_UART] = {
259 .uts_reg = IMX21_UTS,
260 .devtype = IMX6Q_UART,
261 },
262 };
263
264 static const struct of_device_id imx_uart_dt_ids[] = {
265 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
266 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
267 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
268 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
269 { /* sentinel */ }
270 };
271 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
272
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)273 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
274 {
275 writel(val, sport->port.membase + offset);
276 }
277
imx_uart_readl(struct imx_port * sport,u32 offset)278 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
279 {
280 return readl(sport->port.membase + offset);
281 }
282
imx_uart_uts_reg(struct imx_port * sport)283 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
284 {
285 return sport->devdata->uts_reg;
286 }
287
imx_uart_is_imx1(struct imx_port * sport)288 static inline int imx_uart_is_imx1(struct imx_port *sport)
289 {
290 return sport->devdata->devtype == IMX1_UART;
291 }
292
293 /*
294 * Save and restore functions for UCR1, UCR2 and UCR3 registers
295 */
296 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)297 static void imx_uart_ucrs_save(struct imx_port *sport,
298 struct imx_port_ucrs *ucr)
299 {
300 /* save control registers */
301 ucr->ucr1 = imx_uart_readl(sport, UCR1);
302 ucr->ucr2 = imx_uart_readl(sport, UCR2);
303 ucr->ucr3 = imx_uart_readl(sport, UCR3);
304 }
305
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)306 static void imx_uart_ucrs_restore(struct imx_port *sport,
307 struct imx_port_ucrs *ucr)
308 {
309 /* restore control registers */
310 imx_uart_writel(sport, ucr->ucr1, UCR1);
311 imx_uart_writel(sport, ucr->ucr2, UCR2);
312 imx_uart_writel(sport, ucr->ucr3, UCR3);
313 }
314 #endif
315
316 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)317 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
318 {
319 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
320
321 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
322 }
323
324 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)325 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
326 {
327 *ucr2 &= ~UCR2_CTSC;
328 *ucr2 |= UCR2_CTS;
329
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
331 }
332
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)333 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
334 {
335 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
336 }
337
338 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)339 static void imx_uart_soft_reset(struct imx_port *sport)
340 {
341 int i = 10;
342 u32 ucr2, ubir, ubmr, uts;
343
344 /*
345 * According to the Reference Manual description of the UART SRST bit:
346 *
347 * "Reset the transmit and receive state machines,
348 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
349 * and UTS[6-3]".
350 *
351 * We don't need to restore the old values from USR1, USR2, URXD and
352 * UTXD. UBRC is read only, so only save/restore the other three
353 * registers.
354 */
355 ubir = imx_uart_readl(sport, UBIR);
356 ubmr = imx_uart_readl(sport, UBMR);
357 uts = imx_uart_readl(sport, IMX21_UTS);
358
359 ucr2 = imx_uart_readl(sport, UCR2);
360 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
361
362 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
363 udelay(1);
364
365 /* Restore the registers */
366 imx_uart_writel(sport, ubir, UBIR);
367 imx_uart_writel(sport, ubmr, UBMR);
368 imx_uart_writel(sport, uts, IMX21_UTS);
369
370 sport->idle_counter = 0;
371 }
372
imx_uart_disable_loopback_rs485(struct imx_port * sport)373 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
374 {
375 unsigned int uts;
376
377 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
378 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
379 uts &= ~UTS_LOOP;
380 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
381 }
382
383 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)384 static void imx_uart_start_rx(struct uart_port *port)
385 {
386 struct imx_port *sport = (struct imx_port *)port;
387 unsigned int ucr1, ucr2;
388
389 ucr1 = imx_uart_readl(sport, UCR1);
390 ucr2 = imx_uart_readl(sport, UCR2);
391
392 ucr2 |= UCR2_RXEN;
393
394 if (sport->dma_is_enabled) {
395 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
396 } else {
397 ucr1 |= UCR1_RRDYEN;
398 ucr2 |= UCR2_ATEN;
399 }
400
401 /* Write UCR2 first as it includes RXEN */
402 imx_uart_writel(sport, ucr2, UCR2);
403 imx_uart_writel(sport, ucr1, UCR1);
404 imx_uart_disable_loopback_rs485(sport);
405 }
406
407 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)408 static void imx_uart_stop_tx(struct uart_port *port)
409 {
410 struct imx_port *sport = (struct imx_port *)port;
411 u32 ucr1, ucr4, usr2;
412
413 if (sport->tx_state == OFF)
414 return;
415
416 /*
417 * We are maybe in the SMP context, so if the DMA TX thread is running
418 * on other cpu, we have to wait for it to finish.
419 */
420 if (sport->dma_is_txing)
421 return;
422
423 ucr1 = imx_uart_readl(sport, UCR1);
424 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
425
426 ucr4 = imx_uart_readl(sport, UCR4);
427 usr2 = imx_uart_readl(sport, USR2);
428 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
429 /* The shifter is still busy, so retry once TC triggers */
430 return;
431 }
432
433 ucr4 &= ~UCR4_TCEN;
434 imx_uart_writel(sport, ucr4, UCR4);
435
436 /* in rs485 mode disable transmitter */
437 if (port->rs485.flags & SER_RS485_ENABLED) {
438 if (sport->tx_state == SEND) {
439 sport->tx_state = WAIT_AFTER_SEND;
440
441 if (port->rs485.delay_rts_after_send > 0) {
442 start_hrtimer_ms(&sport->trigger_stop_tx,
443 port->rs485.delay_rts_after_send);
444 return;
445 }
446
447 /* continue without any delay */
448 }
449
450 if (sport->tx_state == WAIT_AFTER_RTS ||
451 sport->tx_state == WAIT_AFTER_SEND) {
452 u32 ucr2;
453
454 hrtimer_try_to_cancel(&sport->trigger_start_tx);
455
456 ucr2 = imx_uart_readl(sport, UCR2);
457 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
458 imx_uart_rts_active(sport, &ucr2);
459 else
460 imx_uart_rts_inactive(sport, &ucr2);
461 imx_uart_writel(sport, ucr2, UCR2);
462
463 if (!port->rs485_rx_during_tx_gpio)
464 imx_uart_start_rx(port);
465
466 sport->tx_state = OFF;
467 }
468 } else {
469 sport->tx_state = OFF;
470 }
471 }
472
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)473 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
474 {
475 struct imx_port *sport = (struct imx_port *)port;
476 u32 ucr1, ucr2, ucr4, uts;
477
478 ucr1 = imx_uart_readl(sport, UCR1);
479 ucr2 = imx_uart_readl(sport, UCR2);
480 ucr4 = imx_uart_readl(sport, UCR4);
481
482 if (sport->dma_is_enabled) {
483 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
484 } else {
485 ucr1 &= ~UCR1_RRDYEN;
486 ucr2 &= ~UCR2_ATEN;
487 ucr4 &= ~UCR4_OREN;
488 }
489 imx_uart_writel(sport, ucr1, UCR1);
490 imx_uart_writel(sport, ucr4, UCR4);
491
492 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
493 if (port->rs485.flags & SER_RS485_ENABLED &&
494 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
495 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
496 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
497 uts |= UTS_LOOP;
498 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
499 ucr2 |= UCR2_RXEN;
500 } else {
501 ucr2 &= ~UCR2_RXEN;
502 }
503
504 imx_uart_writel(sport, ucr2, UCR2);
505 }
506
507 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)508 static void imx_uart_stop_rx(struct uart_port *port)
509 {
510 /*
511 * Stop RX and enable loopback in order to make sure RS485 bus
512 * is not blocked. Se comment in imx_uart_probe().
513 */
514 imx_uart_stop_rx_with_loopback_ctrl(port, true);
515 }
516
517 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)518 static void imx_uart_enable_ms(struct uart_port *port)
519 {
520 struct imx_port *sport = (struct imx_port *)port;
521
522 mod_timer(&sport->timer, jiffies);
523
524 mctrl_gpio_enable_ms(sport->gpios);
525 }
526
527 static void imx_uart_dma_tx(struct imx_port *sport);
528
529 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)530 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
531 {
532 struct circ_buf *xmit = &sport->port.state->xmit;
533
534 if (sport->port.x_char) {
535 /* Send next char */
536 imx_uart_writel(sport, sport->port.x_char, URTX0);
537 sport->port.icount.tx++;
538 sport->port.x_char = 0;
539 return;
540 }
541
542 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
543 imx_uart_stop_tx(&sport->port);
544 return;
545 }
546
547 if (sport->dma_is_enabled) {
548 u32 ucr1;
549 /*
550 * We've just sent a X-char Ensure the TX DMA is enabled
551 * and the TX IRQ is disabled.
552 **/
553 ucr1 = imx_uart_readl(sport, UCR1);
554 ucr1 &= ~UCR1_TRDYEN;
555 if (sport->dma_is_txing) {
556 ucr1 |= UCR1_TXDMAEN;
557 imx_uart_writel(sport, ucr1, UCR1);
558 } else {
559 imx_uart_writel(sport, ucr1, UCR1);
560 imx_uart_dma_tx(sport);
561 }
562
563 return;
564 }
565
566 while (!uart_circ_empty(xmit) &&
567 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
568 /* send xmit->buf[xmit->tail]
569 * out the port here */
570 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
571 uart_xmit_advance(&sport->port, 1);
572 }
573
574 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
575 uart_write_wakeup(&sport->port);
576
577 if (uart_circ_empty(xmit))
578 imx_uart_stop_tx(&sport->port);
579 }
580
imx_uart_dma_tx_callback(void * data)581 static void imx_uart_dma_tx_callback(void *data)
582 {
583 struct imx_port *sport = data;
584 struct scatterlist *sgl = &sport->tx_sgl[0];
585 struct circ_buf *xmit = &sport->port.state->xmit;
586 unsigned long flags;
587 u32 ucr1;
588
589 spin_lock_irqsave(&sport->port.lock, flags);
590
591 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
592
593 ucr1 = imx_uart_readl(sport, UCR1);
594 ucr1 &= ~UCR1_TXDMAEN;
595 imx_uart_writel(sport, ucr1, UCR1);
596
597 uart_xmit_advance(&sport->port, sport->tx_bytes);
598
599 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
600
601 sport->dma_is_txing = 0;
602
603 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
604 uart_write_wakeup(&sport->port);
605
606 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
607 imx_uart_dma_tx(sport);
608 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
609 u32 ucr4 = imx_uart_readl(sport, UCR4);
610 ucr4 |= UCR4_TCEN;
611 imx_uart_writel(sport, ucr4, UCR4);
612 }
613
614 spin_unlock_irqrestore(&sport->port.lock, flags);
615 }
616
617 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)618 static void imx_uart_dma_tx(struct imx_port *sport)
619 {
620 struct circ_buf *xmit = &sport->port.state->xmit;
621 struct scatterlist *sgl = sport->tx_sgl;
622 struct dma_async_tx_descriptor *desc;
623 struct dma_chan *chan = sport->dma_chan_tx;
624 struct device *dev = sport->port.dev;
625 u32 ucr1, ucr4;
626 int ret;
627
628 if (sport->dma_is_txing)
629 return;
630
631 ucr4 = imx_uart_readl(sport, UCR4);
632 ucr4 &= ~UCR4_TCEN;
633 imx_uart_writel(sport, ucr4, UCR4);
634
635 sport->tx_bytes = uart_circ_chars_pending(xmit);
636
637 if (xmit->tail < xmit->head || xmit->head == 0) {
638 sport->dma_tx_nents = 1;
639 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
640 } else {
641 sport->dma_tx_nents = 2;
642 sg_init_table(sgl, 2);
643 sg_set_buf(sgl, xmit->buf + xmit->tail,
644 UART_XMIT_SIZE - xmit->tail);
645 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
646 }
647
648 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
649 if (ret == 0) {
650 dev_err(dev, "DMA mapping error for TX.\n");
651 return;
652 }
653 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
654 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
655 if (!desc) {
656 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
657 DMA_TO_DEVICE);
658 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
659 return;
660 }
661 desc->callback = imx_uart_dma_tx_callback;
662 desc->callback_param = sport;
663
664 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
665 uart_circ_chars_pending(xmit));
666
667 ucr1 = imx_uart_readl(sport, UCR1);
668 ucr1 |= UCR1_TXDMAEN;
669 imx_uart_writel(sport, ucr1, UCR1);
670
671 /* fire it */
672 sport->dma_is_txing = 1;
673 dmaengine_submit(desc);
674 dma_async_issue_pending(chan);
675 return;
676 }
677
678 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)679 static void imx_uart_start_tx(struct uart_port *port)
680 {
681 struct imx_port *sport = (struct imx_port *)port;
682 u32 ucr1;
683
684 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
685 return;
686
687 /*
688 * We cannot simply do nothing here if sport->tx_state == SEND already
689 * because UCR1_TXMPTYEN might already have been cleared in
690 * imx_uart_stop_tx(), but tx_state is still SEND.
691 */
692
693 if (port->rs485.flags & SER_RS485_ENABLED) {
694 if (sport->tx_state == OFF) {
695 u32 ucr2 = imx_uart_readl(sport, UCR2);
696 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
697 imx_uart_rts_active(sport, &ucr2);
698 else
699 imx_uart_rts_inactive(sport, &ucr2);
700 imx_uart_writel(sport, ucr2, UCR2);
701
702 /*
703 * Since we are about to transmit we can not stop RX
704 * with loopback enabled because that will make our
705 * transmitted data being just looped to RX.
706 */
707 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
708 !port->rs485_rx_during_tx_gpio)
709 imx_uart_stop_rx_with_loopback_ctrl(port, false);
710
711 sport->tx_state = WAIT_AFTER_RTS;
712
713 if (port->rs485.delay_rts_before_send > 0) {
714 start_hrtimer_ms(&sport->trigger_start_tx,
715 port->rs485.delay_rts_before_send);
716 return;
717 }
718
719 /* continue without any delay */
720 }
721
722 if (sport->tx_state == WAIT_AFTER_SEND
723 || sport->tx_state == WAIT_AFTER_RTS) {
724
725 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
726
727 /*
728 * Enable transmitter and shifter empty irq only if DMA
729 * is off. In the DMA case this is done in the
730 * tx-callback.
731 */
732 if (!sport->dma_is_enabled) {
733 u32 ucr4 = imx_uart_readl(sport, UCR4);
734 ucr4 |= UCR4_TCEN;
735 imx_uart_writel(sport, ucr4, UCR4);
736 }
737
738 sport->tx_state = SEND;
739 }
740 } else {
741 sport->tx_state = SEND;
742 }
743
744 if (!sport->dma_is_enabled) {
745 ucr1 = imx_uart_readl(sport, UCR1);
746 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
747 }
748
749 if (sport->dma_is_enabled) {
750 if (sport->port.x_char) {
751 /* We have X-char to send, so enable TX IRQ and
752 * disable TX DMA to let TX interrupt to send X-char */
753 ucr1 = imx_uart_readl(sport, UCR1);
754 ucr1 &= ~UCR1_TXDMAEN;
755 ucr1 |= UCR1_TRDYEN;
756 imx_uart_writel(sport, ucr1, UCR1);
757 return;
758 }
759
760 if (!uart_circ_empty(&port->state->xmit) &&
761 !uart_tx_stopped(port))
762 imx_uart_dma_tx(sport);
763 return;
764 }
765 }
766
__imx_uart_rtsint(int irq,void * dev_id)767 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
768 {
769 struct imx_port *sport = dev_id;
770 u32 usr1;
771
772 imx_uart_writel(sport, USR1_RTSD, USR1);
773 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
774 /*
775 * Update sport->old_status here, so any follow-up calls to
776 * imx_uart_mctrl_check() will be able to recognize that RTS
777 * state changed since last imx_uart_mctrl_check() call.
778 *
779 * In case RTS has been detected as asserted here and later on
780 * deasserted by the time imx_uart_mctrl_check() was called,
781 * imx_uart_mctrl_check() can detect the RTS state change and
782 * trigger uart_handle_cts_change() to unblock the port for
783 * further TX transfers.
784 */
785 if (usr1 & USR1_RTSS)
786 sport->old_status |= TIOCM_CTS;
787 else
788 sport->old_status &= ~TIOCM_CTS;
789 uart_handle_cts_change(&sport->port, usr1);
790 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
791
792 return IRQ_HANDLED;
793 }
794
imx_uart_rtsint(int irq,void * dev_id)795 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
796 {
797 struct imx_port *sport = dev_id;
798 irqreturn_t ret;
799
800 spin_lock(&sport->port.lock);
801
802 ret = __imx_uart_rtsint(irq, dev_id);
803
804 spin_unlock(&sport->port.lock);
805
806 return ret;
807 }
808
imx_uart_txint(int irq,void * dev_id)809 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
810 {
811 struct imx_port *sport = dev_id;
812
813 spin_lock(&sport->port.lock);
814 imx_uart_transmit_buffer(sport);
815 spin_unlock(&sport->port.lock);
816 return IRQ_HANDLED;
817 }
818
819 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
820 * This is to be called from Rx ISRs only when some bytes were actually
821 * received.
822 *
823 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
824 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
825 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
826 * that is terminated by any activity on RxD line, or could be stopped by
827 * issuing soft reset to the UART (just stop/start of RX does not help). Note
828 * that what we do here is sending isolated start bit about 2.4 times shorter
829 * than it is to be on UART configured baud rate.
830 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)831 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
832 {
833 /* To detect hardware 0xff flood we monitor RxD line between RX
834 * interrupts to isolate "receiving" of char(s) with no activity
835 * on RxD line, that'd never happen on actual data transfers.
836 *
837 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
838 * race here if we clear USR2_WAKE when receiving of a char is in
839 * progress, so we might get RX interrupt later with USR2_WAKE bit
840 * cleared. Note though that as we don't try to clear USR2_WAKE when we
841 * detected no activity, this race may hide actual activity only once.
842 *
843 * Yet another case where receive interrupt may occur without RxD
844 * activity is expiration of aging timer, so we consider this as well.
845 *
846 * We use 'idle_counter' to ensure that we got at least so many RX
847 * interrupts without any detected activity on RxD line. 2 cases
848 * described plus 1 to be on the safe side gives us a margin of 3,
849 * below. In practice I was not able to produce a false positive to
850 * induce soft reset at regular data transfers even using 1 as the
851 * margin, so 3 is actually very strong.
852 *
853 * We count interrupts, not chars in 'idle-counter' for simplicity.
854 */
855
856 if (usr2 & USR2_WAKE) {
857 imx_uart_writel(sport, USR2_WAKE, USR2);
858 sport->idle_counter = 0;
859 } else if (++sport->idle_counter > 3) {
860 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
861 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
862 }
863 }
864
__imx_uart_rxint(int irq,void * dev_id)865 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
866 {
867 struct imx_port *sport = dev_id;
868 struct tty_port *port = &sport->port.state->port;
869 u32 usr2, rx;
870
871 /* If we received something, check for 0xff flood */
872 usr2 = imx_uart_readl(sport, USR2);
873 if (usr2 & USR2_RDR)
874 imx_uart_check_flood(sport, usr2);
875
876 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
877 unsigned int flg = TTY_NORMAL;
878 sport->port.icount.rx++;
879
880 if (unlikely(rx & URXD_ERR)) {
881 if (rx & URXD_BRK) {
882 sport->port.icount.brk++;
883 if (uart_handle_break(&sport->port))
884 continue;
885 }
886 else if (rx & URXD_PRERR)
887 sport->port.icount.parity++;
888 else if (rx & URXD_FRMERR)
889 sport->port.icount.frame++;
890 if (rx & URXD_OVRRUN)
891 sport->port.icount.overrun++;
892
893 if (rx & sport->port.ignore_status_mask)
894 continue;
895
896 rx &= (sport->port.read_status_mask | 0xFF);
897
898 if (rx & URXD_BRK)
899 flg = TTY_BREAK;
900 else if (rx & URXD_PRERR)
901 flg = TTY_PARITY;
902 else if (rx & URXD_FRMERR)
903 flg = TTY_FRAME;
904 if (rx & URXD_OVRRUN)
905 flg = TTY_OVERRUN;
906
907 sport->port.sysrq = 0;
908 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
909 continue;
910 }
911
912 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
913 continue;
914
915 if (tty_insert_flip_char(port, rx, flg) == 0)
916 sport->port.icount.buf_overrun++;
917 }
918
919 tty_flip_buffer_push(port);
920
921 return IRQ_HANDLED;
922 }
923
imx_uart_rxint(int irq,void * dev_id)924 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
925 {
926 struct imx_port *sport = dev_id;
927 irqreturn_t ret;
928
929 spin_lock(&sport->port.lock);
930
931 ret = __imx_uart_rxint(irq, dev_id);
932
933 spin_unlock(&sport->port.lock);
934
935 return ret;
936 }
937
938 static void imx_uart_clear_rx_errors(struct imx_port *sport);
939
940 /*
941 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
942 */
imx_uart_get_hwmctrl(struct imx_port * sport)943 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
944 {
945 unsigned int tmp = TIOCM_DSR;
946 unsigned usr1 = imx_uart_readl(sport, USR1);
947 unsigned usr2 = imx_uart_readl(sport, USR2);
948
949 if (usr1 & USR1_RTSS)
950 tmp |= TIOCM_CTS;
951
952 /* in DCE mode DCDIN is always 0 */
953 if (!(usr2 & USR2_DCDIN))
954 tmp |= TIOCM_CAR;
955
956 if (sport->dte_mode)
957 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
958 tmp |= TIOCM_RI;
959
960 return tmp;
961 }
962
963 /*
964 * Handle any change of modem status signal since we were last called.
965 */
imx_uart_mctrl_check(struct imx_port * sport)966 static void imx_uart_mctrl_check(struct imx_port *sport)
967 {
968 unsigned int status, changed;
969
970 status = imx_uart_get_hwmctrl(sport);
971 changed = status ^ sport->old_status;
972
973 if (changed == 0)
974 return;
975
976 sport->old_status = status;
977
978 if (changed & TIOCM_RI && status & TIOCM_RI)
979 sport->port.icount.rng++;
980 if (changed & TIOCM_DSR)
981 sport->port.icount.dsr++;
982 if (changed & TIOCM_CAR)
983 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
984 if (changed & TIOCM_CTS)
985 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
986
987 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
988 }
989
imx_uart_int(int irq,void * dev_id)990 static irqreturn_t imx_uart_int(int irq, void *dev_id)
991 {
992 struct imx_port *sport = dev_id;
993 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
994 irqreturn_t ret = IRQ_NONE;
995
996 spin_lock(&sport->port.lock);
997
998 usr1 = imx_uart_readl(sport, USR1);
999 usr2 = imx_uart_readl(sport, USR2);
1000 ucr1 = imx_uart_readl(sport, UCR1);
1001 ucr2 = imx_uart_readl(sport, UCR2);
1002 ucr3 = imx_uart_readl(sport, UCR3);
1003 ucr4 = imx_uart_readl(sport, UCR4);
1004
1005 /*
1006 * Even if a condition is true that can trigger an irq only handle it if
1007 * the respective irq source is enabled. This prevents some undesired
1008 * actions, for example if a character that sits in the RX FIFO and that
1009 * should be fetched via DMA is tried to be fetched using PIO. Or the
1010 * receiver is currently off and so reading from URXD0 results in an
1011 * exception. So just mask the (raw) status bits for disabled irqs.
1012 */
1013 if ((ucr1 & UCR1_RRDYEN) == 0)
1014 usr1 &= ~USR1_RRDY;
1015 if ((ucr2 & UCR2_ATEN) == 0)
1016 usr1 &= ~USR1_AGTIM;
1017 if ((ucr1 & UCR1_TRDYEN) == 0)
1018 usr1 &= ~USR1_TRDY;
1019 if ((ucr4 & UCR4_TCEN) == 0)
1020 usr2 &= ~USR2_TXDC;
1021 if ((ucr3 & UCR3_DTRDEN) == 0)
1022 usr1 &= ~USR1_DTRD;
1023 if ((ucr1 & UCR1_RTSDEN) == 0)
1024 usr1 &= ~USR1_RTSD;
1025 if ((ucr3 & UCR3_AWAKEN) == 0)
1026 usr1 &= ~USR1_AWAKE;
1027 if ((ucr4 & UCR4_OREN) == 0)
1028 usr2 &= ~USR2_ORE;
1029
1030 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1031 imx_uart_writel(sport, USR1_AGTIM, USR1);
1032
1033 __imx_uart_rxint(irq, dev_id);
1034 ret = IRQ_HANDLED;
1035 }
1036
1037 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1038 imx_uart_transmit_buffer(sport);
1039 ret = IRQ_HANDLED;
1040 }
1041
1042 if (usr1 & USR1_DTRD) {
1043 imx_uart_writel(sport, USR1_DTRD, USR1);
1044
1045 imx_uart_mctrl_check(sport);
1046
1047 ret = IRQ_HANDLED;
1048 }
1049
1050 if (usr1 & USR1_RTSD) {
1051 __imx_uart_rtsint(irq, dev_id);
1052 ret = IRQ_HANDLED;
1053 }
1054
1055 if (usr1 & USR1_AWAKE) {
1056 imx_uart_writel(sport, USR1_AWAKE, USR1);
1057 ret = IRQ_HANDLED;
1058 }
1059
1060 if (usr2 & USR2_ORE) {
1061 sport->port.icount.overrun++;
1062 imx_uart_writel(sport, USR2_ORE, USR2);
1063 ret = IRQ_HANDLED;
1064 }
1065
1066 spin_unlock(&sport->port.lock);
1067
1068 return ret;
1069 }
1070
1071 /*
1072 * Return TIOCSER_TEMT when transmitter is not busy.
1073 */
imx_uart_tx_empty(struct uart_port * port)1074 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1075 {
1076 struct imx_port *sport = (struct imx_port *)port;
1077 unsigned int ret;
1078
1079 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1080
1081 /* If the TX DMA is working, return 0. */
1082 if (sport->dma_is_txing)
1083 ret = 0;
1084
1085 return ret;
1086 }
1087
1088 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1089 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1090 {
1091 struct imx_port *sport = (struct imx_port *)port;
1092 unsigned int ret = imx_uart_get_hwmctrl(sport);
1093
1094 mctrl_gpio_get(sport->gpios, &ret);
1095
1096 return ret;
1097 }
1098
1099 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1100 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1101 {
1102 struct imx_port *sport = (struct imx_port *)port;
1103 u32 ucr3, uts;
1104
1105 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1106 u32 ucr2;
1107
1108 /*
1109 * Turn off autoRTS if RTS is lowered and restore autoRTS
1110 * setting if RTS is raised.
1111 */
1112 ucr2 = imx_uart_readl(sport, UCR2);
1113 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1114 if (mctrl & TIOCM_RTS) {
1115 ucr2 |= UCR2_CTS;
1116 /*
1117 * UCR2_IRTS is unset if and only if the port is
1118 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1119 * to get the state to restore to.
1120 */
1121 if (!(ucr2 & UCR2_IRTS))
1122 ucr2 |= UCR2_CTSC;
1123 }
1124 imx_uart_writel(sport, ucr2, UCR2);
1125 }
1126
1127 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1128 if (!(mctrl & TIOCM_DTR))
1129 ucr3 |= UCR3_DSR;
1130 imx_uart_writel(sport, ucr3, UCR3);
1131
1132 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1133 if (mctrl & TIOCM_LOOP)
1134 uts |= UTS_LOOP;
1135 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1136
1137 mctrl_gpio_set(sport->gpios, mctrl);
1138 }
1139
1140 /*
1141 * Interrupts always disabled.
1142 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1143 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1144 {
1145 struct imx_port *sport = (struct imx_port *)port;
1146 unsigned long flags;
1147 u32 ucr1;
1148
1149 spin_lock_irqsave(&sport->port.lock, flags);
1150
1151 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1152
1153 if (break_state != 0)
1154 ucr1 |= UCR1_SNDBRK;
1155
1156 imx_uart_writel(sport, ucr1, UCR1);
1157
1158 spin_unlock_irqrestore(&sport->port.lock, flags);
1159 }
1160
1161 /*
1162 * This is our per-port timeout handler, for checking the
1163 * modem status signals.
1164 */
imx_uart_timeout(struct timer_list * t)1165 static void imx_uart_timeout(struct timer_list *t)
1166 {
1167 struct imx_port *sport = from_timer(sport, t, timer);
1168 unsigned long flags;
1169
1170 if (sport->port.state) {
1171 spin_lock_irqsave(&sport->port.lock, flags);
1172 imx_uart_mctrl_check(sport);
1173 spin_unlock_irqrestore(&sport->port.lock, flags);
1174
1175 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1176 }
1177 }
1178
1179 /*
1180 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1181 * [1] the RX DMA buffer is full.
1182 * [2] the aging timer expires
1183 *
1184 * Condition [2] is triggered when a character has been sitting in the FIFO
1185 * for at least 8 byte durations.
1186 */
imx_uart_dma_rx_callback(void * data)1187 static void imx_uart_dma_rx_callback(void *data)
1188 {
1189 struct imx_port *sport = data;
1190 struct dma_chan *chan = sport->dma_chan_rx;
1191 struct scatterlist *sgl = &sport->rx_sgl;
1192 struct tty_port *port = &sport->port.state->port;
1193 struct dma_tx_state state;
1194 struct circ_buf *rx_ring = &sport->rx_ring;
1195 enum dma_status status;
1196 unsigned int w_bytes = 0;
1197 unsigned int r_bytes;
1198 unsigned int bd_size;
1199
1200 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1201
1202 if (status == DMA_ERROR) {
1203 spin_lock(&sport->port.lock);
1204 imx_uart_clear_rx_errors(sport);
1205 spin_unlock(&sport->port.lock);
1206 return;
1207 }
1208
1209 /*
1210 * The state-residue variable represents the empty space
1211 * relative to the entire buffer. Taking this in consideration
1212 * the head is always calculated base on the buffer total
1213 * length - DMA transaction residue. The UART script from the
1214 * SDMA firmware will jump to the next buffer descriptor,
1215 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1216 * Taking this in consideration the tail is always at the
1217 * beginning of the buffer descriptor that contains the head.
1218 */
1219
1220 /* Calculate the head */
1221 rx_ring->head = sg_dma_len(sgl) - state.residue;
1222
1223 /* Calculate the tail. */
1224 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1225 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1226
1227 if (rx_ring->head <= sg_dma_len(sgl) &&
1228 rx_ring->head > rx_ring->tail) {
1229
1230 /* Move data from tail to head */
1231 r_bytes = rx_ring->head - rx_ring->tail;
1232
1233 /* If we received something, check for 0xff flood */
1234 spin_lock(&sport->port.lock);
1235 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1236 spin_unlock(&sport->port.lock);
1237
1238 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1239
1240 /* CPU claims ownership of RX DMA buffer */
1241 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1242 DMA_FROM_DEVICE);
1243
1244 w_bytes = tty_insert_flip_string(port,
1245 sport->rx_buf + rx_ring->tail, r_bytes);
1246
1247 /* UART retrieves ownership of RX DMA buffer */
1248 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1249 DMA_FROM_DEVICE);
1250
1251 if (w_bytes != r_bytes)
1252 sport->port.icount.buf_overrun++;
1253
1254 sport->port.icount.rx += w_bytes;
1255 }
1256 } else {
1257 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1258 WARN_ON(rx_ring->head <= rx_ring->tail);
1259 }
1260
1261 if (w_bytes) {
1262 tty_flip_buffer_push(port);
1263 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1264 }
1265 }
1266
imx_uart_start_rx_dma(struct imx_port * sport)1267 static int imx_uart_start_rx_dma(struct imx_port *sport)
1268 {
1269 struct scatterlist *sgl = &sport->rx_sgl;
1270 struct dma_chan *chan = sport->dma_chan_rx;
1271 struct device *dev = sport->port.dev;
1272 struct dma_async_tx_descriptor *desc;
1273 int ret;
1274
1275 sport->rx_ring.head = 0;
1276 sport->rx_ring.tail = 0;
1277
1278 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1279 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1280 if (ret == 0) {
1281 dev_err(dev, "DMA mapping error for RX.\n");
1282 return -EINVAL;
1283 }
1284
1285 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1286 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1287 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1288
1289 if (!desc) {
1290 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1291 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1292 return -EINVAL;
1293 }
1294 desc->callback = imx_uart_dma_rx_callback;
1295 desc->callback_param = sport;
1296
1297 dev_dbg(dev, "RX: prepare for the DMA.\n");
1298 sport->dma_is_rxing = 1;
1299 sport->rx_cookie = dmaengine_submit(desc);
1300 dma_async_issue_pending(chan);
1301 return 0;
1302 }
1303
imx_uart_clear_rx_errors(struct imx_port * sport)1304 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1305 {
1306 struct tty_port *port = &sport->port.state->port;
1307 u32 usr1, usr2;
1308
1309 usr1 = imx_uart_readl(sport, USR1);
1310 usr2 = imx_uart_readl(sport, USR2);
1311
1312 if (usr2 & USR2_BRCD) {
1313 sport->port.icount.brk++;
1314 imx_uart_writel(sport, USR2_BRCD, USR2);
1315 uart_handle_break(&sport->port);
1316 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1317 sport->port.icount.buf_overrun++;
1318 tty_flip_buffer_push(port);
1319 } else {
1320 if (usr1 & USR1_FRAMERR) {
1321 sport->port.icount.frame++;
1322 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1323 } else if (usr1 & USR1_PARITYERR) {
1324 sport->port.icount.parity++;
1325 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1326 }
1327 }
1328
1329 if (usr2 & USR2_ORE) {
1330 sport->port.icount.overrun++;
1331 imx_uart_writel(sport, USR2_ORE, USR2);
1332 }
1333
1334 sport->idle_counter = 0;
1335
1336 }
1337
1338 #define TXTL_DEFAULT 8
1339 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1340 #define TXTL_DMA 8 /* DMA burst setting */
1341 #define RXTL_DMA 9 /* DMA burst setting */
1342
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1343 static void imx_uart_setup_ufcr(struct imx_port *sport,
1344 unsigned char txwl, unsigned char rxwl)
1345 {
1346 unsigned int val;
1347
1348 /* set receiver / transmitter trigger level */
1349 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1350 val |= txwl << UFCR_TXTL_SHF | rxwl;
1351 imx_uart_writel(sport, val, UFCR);
1352 }
1353
imx_uart_dma_exit(struct imx_port * sport)1354 static void imx_uart_dma_exit(struct imx_port *sport)
1355 {
1356 if (sport->dma_chan_rx) {
1357 dmaengine_terminate_sync(sport->dma_chan_rx);
1358 dma_release_channel(sport->dma_chan_rx);
1359 sport->dma_chan_rx = NULL;
1360 sport->rx_cookie = -EINVAL;
1361 kfree(sport->rx_buf);
1362 sport->rx_buf = NULL;
1363 }
1364
1365 if (sport->dma_chan_tx) {
1366 dmaengine_terminate_sync(sport->dma_chan_tx);
1367 dma_release_channel(sport->dma_chan_tx);
1368 sport->dma_chan_tx = NULL;
1369 }
1370 }
1371
imx_uart_dma_init(struct imx_port * sport)1372 static int imx_uart_dma_init(struct imx_port *sport)
1373 {
1374 struct dma_slave_config slave_config = {};
1375 struct device *dev = sport->port.dev;
1376 int ret;
1377
1378 /* Prepare for RX : */
1379 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1380 if (!sport->dma_chan_rx) {
1381 dev_dbg(dev, "cannot get the DMA channel.\n");
1382 ret = -EINVAL;
1383 goto err;
1384 }
1385
1386 slave_config.direction = DMA_DEV_TO_MEM;
1387 slave_config.src_addr = sport->port.mapbase + URXD0;
1388 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1389 /* one byte less than the watermark level to enable the aging timer */
1390 slave_config.src_maxburst = RXTL_DMA - 1;
1391 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1392 if (ret) {
1393 dev_err(dev, "error in RX dma configuration.\n");
1394 goto err;
1395 }
1396
1397 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1398 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1399 if (!sport->rx_buf) {
1400 ret = -ENOMEM;
1401 goto err;
1402 }
1403 sport->rx_ring.buf = sport->rx_buf;
1404
1405 /* Prepare for TX : */
1406 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1407 if (!sport->dma_chan_tx) {
1408 dev_err(dev, "cannot get the TX DMA channel!\n");
1409 ret = -EINVAL;
1410 goto err;
1411 }
1412
1413 slave_config.direction = DMA_MEM_TO_DEV;
1414 slave_config.dst_addr = sport->port.mapbase + URTX0;
1415 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1416 slave_config.dst_maxburst = TXTL_DMA;
1417 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1418 if (ret) {
1419 dev_err(dev, "error in TX dma configuration.");
1420 goto err;
1421 }
1422
1423 return 0;
1424 err:
1425 imx_uart_dma_exit(sport);
1426 return ret;
1427 }
1428
imx_uart_enable_dma(struct imx_port * sport)1429 static void imx_uart_enable_dma(struct imx_port *sport)
1430 {
1431 u32 ucr1;
1432
1433 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1434
1435 /* set UCR1 */
1436 ucr1 = imx_uart_readl(sport, UCR1);
1437 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1438 imx_uart_writel(sport, ucr1, UCR1);
1439
1440 sport->dma_is_enabled = 1;
1441 }
1442
imx_uart_disable_dma(struct imx_port * sport)1443 static void imx_uart_disable_dma(struct imx_port *sport)
1444 {
1445 u32 ucr1;
1446
1447 /* clear UCR1 */
1448 ucr1 = imx_uart_readl(sport, UCR1);
1449 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1450 imx_uart_writel(sport, ucr1, UCR1);
1451
1452 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1453
1454 sport->dma_is_enabled = 0;
1455 }
1456
1457 /* half the RX buffer size */
1458 #define CTSTL 16
1459
imx_uart_startup(struct uart_port * port)1460 static int imx_uart_startup(struct uart_port *port)
1461 {
1462 struct imx_port *sport = (struct imx_port *)port;
1463 int retval;
1464 unsigned long flags;
1465 int dma_is_inited = 0;
1466 u32 ucr1, ucr2, ucr3, ucr4;
1467
1468 retval = clk_prepare_enable(sport->clk_per);
1469 if (retval)
1470 return retval;
1471 retval = clk_prepare_enable(sport->clk_ipg);
1472 if (retval) {
1473 clk_disable_unprepare(sport->clk_per);
1474 return retval;
1475 }
1476
1477 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1478
1479 /* disable the DREN bit (Data Ready interrupt enable) before
1480 * requesting IRQs
1481 */
1482 ucr4 = imx_uart_readl(sport, UCR4);
1483
1484 /* set the trigger level for CTS */
1485 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1486 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1487
1488 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1489
1490 /* Can we enable the DMA support? */
1491 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1492 dma_is_inited = 1;
1493
1494 spin_lock_irqsave(&sport->port.lock, flags);
1495
1496 /* Reset fifo's and state machines */
1497 imx_uart_soft_reset(sport);
1498
1499 /*
1500 * Finally, clear and enable interrupts
1501 */
1502 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1503 imx_uart_writel(sport, USR2_ORE, USR2);
1504
1505 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1506 ucr1 |= UCR1_UARTEN;
1507 if (sport->have_rtscts)
1508 ucr1 |= UCR1_RTSDEN;
1509
1510 imx_uart_writel(sport, ucr1, UCR1);
1511
1512 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1513 if (!dma_is_inited)
1514 ucr4 |= UCR4_OREN;
1515 if (sport->inverted_rx)
1516 ucr4 |= UCR4_INVR;
1517 imx_uart_writel(sport, ucr4, UCR4);
1518
1519 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1520 /*
1521 * configure tx polarity before enabling tx
1522 */
1523 if (sport->inverted_tx)
1524 ucr3 |= UCR3_INVT;
1525
1526 if (!imx_uart_is_imx1(sport)) {
1527 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1528
1529 if (sport->dte_mode)
1530 /* disable broken interrupts */
1531 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1532 }
1533 imx_uart_writel(sport, ucr3, UCR3);
1534
1535 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1536 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1537 if (!sport->have_rtscts)
1538 ucr2 |= UCR2_IRTS;
1539 /*
1540 * make sure the edge sensitive RTS-irq is disabled,
1541 * we're using RTSD instead.
1542 */
1543 if (!imx_uart_is_imx1(sport))
1544 ucr2 &= ~UCR2_RTSEN;
1545 imx_uart_writel(sport, ucr2, UCR2);
1546
1547 /*
1548 * Enable modem status interrupts
1549 */
1550 imx_uart_enable_ms(&sport->port);
1551
1552 if (dma_is_inited) {
1553 imx_uart_enable_dma(sport);
1554 imx_uart_start_rx_dma(sport);
1555 } else {
1556 ucr1 = imx_uart_readl(sport, UCR1);
1557 ucr1 |= UCR1_RRDYEN;
1558 imx_uart_writel(sport, ucr1, UCR1);
1559
1560 ucr2 = imx_uart_readl(sport, UCR2);
1561 ucr2 |= UCR2_ATEN;
1562 imx_uart_writel(sport, ucr2, UCR2);
1563 }
1564
1565 imx_uart_disable_loopback_rs485(sport);
1566
1567 spin_unlock_irqrestore(&sport->port.lock, flags);
1568
1569 return 0;
1570 }
1571
imx_uart_shutdown(struct uart_port * port)1572 static void imx_uart_shutdown(struct uart_port *port)
1573 {
1574 struct imx_port *sport = (struct imx_port *)port;
1575 unsigned long flags;
1576 u32 ucr1, ucr2, ucr4, uts;
1577
1578 if (sport->dma_is_enabled) {
1579 dmaengine_terminate_sync(sport->dma_chan_tx);
1580 if (sport->dma_is_txing) {
1581 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1582 sport->dma_tx_nents, DMA_TO_DEVICE);
1583 sport->dma_is_txing = 0;
1584 }
1585 dmaengine_terminate_sync(sport->dma_chan_rx);
1586 if (sport->dma_is_rxing) {
1587 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1588 1, DMA_FROM_DEVICE);
1589 sport->dma_is_rxing = 0;
1590 }
1591
1592 spin_lock_irqsave(&sport->port.lock, flags);
1593 imx_uart_stop_tx(port);
1594 imx_uart_stop_rx(port);
1595 imx_uart_disable_dma(sport);
1596 spin_unlock_irqrestore(&sport->port.lock, flags);
1597 imx_uart_dma_exit(sport);
1598 }
1599
1600 mctrl_gpio_disable_ms(sport->gpios);
1601
1602 spin_lock_irqsave(&sport->port.lock, flags);
1603 ucr2 = imx_uart_readl(sport, UCR2);
1604 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1605 imx_uart_writel(sport, ucr2, UCR2);
1606 spin_unlock_irqrestore(&sport->port.lock, flags);
1607
1608 /*
1609 * Stop our timer.
1610 */
1611 del_timer_sync(&sport->timer);
1612
1613 /*
1614 * Disable all interrupts, port and break condition.
1615 */
1616
1617 spin_lock_irqsave(&sport->port.lock, flags);
1618
1619 ucr1 = imx_uart_readl(sport, UCR1);
1620 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1621 UCR1_ATDMAEN | UCR1_SNDBRK);
1622 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1623 if (port->rs485.flags & SER_RS485_ENABLED &&
1624 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1625 sport->have_rtscts && !sport->have_rtsgpio) {
1626 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1627 uts |= UTS_LOOP;
1628 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1629 ucr1 |= UCR1_UARTEN;
1630 } else {
1631 ucr1 &= ~UCR1_UARTEN;
1632 }
1633 imx_uart_writel(sport, ucr1, UCR1);
1634
1635 ucr4 = imx_uart_readl(sport, UCR4);
1636 ucr4 &= ~UCR4_TCEN;
1637 imx_uart_writel(sport, ucr4, UCR4);
1638
1639 spin_unlock_irqrestore(&sport->port.lock, flags);
1640
1641 clk_disable_unprepare(sport->clk_per);
1642 clk_disable_unprepare(sport->clk_ipg);
1643 }
1644
1645 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1646 static void imx_uart_flush_buffer(struct uart_port *port)
1647 {
1648 struct imx_port *sport = (struct imx_port *)port;
1649 struct scatterlist *sgl = &sport->tx_sgl[0];
1650
1651 if (!sport->dma_chan_tx)
1652 return;
1653
1654 sport->tx_bytes = 0;
1655 dmaengine_terminate_all(sport->dma_chan_tx);
1656 if (sport->dma_is_txing) {
1657 u32 ucr1;
1658
1659 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1660 DMA_TO_DEVICE);
1661 ucr1 = imx_uart_readl(sport, UCR1);
1662 ucr1 &= ~UCR1_TXDMAEN;
1663 imx_uart_writel(sport, ucr1, UCR1);
1664 sport->dma_is_txing = 0;
1665 }
1666
1667 imx_uart_soft_reset(sport);
1668
1669 }
1670
1671 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1672 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1673 const struct ktermios *old)
1674 {
1675 struct imx_port *sport = (struct imx_port *)port;
1676 unsigned long flags;
1677 u32 ucr2, old_ucr2, ufcr;
1678 unsigned int baud, quot;
1679 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1680 unsigned long div;
1681 unsigned long num, denom, old_ubir, old_ubmr;
1682 uint64_t tdiv64;
1683
1684 /*
1685 * We only support CS7 and CS8.
1686 */
1687 while ((termios->c_cflag & CSIZE) != CS7 &&
1688 (termios->c_cflag & CSIZE) != CS8) {
1689 termios->c_cflag &= ~CSIZE;
1690 termios->c_cflag |= old_csize;
1691 old_csize = CS8;
1692 }
1693
1694 del_timer_sync(&sport->timer);
1695
1696 /*
1697 * Ask the core to calculate the divisor for us.
1698 */
1699 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1700 quot = uart_get_divisor(port, baud);
1701
1702 spin_lock_irqsave(&sport->port.lock, flags);
1703
1704 /*
1705 * Read current UCR2 and save it for future use, then clear all the bits
1706 * except those we will or may need to preserve.
1707 */
1708 old_ucr2 = imx_uart_readl(sport, UCR2);
1709 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1710
1711 ucr2 |= UCR2_SRST | UCR2_IRTS;
1712 if ((termios->c_cflag & CSIZE) == CS8)
1713 ucr2 |= UCR2_WS;
1714
1715 if (!sport->have_rtscts)
1716 termios->c_cflag &= ~CRTSCTS;
1717
1718 if (port->rs485.flags & SER_RS485_ENABLED) {
1719 /*
1720 * RTS is mandatory for rs485 operation, so keep
1721 * it under manual control and keep transmitter
1722 * disabled.
1723 */
1724 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1725 imx_uart_rts_active(sport, &ucr2);
1726 else
1727 imx_uart_rts_inactive(sport, &ucr2);
1728
1729 } else if (termios->c_cflag & CRTSCTS) {
1730 /*
1731 * Only let receiver control RTS output if we were not requested
1732 * to have RTS inactive (which then should take precedence).
1733 */
1734 if (ucr2 & UCR2_CTS)
1735 ucr2 |= UCR2_CTSC;
1736 }
1737
1738 if (termios->c_cflag & CRTSCTS)
1739 ucr2 &= ~UCR2_IRTS;
1740 if (termios->c_cflag & CSTOPB)
1741 ucr2 |= UCR2_STPB;
1742 if (termios->c_cflag & PARENB) {
1743 ucr2 |= UCR2_PREN;
1744 if (termios->c_cflag & PARODD)
1745 ucr2 |= UCR2_PROE;
1746 }
1747
1748 sport->port.read_status_mask = 0;
1749 if (termios->c_iflag & INPCK)
1750 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1751 if (termios->c_iflag & (BRKINT | PARMRK))
1752 sport->port.read_status_mask |= URXD_BRK;
1753
1754 /*
1755 * Characters to ignore
1756 */
1757 sport->port.ignore_status_mask = 0;
1758 if (termios->c_iflag & IGNPAR)
1759 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1760 if (termios->c_iflag & IGNBRK) {
1761 sport->port.ignore_status_mask |= URXD_BRK;
1762 /*
1763 * If we're ignoring parity and break indicators,
1764 * ignore overruns too (for real raw support).
1765 */
1766 if (termios->c_iflag & IGNPAR)
1767 sport->port.ignore_status_mask |= URXD_OVRRUN;
1768 }
1769
1770 if ((termios->c_cflag & CREAD) == 0)
1771 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1772
1773 /*
1774 * Update the per-port timeout.
1775 */
1776 uart_update_timeout(port, termios->c_cflag, baud);
1777
1778 /* custom-baudrate handling */
1779 div = sport->port.uartclk / (baud * 16);
1780 if (baud == 38400 && quot != div)
1781 baud = sport->port.uartclk / (quot * 16);
1782
1783 div = sport->port.uartclk / (baud * 16);
1784 if (div > 7)
1785 div = 7;
1786 if (!div)
1787 div = 1;
1788
1789 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1790 1 << 16, 1 << 16, &num, &denom);
1791
1792 tdiv64 = sport->port.uartclk;
1793 tdiv64 *= num;
1794 do_div(tdiv64, denom * 16 * div);
1795 tty_termios_encode_baud_rate(termios,
1796 (speed_t)tdiv64, (speed_t)tdiv64);
1797
1798 num -= 1;
1799 denom -= 1;
1800
1801 ufcr = imx_uart_readl(sport, UFCR);
1802 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1803 imx_uart_writel(sport, ufcr, UFCR);
1804
1805 /*
1806 * Two registers below should always be written both and in this
1807 * particular order. One consequence is that we need to check if any of
1808 * them changes and then update both. We do need the check for change
1809 * as even writing the same values seem to "restart"
1810 * transmission/receiving logic in the hardware, that leads to data
1811 * breakage even when rate doesn't in fact change. E.g., user switches
1812 * RTS/CTS handshake and suddenly gets broken bytes.
1813 */
1814 old_ubir = imx_uart_readl(sport, UBIR);
1815 old_ubmr = imx_uart_readl(sport, UBMR);
1816 if (old_ubir != num || old_ubmr != denom) {
1817 imx_uart_writel(sport, num, UBIR);
1818 imx_uart_writel(sport, denom, UBMR);
1819 }
1820
1821 if (!imx_uart_is_imx1(sport))
1822 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1823 IMX21_ONEMS);
1824
1825 imx_uart_writel(sport, ucr2, UCR2);
1826
1827 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1828 imx_uart_enable_ms(&sport->port);
1829
1830 spin_unlock_irqrestore(&sport->port.lock, flags);
1831 }
1832
imx_uart_type(struct uart_port * port)1833 static const char *imx_uart_type(struct uart_port *port)
1834 {
1835 return port->type == PORT_IMX ? "IMX" : NULL;
1836 }
1837
1838 /*
1839 * Configure/autoconfigure the port.
1840 */
imx_uart_config_port(struct uart_port * port,int flags)1841 static void imx_uart_config_port(struct uart_port *port, int flags)
1842 {
1843 if (flags & UART_CONFIG_TYPE)
1844 port->type = PORT_IMX;
1845 }
1846
1847 /*
1848 * Verify the new serial_struct (for TIOCSSERIAL).
1849 * The only change we allow are to the flags and type, and
1850 * even then only between PORT_IMX and PORT_UNKNOWN
1851 */
1852 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1853 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1854 {
1855 int ret = 0;
1856
1857 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1858 ret = -EINVAL;
1859 if (port->irq != ser->irq)
1860 ret = -EINVAL;
1861 if (ser->io_type != UPIO_MEM)
1862 ret = -EINVAL;
1863 if (port->uartclk / 16 != ser->baud_base)
1864 ret = -EINVAL;
1865 if (port->mapbase != (unsigned long)ser->iomem_base)
1866 ret = -EINVAL;
1867 if (port->iobase != ser->port)
1868 ret = -EINVAL;
1869 if (ser->hub6 != 0)
1870 ret = -EINVAL;
1871 return ret;
1872 }
1873
1874 #if defined(CONFIG_CONSOLE_POLL)
1875
imx_uart_poll_init(struct uart_port * port)1876 static int imx_uart_poll_init(struct uart_port *port)
1877 {
1878 struct imx_port *sport = (struct imx_port *)port;
1879 unsigned long flags;
1880 u32 ucr1, ucr2;
1881 int retval;
1882
1883 retval = clk_prepare_enable(sport->clk_ipg);
1884 if (retval)
1885 return retval;
1886 retval = clk_prepare_enable(sport->clk_per);
1887 if (retval)
1888 clk_disable_unprepare(sport->clk_ipg);
1889
1890 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1891
1892 spin_lock_irqsave(&sport->port.lock, flags);
1893
1894 /*
1895 * Be careful about the order of enabling bits here. First enable the
1896 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1897 * This prevents that a character that already sits in the RX fifo is
1898 * triggering an irq but the try to fetch it from there results in an
1899 * exception because UARTEN or RXEN is still off.
1900 */
1901 ucr1 = imx_uart_readl(sport, UCR1);
1902 ucr2 = imx_uart_readl(sport, UCR2);
1903
1904 if (imx_uart_is_imx1(sport))
1905 ucr1 |= IMX1_UCR1_UARTCLKEN;
1906
1907 ucr1 |= UCR1_UARTEN;
1908 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1909
1910 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1911 ucr2 &= ~UCR2_ATEN;
1912
1913 imx_uart_writel(sport, ucr1, UCR1);
1914 imx_uart_writel(sport, ucr2, UCR2);
1915
1916 /* now enable irqs */
1917 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1918 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1919
1920 spin_unlock_irqrestore(&sport->port.lock, flags);
1921
1922 return 0;
1923 }
1924
imx_uart_poll_get_char(struct uart_port * port)1925 static int imx_uart_poll_get_char(struct uart_port *port)
1926 {
1927 struct imx_port *sport = (struct imx_port *)port;
1928 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1929 return NO_POLL_CHAR;
1930
1931 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1932 }
1933
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1934 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1935 {
1936 struct imx_port *sport = (struct imx_port *)port;
1937 unsigned int status;
1938
1939 /* drain */
1940 do {
1941 status = imx_uart_readl(sport, USR1);
1942 } while (~status & USR1_TRDY);
1943
1944 /* write */
1945 imx_uart_writel(sport, c, URTX0);
1946
1947 /* flush */
1948 do {
1949 status = imx_uart_readl(sport, USR2);
1950 } while (~status & USR2_TXDC);
1951 }
1952 #endif
1953
1954 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1955 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1956 struct serial_rs485 *rs485conf)
1957 {
1958 struct imx_port *sport = (struct imx_port *)port;
1959 u32 ucr2, ufcr;
1960
1961 if (rs485conf->flags & SER_RS485_ENABLED) {
1962 /* Enable receiver if low-active RTS signal is requested */
1963 if (sport->have_rtscts && !sport->have_rtsgpio &&
1964 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1965 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1966
1967 /* disable transmitter */
1968 ucr2 = imx_uart_readl(sport, UCR2);
1969 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1970 imx_uart_rts_active(sport, &ucr2);
1971 else
1972 imx_uart_rts_inactive(sport, &ucr2);
1973 imx_uart_writel(sport, ucr2, UCR2);
1974 }
1975
1976 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1977 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1978 rs485conf->flags & SER_RS485_RX_DURING_TX) {
1979 /* If the receiver trigger is 0, set it to a default value */
1980 ufcr = imx_uart_readl(sport, UFCR);
1981 if ((ufcr & UFCR_RXTL_MASK) == 0)
1982 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1983 imx_uart_start_rx(port);
1984 }
1985
1986 return 0;
1987 }
1988
1989 static const struct uart_ops imx_uart_pops = {
1990 .tx_empty = imx_uart_tx_empty,
1991 .set_mctrl = imx_uart_set_mctrl,
1992 .get_mctrl = imx_uart_get_mctrl,
1993 .stop_tx = imx_uart_stop_tx,
1994 .start_tx = imx_uart_start_tx,
1995 .stop_rx = imx_uart_stop_rx,
1996 .enable_ms = imx_uart_enable_ms,
1997 .break_ctl = imx_uart_break_ctl,
1998 .startup = imx_uart_startup,
1999 .shutdown = imx_uart_shutdown,
2000 .flush_buffer = imx_uart_flush_buffer,
2001 .set_termios = imx_uart_set_termios,
2002 .type = imx_uart_type,
2003 .config_port = imx_uart_config_port,
2004 .verify_port = imx_uart_verify_port,
2005 #if defined(CONFIG_CONSOLE_POLL)
2006 .poll_init = imx_uart_poll_init,
2007 .poll_get_char = imx_uart_poll_get_char,
2008 .poll_put_char = imx_uart_poll_put_char,
2009 #endif
2010 };
2011
2012 static struct imx_port *imx_uart_ports[UART_NR];
2013
2014 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)2015 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2016 {
2017 struct imx_port *sport = (struct imx_port *)port;
2018
2019 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2020 barrier();
2021
2022 imx_uart_writel(sport, ch, URTX0);
2023 }
2024
2025 /*
2026 * Interrupts are disabled on entering
2027 */
2028 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2029 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2030 {
2031 struct imx_port *sport = imx_uart_ports[co->index];
2032 struct imx_port_ucrs old_ucr;
2033 unsigned long flags;
2034 unsigned int ucr1, usr2;
2035 int locked = 1;
2036
2037 if (sport->port.sysrq)
2038 locked = 0;
2039 else if (oops_in_progress)
2040 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2041 else
2042 spin_lock_irqsave(&sport->port.lock, flags);
2043
2044 /*
2045 * First, save UCR1/2/3 and then disable interrupts
2046 */
2047 imx_uart_ucrs_save(sport, &old_ucr);
2048 ucr1 = old_ucr.ucr1;
2049
2050 if (imx_uart_is_imx1(sport))
2051 ucr1 |= IMX1_UCR1_UARTCLKEN;
2052 ucr1 |= UCR1_UARTEN;
2053 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2054
2055 imx_uart_writel(sport, ucr1, UCR1);
2056
2057 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2058
2059 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2060
2061 /*
2062 * Finally, wait for transmitter to become empty
2063 * and restore UCR1/2/3
2064 */
2065 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2066 0, USEC_PER_SEC, false, sport, USR2);
2067 imx_uart_ucrs_restore(sport, &old_ucr);
2068
2069 if (locked)
2070 spin_unlock_irqrestore(&sport->port.lock, flags);
2071 }
2072
2073 /*
2074 * If the port was already initialised (eg, by a boot loader),
2075 * try to determine the current setup.
2076 */
2077 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2078 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2079 int *parity, int *bits)
2080 {
2081
2082 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2083 /* ok, the port was enabled */
2084 unsigned int ucr2, ubir, ubmr, uartclk;
2085 unsigned int baud_raw;
2086 unsigned int ucfr_rfdiv;
2087
2088 ucr2 = imx_uart_readl(sport, UCR2);
2089
2090 *parity = 'n';
2091 if (ucr2 & UCR2_PREN) {
2092 if (ucr2 & UCR2_PROE)
2093 *parity = 'o';
2094 else
2095 *parity = 'e';
2096 }
2097
2098 if (ucr2 & UCR2_WS)
2099 *bits = 8;
2100 else
2101 *bits = 7;
2102
2103 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2104 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2105
2106 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2107 if (ucfr_rfdiv == 6)
2108 ucfr_rfdiv = 7;
2109 else
2110 ucfr_rfdiv = 6 - ucfr_rfdiv;
2111
2112 uartclk = clk_get_rate(sport->clk_per);
2113 uartclk /= ucfr_rfdiv;
2114
2115 { /*
2116 * The next code provides exact computation of
2117 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2118 * without need of float support or long long division,
2119 * which would be required to prevent 32bit arithmetic overflow
2120 */
2121 unsigned int mul = ubir + 1;
2122 unsigned int div = 16 * (ubmr + 1);
2123 unsigned int rem = uartclk % div;
2124
2125 baud_raw = (uartclk / div) * mul;
2126 baud_raw += (rem * mul + div / 2) / div;
2127 *baud = (baud_raw + 50) / 100 * 100;
2128 }
2129
2130 if (*baud != baud_raw)
2131 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2132 baud_raw, *baud);
2133 }
2134 }
2135
2136 static int
imx_uart_console_setup(struct console * co,char * options)2137 imx_uart_console_setup(struct console *co, char *options)
2138 {
2139 struct imx_port *sport;
2140 int baud = 9600;
2141 int bits = 8;
2142 int parity = 'n';
2143 int flow = 'n';
2144 int retval;
2145
2146 /*
2147 * Check whether an invalid uart number has been specified, and
2148 * if so, search for the first available port that does have
2149 * console support.
2150 */
2151 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2152 co->index = 0;
2153 sport = imx_uart_ports[co->index];
2154 if (sport == NULL)
2155 return -ENODEV;
2156
2157 /* For setting the registers, we only need to enable the ipg clock. */
2158 retval = clk_prepare_enable(sport->clk_ipg);
2159 if (retval)
2160 goto error_console;
2161
2162 if (options)
2163 uart_parse_options(options, &baud, &parity, &bits, &flow);
2164 else
2165 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2166
2167 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2168
2169 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2170
2171 if (retval) {
2172 clk_disable_unprepare(sport->clk_ipg);
2173 goto error_console;
2174 }
2175
2176 retval = clk_prepare_enable(sport->clk_per);
2177 if (retval)
2178 clk_disable_unprepare(sport->clk_ipg);
2179
2180 error_console:
2181 return retval;
2182 }
2183
2184 static int
imx_uart_console_exit(struct console * co)2185 imx_uart_console_exit(struct console *co)
2186 {
2187 struct imx_port *sport = imx_uart_ports[co->index];
2188
2189 clk_disable_unprepare(sport->clk_per);
2190 clk_disable_unprepare(sport->clk_ipg);
2191
2192 return 0;
2193 }
2194
2195 static struct uart_driver imx_uart_uart_driver;
2196 static struct console imx_uart_console = {
2197 .name = DEV_NAME,
2198 .write = imx_uart_console_write,
2199 .device = uart_console_device,
2200 .setup = imx_uart_console_setup,
2201 .exit = imx_uart_console_exit,
2202 .flags = CON_PRINTBUFFER,
2203 .index = -1,
2204 .data = &imx_uart_uart_driver,
2205 };
2206
2207 #define IMX_CONSOLE &imx_uart_console
2208
2209 #else
2210 #define IMX_CONSOLE NULL
2211 #endif
2212
2213 static struct uart_driver imx_uart_uart_driver = {
2214 .owner = THIS_MODULE,
2215 .driver_name = DRIVER_NAME,
2216 .dev_name = DEV_NAME,
2217 .major = SERIAL_IMX_MAJOR,
2218 .minor = MINOR_START,
2219 .nr = ARRAY_SIZE(imx_uart_ports),
2220 .cons = IMX_CONSOLE,
2221 };
2222
imx_trigger_start_tx(struct hrtimer * t)2223 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2224 {
2225 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2226 unsigned long flags;
2227
2228 spin_lock_irqsave(&sport->port.lock, flags);
2229 if (sport->tx_state == WAIT_AFTER_RTS)
2230 imx_uart_start_tx(&sport->port);
2231 spin_unlock_irqrestore(&sport->port.lock, flags);
2232
2233 return HRTIMER_NORESTART;
2234 }
2235
imx_trigger_stop_tx(struct hrtimer * t)2236 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2237 {
2238 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2239 unsigned long flags;
2240
2241 spin_lock_irqsave(&sport->port.lock, flags);
2242 if (sport->tx_state == WAIT_AFTER_SEND)
2243 imx_uart_stop_tx(&sport->port);
2244 spin_unlock_irqrestore(&sport->port.lock, flags);
2245
2246 return HRTIMER_NORESTART;
2247 }
2248
2249 static const struct serial_rs485 imx_rs485_supported = {
2250 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2251 SER_RS485_RX_DURING_TX,
2252 .delay_rts_before_send = 1,
2253 .delay_rts_after_send = 1,
2254 };
2255
2256 /* Default RX DMA buffer configuration */
2257 #define RX_DMA_PERIODS 16
2258 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2259
imx_uart_probe(struct platform_device * pdev)2260 static int imx_uart_probe(struct platform_device *pdev)
2261 {
2262 struct device_node *np = pdev->dev.of_node;
2263 struct imx_port *sport;
2264 void __iomem *base;
2265 u32 dma_buf_conf[2];
2266 int ret = 0;
2267 u32 ucr1, ucr2, uts;
2268 struct resource *res;
2269 int txirq, rxirq, rtsirq;
2270
2271 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2272 if (!sport)
2273 return -ENOMEM;
2274
2275 sport->devdata = of_device_get_match_data(&pdev->dev);
2276
2277 ret = of_alias_get_id(np, "serial");
2278 if (ret < 0) {
2279 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2280 return ret;
2281 }
2282 sport->port.line = ret;
2283
2284 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2285 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2286
2287 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2288
2289 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2290
2291 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2292
2293 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2294
2295 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2296 sport->rx_period_length = dma_buf_conf[0];
2297 sport->rx_periods = dma_buf_conf[1];
2298 } else {
2299 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2300 sport->rx_periods = RX_DMA_PERIODS;
2301 }
2302
2303 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2304 dev_err(&pdev->dev, "serial%d out of range\n",
2305 sport->port.line);
2306 return -EINVAL;
2307 }
2308
2309 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2310 if (IS_ERR(base))
2311 return PTR_ERR(base);
2312
2313 rxirq = platform_get_irq(pdev, 0);
2314 if (rxirq < 0)
2315 return rxirq;
2316 txirq = platform_get_irq_optional(pdev, 1);
2317 rtsirq = platform_get_irq_optional(pdev, 2);
2318
2319 sport->port.dev = &pdev->dev;
2320 sport->port.mapbase = res->start;
2321 sport->port.membase = base;
2322 sport->port.type = PORT_IMX;
2323 sport->port.iotype = UPIO_MEM;
2324 sport->port.irq = rxirq;
2325 sport->port.fifosize = 32;
2326 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2327 sport->port.ops = &imx_uart_pops;
2328 sport->port.rs485_config = imx_uart_rs485_config;
2329 /* RTS is required to control the RS485 transmitter */
2330 if (sport->have_rtscts || sport->have_rtsgpio)
2331 sport->port.rs485_supported = imx_rs485_supported;
2332 sport->port.flags = UPF_BOOT_AUTOCONF;
2333 timer_setup(&sport->timer, imx_uart_timeout, 0);
2334
2335 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2336 if (IS_ERR(sport->gpios))
2337 return PTR_ERR(sport->gpios);
2338
2339 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2340 if (IS_ERR(sport->clk_ipg)) {
2341 ret = PTR_ERR(sport->clk_ipg);
2342 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2343 return ret;
2344 }
2345
2346 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2347 if (IS_ERR(sport->clk_per)) {
2348 ret = PTR_ERR(sport->clk_per);
2349 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2350 return ret;
2351 }
2352
2353 sport->port.uartclk = clk_get_rate(sport->clk_per);
2354
2355 /* For register access, we only need to enable the ipg clock. */
2356 ret = clk_prepare_enable(sport->clk_ipg);
2357 if (ret) {
2358 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2359 return ret;
2360 }
2361
2362 ret = uart_get_rs485_mode(&sport->port);
2363 if (ret)
2364 goto err_clk;
2365
2366 /*
2367 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2368 * signal cannot be set low during transmission in case the
2369 * receiver is off (limitation of the i.MX UART IP).
2370 */
2371 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2372 sport->have_rtscts && !sport->have_rtsgpio &&
2373 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2374 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2375 dev_err(&pdev->dev,
2376 "low-active RTS not possible when receiver is off, enabling receiver\n");
2377
2378 /* Disable interrupts before requesting them */
2379 ucr1 = imx_uart_readl(sport, UCR1);
2380 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2381 imx_uart_writel(sport, ucr1, UCR1);
2382
2383 /* Disable Ageing Timer interrupt */
2384 ucr2 = imx_uart_readl(sport, UCR2);
2385 ucr2 &= ~UCR2_ATEN;
2386 imx_uart_writel(sport, ucr2, UCR2);
2387
2388 /*
2389 * In case RS485 is enabled without GPIO RTS control, the UART IP
2390 * is used to control CTS signal. Keep both the UART and Receiver
2391 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2392 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2393 * data from being fed into the RX FIFO, enable loopback mode in
2394 * UTS register, which disconnects the RX path from external RXD
2395 * pin and connects it to the Transceiver, which is disabled, so
2396 * no data can be fed to the RX FIFO that way.
2397 */
2398 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2399 sport->have_rtscts && !sport->have_rtsgpio) {
2400 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2401 uts |= UTS_LOOP;
2402 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2403
2404 ucr1 = imx_uart_readl(sport, UCR1);
2405 ucr1 |= UCR1_UARTEN;
2406 imx_uart_writel(sport, ucr1, UCR1);
2407
2408 ucr2 = imx_uart_readl(sport, UCR2);
2409 ucr2 |= UCR2_RXEN;
2410 imx_uart_writel(sport, ucr2, UCR2);
2411 }
2412
2413 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2414 /*
2415 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2416 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2417 * and DCD (when they are outputs) or enables the respective
2418 * irqs. So set this bit early, i.e. before requesting irqs.
2419 */
2420 u32 ufcr = imx_uart_readl(sport, UFCR);
2421 if (!(ufcr & UFCR_DCEDTE))
2422 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2423
2424 /*
2425 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2426 * enabled later because they cannot be cleared
2427 * (confirmed on i.MX25) which makes them unusable.
2428 */
2429 imx_uart_writel(sport,
2430 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2431 UCR3);
2432
2433 } else {
2434 u32 ucr3 = UCR3_DSR;
2435 u32 ufcr = imx_uart_readl(sport, UFCR);
2436 if (ufcr & UFCR_DCEDTE)
2437 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2438
2439 if (!imx_uart_is_imx1(sport))
2440 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2441 imx_uart_writel(sport, ucr3, UCR3);
2442 }
2443
2444 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2445 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2446 sport->trigger_start_tx.function = imx_trigger_start_tx;
2447 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2448
2449 /*
2450 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2451 * chips only have one interrupt.
2452 */
2453 if (txirq > 0) {
2454 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2455 dev_name(&pdev->dev), sport);
2456 if (ret) {
2457 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2458 ret);
2459 goto err_clk;
2460 }
2461
2462 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2463 dev_name(&pdev->dev), sport);
2464 if (ret) {
2465 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2466 ret);
2467 goto err_clk;
2468 }
2469
2470 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2471 dev_name(&pdev->dev), sport);
2472 if (ret) {
2473 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2474 ret);
2475 goto err_clk;
2476 }
2477 } else {
2478 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2479 dev_name(&pdev->dev), sport);
2480 if (ret) {
2481 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2482 goto err_clk;
2483 }
2484 }
2485
2486 imx_uart_ports[sport->port.line] = sport;
2487
2488 platform_set_drvdata(pdev, sport);
2489
2490 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2491
2492 err_clk:
2493 clk_disable_unprepare(sport->clk_ipg);
2494
2495 return ret;
2496 }
2497
imx_uart_remove(struct platform_device * pdev)2498 static int imx_uart_remove(struct platform_device *pdev)
2499 {
2500 struct imx_port *sport = platform_get_drvdata(pdev);
2501
2502 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2503
2504 return 0;
2505 }
2506
imx_uart_restore_context(struct imx_port * sport)2507 static void imx_uart_restore_context(struct imx_port *sport)
2508 {
2509 unsigned long flags;
2510
2511 spin_lock_irqsave(&sport->port.lock, flags);
2512 if (!sport->context_saved) {
2513 spin_unlock_irqrestore(&sport->port.lock, flags);
2514 return;
2515 }
2516
2517 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2518 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2519 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2520 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2521 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2522 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2523 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2524 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2525 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2526 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2527 sport->context_saved = false;
2528 spin_unlock_irqrestore(&sport->port.lock, flags);
2529 }
2530
imx_uart_save_context(struct imx_port * sport)2531 static void imx_uart_save_context(struct imx_port *sport)
2532 {
2533 unsigned long flags;
2534
2535 /* Save necessary regs */
2536 spin_lock_irqsave(&sport->port.lock, flags);
2537 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2538 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2539 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2540 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2541 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2542 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2543 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2544 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2545 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2546 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2547 sport->context_saved = true;
2548 spin_unlock_irqrestore(&sport->port.lock, flags);
2549 }
2550
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2551 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2552 {
2553 u32 ucr3;
2554
2555 ucr3 = imx_uart_readl(sport, UCR3);
2556 if (on) {
2557 imx_uart_writel(sport, USR1_AWAKE, USR1);
2558 ucr3 |= UCR3_AWAKEN;
2559 } else {
2560 ucr3 &= ~UCR3_AWAKEN;
2561 }
2562 imx_uart_writel(sport, ucr3, UCR3);
2563
2564 if (sport->have_rtscts) {
2565 u32 ucr1 = imx_uart_readl(sport, UCR1);
2566 if (on) {
2567 imx_uart_writel(sport, USR1_RTSD, USR1);
2568 ucr1 |= UCR1_RTSDEN;
2569 } else {
2570 ucr1 &= ~UCR1_RTSDEN;
2571 }
2572 imx_uart_writel(sport, ucr1, UCR1);
2573 }
2574 }
2575
imx_uart_suspend_noirq(struct device * dev)2576 static int imx_uart_suspend_noirq(struct device *dev)
2577 {
2578 struct imx_port *sport = dev_get_drvdata(dev);
2579
2580 imx_uart_save_context(sport);
2581
2582 clk_disable(sport->clk_ipg);
2583
2584 pinctrl_pm_select_sleep_state(dev);
2585
2586 return 0;
2587 }
2588
imx_uart_resume_noirq(struct device * dev)2589 static int imx_uart_resume_noirq(struct device *dev)
2590 {
2591 struct imx_port *sport = dev_get_drvdata(dev);
2592 int ret;
2593
2594 pinctrl_pm_select_default_state(dev);
2595
2596 ret = clk_enable(sport->clk_ipg);
2597 if (ret)
2598 return ret;
2599
2600 imx_uart_restore_context(sport);
2601
2602 return 0;
2603 }
2604
imx_uart_suspend(struct device * dev)2605 static int imx_uart_suspend(struct device *dev)
2606 {
2607 struct imx_port *sport = dev_get_drvdata(dev);
2608 int ret;
2609
2610 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2611 disable_irq(sport->port.irq);
2612
2613 ret = clk_prepare_enable(sport->clk_ipg);
2614 if (ret)
2615 return ret;
2616
2617 /* enable wakeup from i.MX UART */
2618 imx_uart_enable_wakeup(sport, true);
2619
2620 return 0;
2621 }
2622
imx_uart_resume(struct device * dev)2623 static int imx_uart_resume(struct device *dev)
2624 {
2625 struct imx_port *sport = dev_get_drvdata(dev);
2626
2627 /* disable wakeup from i.MX UART */
2628 imx_uart_enable_wakeup(sport, false);
2629
2630 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2631 enable_irq(sport->port.irq);
2632
2633 clk_disable_unprepare(sport->clk_ipg);
2634
2635 return 0;
2636 }
2637
imx_uart_freeze(struct device * dev)2638 static int imx_uart_freeze(struct device *dev)
2639 {
2640 struct imx_port *sport = dev_get_drvdata(dev);
2641
2642 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2643
2644 return clk_prepare_enable(sport->clk_ipg);
2645 }
2646
imx_uart_thaw(struct device * dev)2647 static int imx_uart_thaw(struct device *dev)
2648 {
2649 struct imx_port *sport = dev_get_drvdata(dev);
2650
2651 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2652
2653 clk_disable_unprepare(sport->clk_ipg);
2654
2655 return 0;
2656 }
2657
2658 static const struct dev_pm_ops imx_uart_pm_ops = {
2659 .suspend_noirq = imx_uart_suspend_noirq,
2660 .resume_noirq = imx_uart_resume_noirq,
2661 .freeze_noirq = imx_uart_suspend_noirq,
2662 .thaw_noirq = imx_uart_resume_noirq,
2663 .restore_noirq = imx_uart_resume_noirq,
2664 .suspend = imx_uart_suspend,
2665 .resume = imx_uart_resume,
2666 .freeze = imx_uart_freeze,
2667 .thaw = imx_uart_thaw,
2668 .restore = imx_uart_thaw,
2669 };
2670
2671 static struct platform_driver imx_uart_platform_driver = {
2672 .probe = imx_uart_probe,
2673 .remove = imx_uart_remove,
2674
2675 .driver = {
2676 .name = "imx-uart",
2677 .of_match_table = imx_uart_dt_ids,
2678 .pm = &imx_uart_pm_ops,
2679 },
2680 };
2681
imx_uart_init(void)2682 static int __init imx_uart_init(void)
2683 {
2684 int ret = uart_register_driver(&imx_uart_uart_driver);
2685
2686 if (ret)
2687 return ret;
2688
2689 ret = platform_driver_register(&imx_uart_platform_driver);
2690 if (ret != 0)
2691 uart_unregister_driver(&imx_uart_uart_driver);
2692
2693 return ret;
2694 }
2695
imx_uart_exit(void)2696 static void __exit imx_uart_exit(void)
2697 {
2698 platform_driver_unregister(&imx_uart_platform_driver);
2699 uart_unregister_driver(&imx_uart_uart_driver);
2700 }
2701
2702 module_init(imx_uart_init);
2703 module_exit(imx_uart_exit);
2704
2705 MODULE_AUTHOR("Sascha Hauer");
2706 MODULE_DESCRIPTION("IMX generic serial port driver");
2707 MODULE_LICENSE("GPL");
2708 MODULE_ALIAS("platform:imx-uart");
2709