xref: /openbmc/linux/drivers/tty/serial/ucc_uart.c (revision a833b201)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Freescale QUICC Engine UART device driver
4  *
5  * Author: Timur Tabi <timur@freescale.com>
6  *
7  * Copyright 2007 Freescale Semiconductor, Inc.
8  *
9  * This driver adds support for UART devices via Freescale's QUICC Engine
10  * found on some Freescale SOCs.
11  *
12  * If Soft-UART support is needed but not already present, then this driver
13  * will request and upload the "Soft-UART" microcode upon probe.  The
14  * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
15  * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
16  * (e.g. "11" for 1.1).
17  */
18 
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial.h>
22 #include <linux/serial_core.h>
23 #include <linux/slab.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/io.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/dma-mapping.h>
31 
32 #include <soc/fsl/qe/ucc_slow.h>
33 
34 #include <linux/firmware.h>
35 #include <soc/fsl/cpm.h>
36 
37 #ifdef CONFIG_PPC32
38 #include <asm/reg.h> /* mfspr, SPRN_SVR */
39 #endif
40 
41 /*
42  * The GUMR flag for Soft UART.  This would normally be defined in qe.h,
43  * but Soft-UART is a hack and we want to keep everything related to it in
44  * this file.
45  */
46 #define UCC_SLOW_GUMR_H_SUART   	0x00004000      /* Soft-UART */
47 
48 /*
49  * soft_uart is 1 if we need to use Soft-UART mode
50  */
51 static int soft_uart;
52 /*
53  * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
54  */
55 static int firmware_loaded;
56 
57 /* Enable this macro to configure all serial ports in internal loopback
58    mode */
59 /* #define LOOPBACK */
60 
61 /* The major and minor device numbers are defined in
62  * Documentation/admin-guide/devices.txt.  For the QE
63  * UART, we have major number 204 and minor numbers 46 - 49, which are the
64  * same as for the CPM2.  This decision was made because no Freescale part
65  * has both a CPM and a QE.
66  */
67 #define SERIAL_QE_MAJOR 204
68 #define SERIAL_QE_MINOR 46
69 
70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
71 #define UCC_MAX_UART    4
72 
73 /* The number of buffer descriptors for receiving characters. */
74 #define RX_NUM_FIFO     4
75 
76 /* The number of buffer descriptors for transmitting characters. */
77 #define TX_NUM_FIFO     4
78 
79 /* The maximum size of the character buffer for a single RX BD. */
80 #define RX_BUF_SIZE     32
81 
82 /* The maximum size of the character buffer for a single TX BD. */
83 #define TX_BUF_SIZE     32
84 
85 /*
86  * The number of jiffies to wait after receiving a close command before the
87  * device is actually closed.  This allows the last few characters to be
88  * sent over the wire.
89  */
90 #define UCC_WAIT_CLOSING 100
91 
92 struct ucc_uart_pram {
93 	struct ucc_slow_pram common;
94 	u8 res1[8];     	/* reserved */
95 	__be16 maxidl;  	/* Maximum idle chars */
96 	__be16 idlc;    	/* temp idle counter */
97 	__be16 brkcr;   	/* Break count register */
98 	__be16 parec;   	/* receive parity error counter */
99 	__be16 frmec;   	/* receive framing error counter */
100 	__be16 nosec;   	/* receive noise counter */
101 	__be16 brkec;   	/* receive break condition counter */
102 	__be16 brkln;   	/* last received break length */
103 	__be16 uaddr[2];	/* UART address character 1 & 2 */
104 	__be16 rtemp;   	/* Temp storage */
105 	__be16 toseq;   	/* Transmit out of sequence char */
106 	__be16 cchars[8];       /* control characters 1-8 */
107 	__be16 rccm;    	/* receive control character mask */
108 	__be16 rccr;    	/* receive control character register */
109 	__be16 rlbc;    	/* receive last break character */
110 	__be16 res2;    	/* reserved */
111 	__be32 res3;    	/* reserved, should be cleared */
112 	u8 res4;		/* reserved, should be cleared */
113 	u8 res5[3];     	/* reserved, should be cleared */
114 	__be32 res6;    	/* reserved, should be cleared */
115 	__be32 res7;    	/* reserved, should be cleared */
116 	__be32 res8;    	/* reserved, should be cleared */
117 	__be32 res9;    	/* reserved, should be cleared */
118 	__be32 res10;   	/* reserved, should be cleared */
119 	__be32 res11;   	/* reserved, should be cleared */
120 	__be32 res12;   	/* reserved, should be cleared */
121 	__be32 res13;   	/* reserved, should be cleared */
122 /* The rest is for Soft-UART only */
123 	__be16 supsmr;  	/* 0x90, Shadow UPSMR */
124 	__be16 res92;   	/* 0x92, reserved, initialize to 0 */
125 	__be32 rx_state;	/* 0x94, RX state, initialize to 0 */
126 	__be32 rx_cnt;  	/* 0x98, RX count, initialize to 0 */
127 	u8 rx_length;   	/* 0x9C, Char length, set to 1+CL+PEN+1+SL */
128 	u8 rx_bitmark;  	/* 0x9D, reserved, initialize to 0 */
129 	u8 rx_temp_dlst_qe;     /* 0x9E, reserved, initialize to 0 */
130 	u8 res14[0xBC - 0x9F];  /* reserved */
131 	__be32 dump_ptr;	/* 0xBC, Dump pointer */
132 	__be32 rx_frame_rem;    /* 0xC0, reserved, initialize to 0 */
133 	u8 rx_frame_rem_size;   /* 0xC4, reserved, initialize to 0 */
134 	u8 tx_mode;     	/* 0xC5, mode, 0=AHDLC, 1=UART */
135 	__be16 tx_state;	/* 0xC6, TX state */
136 	u8 res15[0xD0 - 0xC8];  /* reserved */
137 	__be32 resD0;   	/* 0xD0, reserved, initialize to 0 */
138 	u8 resD4;       	/* 0xD4, reserved, initialize to 0 */
139 	__be16 resD5;   	/* 0xD5, reserved, initialize to 0 */
140 } __attribute__ ((packed));
141 
142 /* SUPSMR definitions, for Soft-UART only */
143 #define UCC_UART_SUPSMR_SL      	0x8000
144 #define UCC_UART_SUPSMR_RPM_MASK	0x6000
145 #define UCC_UART_SUPSMR_RPM_ODD 	0x0000
146 #define UCC_UART_SUPSMR_RPM_LOW 	0x2000
147 #define UCC_UART_SUPSMR_RPM_EVEN	0x4000
148 #define UCC_UART_SUPSMR_RPM_HIGH	0x6000
149 #define UCC_UART_SUPSMR_PEN     	0x1000
150 #define UCC_UART_SUPSMR_TPM_MASK	0x0C00
151 #define UCC_UART_SUPSMR_TPM_ODD 	0x0000
152 #define UCC_UART_SUPSMR_TPM_LOW 	0x0400
153 #define UCC_UART_SUPSMR_TPM_EVEN	0x0800
154 #define UCC_UART_SUPSMR_TPM_HIGH	0x0C00
155 #define UCC_UART_SUPSMR_FRZ     	0x0100
156 #define UCC_UART_SUPSMR_UM_MASK 	0x00c0
157 #define UCC_UART_SUPSMR_UM_NORMAL       0x0000
158 #define UCC_UART_SUPSMR_UM_MAN_MULTI    0x0040
159 #define UCC_UART_SUPSMR_UM_AUTO_MULTI   0x00c0
160 #define UCC_UART_SUPSMR_CL_MASK 	0x0030
161 #define UCC_UART_SUPSMR_CL_8    	0x0030
162 #define UCC_UART_SUPSMR_CL_7    	0x0020
163 #define UCC_UART_SUPSMR_CL_6    	0x0010
164 #define UCC_UART_SUPSMR_CL_5    	0x0000
165 
166 #define UCC_UART_TX_STATE_AHDLC 	0x00
167 #define UCC_UART_TX_STATE_UART  	0x01
168 #define UCC_UART_TX_STATE_X1    	0x00
169 #define UCC_UART_TX_STATE_X16   	0x80
170 
171 #define UCC_UART_PRAM_ALIGNMENT 0x100
172 
173 #define UCC_UART_SIZE_OF_BD     UCC_SLOW_SIZE_OF_BD
174 #define NUM_CONTROL_CHARS       8
175 
176 /* Private per-port data structure */
177 struct uart_qe_port {
178 	struct uart_port port;
179 	struct ucc_slow __iomem *uccp;
180 	struct ucc_uart_pram __iomem *uccup;
181 	struct ucc_slow_info us_info;
182 	struct ucc_slow_private *us_private;
183 	struct device_node *np;
184 	unsigned int ucc_num;   /* First ucc is 0, not 1 */
185 
186 	u16 rx_nrfifos;
187 	u16 rx_fifosize;
188 	u16 tx_nrfifos;
189 	u16 tx_fifosize;
190 	int wait_closing;
191 	u32 flags;
192 	struct qe_bd *rx_bd_base;
193 	struct qe_bd *rx_cur;
194 	struct qe_bd *tx_bd_base;
195 	struct qe_bd *tx_cur;
196 	unsigned char *tx_buf;
197 	unsigned char *rx_buf;
198 	void *bd_virt;  	/* virtual address of the BD buffers */
199 	dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
200 	unsigned int bd_size;   /* size of BD buffer space */
201 };
202 
203 static struct uart_driver ucc_uart_driver = {
204 	.owner  	= THIS_MODULE,
205 	.driver_name    = "ucc_uart",
206 	.dev_name       = "ttyQE",
207 	.major  	= SERIAL_QE_MAJOR,
208 	.minor  	= SERIAL_QE_MINOR,
209 	.nr     	= UCC_MAX_UART,
210 };
211 
212 /*
213  * Virtual to physical address translation.
214  *
215  * Given the virtual address for a character buffer, this function returns
216  * the physical (DMA) equivalent.
217  */
cpu2qe_addr(void * addr,struct uart_qe_port * qe_port)218 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
219 {
220 	if (likely((addr >= qe_port->bd_virt)) &&
221 	    (addr < (qe_port->bd_virt + qe_port->bd_size)))
222 		return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
223 
224 	/* something nasty happened */
225 	printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
226 	BUG();
227 	return 0;
228 }
229 
230 /*
231  * Physical to virtual address translation.
232  *
233  * Given the physical (DMA) address for a character buffer, this function
234  * returns the virtual equivalent.
235  */
qe2cpu_addr(dma_addr_t addr,struct uart_qe_port * qe_port)236 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
237 {
238 	/* sanity check */
239 	if (likely((addr >= qe_port->bd_dma_addr) &&
240 		   (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
241 		return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
242 
243 	/* something nasty happened */
244 	printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
245 	BUG();
246 	return NULL;
247 }
248 
249 /*
250  * Return 1 if the QE is done transmitting all buffers for this port
251  *
252  * This function scans each BD in sequence.  If we find a BD that is not
253  * ready (READY=1), then we return 0 indicating that the QE is still sending
254  * data.  If we reach the last BD (WRAP=1), then we know we've scanned
255  * the entire list, and all BDs are done.
256  */
qe_uart_tx_empty(struct uart_port * port)257 static unsigned int qe_uart_tx_empty(struct uart_port *port)
258 {
259 	struct uart_qe_port *qe_port =
260 		container_of(port, struct uart_qe_port, port);
261 	struct qe_bd *bdp = qe_port->tx_bd_base;
262 
263 	while (1) {
264 		if (ioread16be(&bdp->status) & BD_SC_READY)
265 			/* This BD is not done, so return "not done" */
266 			return 0;
267 
268 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
269 			/*
270 			 * This BD is done and it's the last one, so return
271 			 * "done"
272 			 */
273 			return 1;
274 
275 		bdp++;
276 	}
277 }
278 
279 /*
280  * Set the modem control lines
281  *
282  * Although the QE can control the modem control lines (e.g. CTS), we
283  * don't need that support. This function must exist, however, otherwise
284  * the kernel will panic.
285  */
qe_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)286 static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 {
288 }
289 
290 /*
291  * Get the current modem control line status
292  *
293  * Although the QE can control the modem control lines (e.g. CTS), this
294  * driver currently doesn't support that, so we always return Carrier
295  * Detect, Data Set Ready, and Clear To Send.
296  */
qe_uart_get_mctrl(struct uart_port * port)297 static unsigned int qe_uart_get_mctrl(struct uart_port *port)
298 {
299 	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
300 }
301 
302 /*
303  * Disable the transmit interrupt.
304  *
305  * Although this function is called "stop_tx", it does not actually stop
306  * transmission of data.  Instead, it tells the QE to not generate an
307  * interrupt when the UCC is finished sending characters.
308  */
qe_uart_stop_tx(struct uart_port * port)309 static void qe_uart_stop_tx(struct uart_port *port)
310 {
311 	struct uart_qe_port *qe_port =
312 		container_of(port, struct uart_qe_port, port);
313 
314 	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
315 }
316 
317 /*
318  * Transmit as many characters to the HW as possible.
319  *
320  * This function will attempt to stuff of all the characters from the
321  * kernel's transmit buffer into TX BDs.
322  *
323  * A return value of non-zero indicates that it successfully stuffed all
324  * characters from the kernel buffer.
325  *
326  * A return value of zero indicates that there are still characters in the
327  * kernel's buffer that have not been transmitted, but there are no more BDs
328  * available.  This function should be called again after a BD has been made
329  * available.
330  */
qe_uart_tx_pump(struct uart_qe_port * qe_port)331 static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
332 {
333 	struct qe_bd *bdp;
334 	unsigned char *p;
335 	unsigned int count;
336 	struct uart_port *port = &qe_port->port;
337 	struct circ_buf *xmit = &port->state->xmit;
338 
339 	/* Handle xon/xoff */
340 	if (port->x_char) {
341 		/* Pick next descriptor and fill from buffer */
342 		bdp = qe_port->tx_cur;
343 
344 		p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
345 
346 		*p++ = port->x_char;
347 		iowrite16be(1, &bdp->length);
348 		qe_setbits_be16(&bdp->status, BD_SC_READY);
349 		/* Get next BD. */
350 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
351 			bdp = qe_port->tx_bd_base;
352 		else
353 			bdp++;
354 		qe_port->tx_cur = bdp;
355 
356 		port->icount.tx++;
357 		port->x_char = 0;
358 		return 1;
359 	}
360 
361 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
362 		qe_uart_stop_tx(port);
363 		return 0;
364 	}
365 
366 	/* Pick next descriptor and fill from buffer */
367 	bdp = qe_port->tx_cur;
368 
369 	while (!(ioread16be(&bdp->status) & BD_SC_READY) && !uart_circ_empty(xmit)) {
370 		count = 0;
371 		p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
372 		while (count < qe_port->tx_fifosize) {
373 			*p++ = xmit->buf[xmit->tail];
374 			uart_xmit_advance(port, 1);
375 			count++;
376 			if (uart_circ_empty(xmit))
377 				break;
378 		}
379 
380 		iowrite16be(count, &bdp->length);
381 		qe_setbits_be16(&bdp->status, BD_SC_READY);
382 
383 		/* Get next BD. */
384 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
385 			bdp = qe_port->tx_bd_base;
386 		else
387 			bdp++;
388 	}
389 	qe_port->tx_cur = bdp;
390 
391 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
392 		uart_write_wakeup(port);
393 
394 	if (uart_circ_empty(xmit)) {
395 		/* The kernel buffer is empty, so turn off TX interrupts.  We
396 		   don't need to be told when the QE is finished transmitting
397 		   the data. */
398 		qe_uart_stop_tx(port);
399 		return 0;
400 	}
401 
402 	return 1;
403 }
404 
405 /*
406  * Start transmitting data
407  *
408  * This function will start transmitting any available data, if the port
409  * isn't already transmitting data.
410  */
qe_uart_start_tx(struct uart_port * port)411 static void qe_uart_start_tx(struct uart_port *port)
412 {
413 	struct uart_qe_port *qe_port =
414 		container_of(port, struct uart_qe_port, port);
415 
416 	/* If we currently are transmitting, then just return */
417 	if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
418 		return;
419 
420 	/* Otherwise, pump the port and start transmission */
421 	if (qe_uart_tx_pump(qe_port))
422 		qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
423 }
424 
425 /*
426  * Stop transmitting data
427  */
qe_uart_stop_rx(struct uart_port * port)428 static void qe_uart_stop_rx(struct uart_port *port)
429 {
430 	struct uart_qe_port *qe_port =
431 		container_of(port, struct uart_qe_port, port);
432 
433 	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
434 }
435 
436 /* Start or stop sending  break signal
437  *
438  * This function controls the sending of a break signal.  If break_state=1,
439  * then we start sending a break signal.  If break_state=0, then we stop
440  * sending the break signal.
441  */
qe_uart_break_ctl(struct uart_port * port,int break_state)442 static void qe_uart_break_ctl(struct uart_port *port, int break_state)
443 {
444 	struct uart_qe_port *qe_port =
445 		container_of(port, struct uart_qe_port, port);
446 
447 	if (break_state)
448 		ucc_slow_stop_tx(qe_port->us_private);
449 	else
450 		ucc_slow_restart_tx(qe_port->us_private);
451 }
452 
453 /* ISR helper function for receiving character.
454  *
455  * This function is called by the ISR to handling receiving characters
456  */
qe_uart_int_rx(struct uart_qe_port * qe_port)457 static void qe_uart_int_rx(struct uart_qe_port *qe_port)
458 {
459 	int i;
460 	unsigned char ch, *cp;
461 	struct uart_port *port = &qe_port->port;
462 	struct tty_port *tport = &port->state->port;
463 	struct qe_bd *bdp;
464 	u16 status;
465 	unsigned int flg;
466 
467 	/* Just loop through the closed BDs and copy the characters into
468 	 * the buffer.
469 	 */
470 	bdp = qe_port->rx_cur;
471 	while (1) {
472 		status = ioread16be(&bdp->status);
473 
474 		/* If this one is empty, then we assume we've read them all */
475 		if (status & BD_SC_EMPTY)
476 			break;
477 
478 		/* get number of characters, and check space in RX buffer */
479 		i = ioread16be(&bdp->length);
480 
481 		/* If we don't have enough room in RX buffer for the entire BD,
482 		 * then we try later, which will be the next RX interrupt.
483 		 */
484 		if (tty_buffer_request_room(tport, i) < i) {
485 			dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
486 			return;
487 		}
488 
489 		/* get pointer */
490 		cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
491 
492 		/* loop through the buffer */
493 		while (i-- > 0) {
494 			ch = *cp++;
495 			port->icount.rx++;
496 			flg = TTY_NORMAL;
497 
498 			if (!i && status &
499 			    (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
500 				goto handle_error;
501 			if (uart_handle_sysrq_char(port, ch))
502 				continue;
503 
504 error_return:
505 			tty_insert_flip_char(tport, ch, flg);
506 
507 		}
508 
509 		/* This BD is ready to be used again. Clear status. get next */
510 		qe_clrsetbits_be16(&bdp->status,
511 				   BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
512 				   BD_SC_EMPTY);
513 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
514 			bdp = qe_port->rx_bd_base;
515 		else
516 			bdp++;
517 
518 	}
519 
520 	/* Write back buffer pointer */
521 	qe_port->rx_cur = bdp;
522 
523 	/* Activate BH processing */
524 	tty_flip_buffer_push(tport);
525 
526 	return;
527 
528 	/* Error processing */
529 
530 handle_error:
531 	/* Statistics */
532 	if (status & BD_SC_BR)
533 		port->icount.brk++;
534 	if (status & BD_SC_PR)
535 		port->icount.parity++;
536 	if (status & BD_SC_FR)
537 		port->icount.frame++;
538 	if (status & BD_SC_OV)
539 		port->icount.overrun++;
540 
541 	/* Mask out ignored conditions */
542 	status &= port->read_status_mask;
543 
544 	/* Handle the remaining ones */
545 	if (status & BD_SC_BR)
546 		flg = TTY_BREAK;
547 	else if (status & BD_SC_PR)
548 		flg = TTY_PARITY;
549 	else if (status & BD_SC_FR)
550 		flg = TTY_FRAME;
551 
552 	/* Overrun does not affect the current character ! */
553 	if (status & BD_SC_OV)
554 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
555 	port->sysrq = 0;
556 	goto error_return;
557 }
558 
559 /* Interrupt handler
560  *
561  * This interrupt handler is called after a BD is processed.
562  */
qe_uart_int(int irq,void * data)563 static irqreturn_t qe_uart_int(int irq, void *data)
564 {
565 	struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
566 	struct ucc_slow __iomem *uccp = qe_port->uccp;
567 	u16 events;
568 
569 	/* Clear the interrupts */
570 	events = ioread16be(&uccp->ucce);
571 	iowrite16be(events, &uccp->ucce);
572 
573 	if (events & UCC_UART_UCCE_BRKE)
574 		uart_handle_break(&qe_port->port);
575 
576 	if (events & UCC_UART_UCCE_RX)
577 		qe_uart_int_rx(qe_port);
578 
579 	if (events & UCC_UART_UCCE_TX)
580 		qe_uart_tx_pump(qe_port);
581 
582 	return events ? IRQ_HANDLED : IRQ_NONE;
583 }
584 
585 /* Initialize buffer descriptors
586  *
587  * This function initializes all of the RX and TX buffer descriptors.
588  */
qe_uart_initbd(struct uart_qe_port * qe_port)589 static void qe_uart_initbd(struct uart_qe_port *qe_port)
590 {
591 	int i;
592 	void *bd_virt;
593 	struct qe_bd *bdp;
594 
595 	/* Set the physical address of the host memory buffers in the buffer
596 	 * descriptors, and the virtual address for us to work with.
597 	 */
598 	bd_virt = qe_port->bd_virt;
599 	bdp = qe_port->rx_bd_base;
600 	qe_port->rx_cur = qe_port->rx_bd_base;
601 	for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
602 		iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
603 		iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
604 		iowrite16be(0, &bdp->length);
605 		bd_virt += qe_port->rx_fifosize;
606 		bdp++;
607 	}
608 
609 	/* */
610 	iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
611 	iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
612 	iowrite16be(0, &bdp->length);
613 
614 	/* Set the physical address of the host memory
615 	 * buffers in the buffer descriptors, and the
616 	 * virtual address for us to work with.
617 	 */
618 	bd_virt = qe_port->bd_virt +
619 		L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
620 	qe_port->tx_cur = qe_port->tx_bd_base;
621 	bdp = qe_port->tx_bd_base;
622 	for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
623 		iowrite16be(BD_SC_INTRPT, &bdp->status);
624 		iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
625 		iowrite16be(0, &bdp->length);
626 		bd_virt += qe_port->tx_fifosize;
627 		bdp++;
628 	}
629 
630 	/* Loopback requires the preamble bit to be set on the first TX BD */
631 #ifdef LOOPBACK
632 	qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
633 #endif
634 
635 	iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
636 	iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
637 	iowrite16be(0, &bdp->length);
638 }
639 
640 /*
641  * Initialize a UCC for UART.
642  *
643  * This function configures a given UCC to be used as a UART device. Basic
644  * UCC initialization is handled in qe_uart_request_port().  This function
645  * does all the UART-specific stuff.
646  */
qe_uart_init_ucc(struct uart_qe_port * qe_port)647 static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
648 {
649 	u32 cecr_subblock;
650 	struct ucc_slow __iomem *uccp = qe_port->uccp;
651 	struct ucc_uart_pram *uccup = qe_port->uccup;
652 
653 	unsigned int i;
654 
655 	/* First, disable TX and RX in the UCC */
656 	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
657 
658 	/* Program the UCC UART parameter RAM */
659 	iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
660 	iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
661 	iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
662 	iowrite16be(0x10, &uccup->maxidl);
663 	iowrite16be(1, &uccup->brkcr);
664 	iowrite16be(0, &uccup->parec);
665 	iowrite16be(0, &uccup->frmec);
666 	iowrite16be(0, &uccup->nosec);
667 	iowrite16be(0, &uccup->brkec);
668 	iowrite16be(0, &uccup->uaddr[0]);
669 	iowrite16be(0, &uccup->uaddr[1]);
670 	iowrite16be(0, &uccup->toseq);
671 	for (i = 0; i < 8; i++)
672 		iowrite16be(0xC000, &uccup->cchars[i]);
673 	iowrite16be(0xc0ff, &uccup->rccm);
674 
675 	/* Configure the GUMR registers for UART */
676 	if (soft_uart) {
677 		/* Soft-UART requires a 1X multiplier for TX */
678 		qe_clrsetbits_be32(&uccp->gumr_l,
679 				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
680 				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
681 
682 		qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
683 				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
684 	} else {
685 		qe_clrsetbits_be32(&uccp->gumr_l,
686 				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
687 				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
688 
689 		qe_clrsetbits_be32(&uccp->gumr_h,
690 				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
691 				   UCC_SLOW_GUMR_H_RFW);
692 	}
693 
694 #ifdef LOOPBACK
695 	qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
696 			   UCC_SLOW_GUMR_L_DIAG_LOOP);
697 	qe_clrsetbits_be32(&uccp->gumr_h,
698 			   UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
699 			   UCC_SLOW_GUMR_H_CDS);
700 #endif
701 
702 	/* Disable rx interrupts  and clear all pending events.  */
703 	iowrite16be(0, &uccp->uccm);
704 	iowrite16be(0xffff, &uccp->ucce);
705 	iowrite16be(0x7e7e, &uccp->udsr);
706 
707 	/* Initialize UPSMR */
708 	iowrite16be(0, &uccp->upsmr);
709 
710 	if (soft_uart) {
711 		iowrite16be(0x30, &uccup->supsmr);
712 		iowrite16be(0, &uccup->res92);
713 		iowrite32be(0, &uccup->rx_state);
714 		iowrite32be(0, &uccup->rx_cnt);
715 		iowrite8(0, &uccup->rx_bitmark);
716 		iowrite8(10, &uccup->rx_length);
717 		iowrite32be(0x4000, &uccup->dump_ptr);
718 		iowrite8(0, &uccup->rx_temp_dlst_qe);
719 		iowrite32be(0, &uccup->rx_frame_rem);
720 		iowrite8(0, &uccup->rx_frame_rem_size);
721 		/* Soft-UART requires TX to be 1X */
722 		iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
723 			    &uccup->tx_mode);
724 		iowrite16be(0, &uccup->tx_state);
725 		iowrite8(0, &uccup->resD4);
726 		iowrite16be(0, &uccup->resD5);
727 
728 		/* Set UART mode.
729 		 * Enable receive and transmit.
730 		 */
731 
732 		/* From the microcode errata:
733 		 * 1.GUMR_L register, set mode=0010 (QMC).
734 		 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
735 		 * 3.Set GUMR_H[19:20] (Transparent mode)
736 		 * 4.Clear GUMR_H[26] (RFW)
737 		 * ...
738 		 * 6.Receiver must use 16x over sampling
739 		 */
740 		qe_clrsetbits_be32(&uccp->gumr_l,
741 				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
742 				   UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
743 
744 		qe_clrsetbits_be32(&uccp->gumr_h,
745 				   UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
746 				   UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
747 
748 #ifdef LOOPBACK
749 		qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
750 				   UCC_SLOW_GUMR_L_DIAG_LOOP);
751 		qe_clrbits_be32(&uccp->gumr_h,
752 				UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
753 #endif
754 
755 		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
756 		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
757 			QE_CR_PROTOCOL_UNSPECIFIED, 0);
758 	} else {
759 		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
760 		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
761 			QE_CR_PROTOCOL_UART, 0);
762 	}
763 }
764 
765 /*
766  * Initialize the port.
767  */
qe_uart_startup(struct uart_port * port)768 static int qe_uart_startup(struct uart_port *port)
769 {
770 	struct uart_qe_port *qe_port =
771 		container_of(port, struct uart_qe_port, port);
772 	int ret;
773 
774 	/*
775 	 * If we're using Soft-UART mode, then we need to make sure the
776 	 * firmware has been uploaded first.
777 	 */
778 	if (soft_uart && !firmware_loaded) {
779 		dev_err(port->dev, "Soft-UART firmware not uploaded\n");
780 		return -ENODEV;
781 	}
782 
783 	qe_uart_initbd(qe_port);
784 	qe_uart_init_ucc(qe_port);
785 
786 	/* Install interrupt handler. */
787 	ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
788 		qe_port);
789 	if (ret) {
790 		dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
791 		return ret;
792 	}
793 
794 	/* Startup rx-int */
795 	qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
796 	ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
797 
798 	return 0;
799 }
800 
801 /*
802  * Shutdown the port.
803  */
qe_uart_shutdown(struct uart_port * port)804 static void qe_uart_shutdown(struct uart_port *port)
805 {
806 	struct uart_qe_port *qe_port =
807 		container_of(port, struct uart_qe_port, port);
808 	struct ucc_slow __iomem *uccp = qe_port->uccp;
809 	unsigned int timeout = 20;
810 
811 	/* Disable RX and TX */
812 
813 	/* Wait for all the BDs marked sent */
814 	while (!qe_uart_tx_empty(port)) {
815 		if (!--timeout) {
816 			dev_warn(port->dev, "shutdown timeout\n");
817 			break;
818 		}
819 		set_current_state(TASK_UNINTERRUPTIBLE);
820 		schedule_timeout(2);
821 	}
822 
823 	if (qe_port->wait_closing) {
824 		/* Wait a bit longer */
825 		set_current_state(TASK_UNINTERRUPTIBLE);
826 		schedule_timeout(qe_port->wait_closing);
827 	}
828 
829 	/* Stop uarts */
830 	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
831 	qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
832 
833 	/* Shut them really down and reinit buffer descriptors */
834 	ucc_slow_graceful_stop_tx(qe_port->us_private);
835 	qe_uart_initbd(qe_port);
836 
837 	free_irq(port->irq, qe_port);
838 }
839 
840 /*
841  * Set the serial port parameters.
842  */
qe_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)843 static void qe_uart_set_termios(struct uart_port *port,
844 				struct ktermios *termios,
845 				const struct ktermios *old)
846 {
847 	struct uart_qe_port *qe_port =
848 		container_of(port, struct uart_qe_port, port);
849 	struct ucc_slow __iomem *uccp = qe_port->uccp;
850 	unsigned int baud;
851 	unsigned long flags;
852 	u16 upsmr = ioread16be(&uccp->upsmr);
853 	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
854 	u16 supsmr = ioread16be(&uccup->supsmr);
855 
856 	/* byte size */
857 	upsmr &= UCC_UART_UPSMR_CL_MASK;
858 	supsmr &= UCC_UART_SUPSMR_CL_MASK;
859 
860 	switch (termios->c_cflag & CSIZE) {
861 	case CS5:
862 		upsmr |= UCC_UART_UPSMR_CL_5;
863 		supsmr |= UCC_UART_SUPSMR_CL_5;
864 		break;
865 	case CS6:
866 		upsmr |= UCC_UART_UPSMR_CL_6;
867 		supsmr |= UCC_UART_SUPSMR_CL_6;
868 		break;
869 	case CS7:
870 		upsmr |= UCC_UART_UPSMR_CL_7;
871 		supsmr |= UCC_UART_SUPSMR_CL_7;
872 		break;
873 	default:	/* case CS8 */
874 		upsmr |= UCC_UART_UPSMR_CL_8;
875 		supsmr |= UCC_UART_SUPSMR_CL_8;
876 		break;
877 	}
878 
879 	/* If CSTOPB is set, we want two stop bits */
880 	if (termios->c_cflag & CSTOPB) {
881 		upsmr |= UCC_UART_UPSMR_SL;
882 		supsmr |= UCC_UART_SUPSMR_SL;
883 	}
884 
885 	if (termios->c_cflag & PARENB) {
886 		upsmr |= UCC_UART_UPSMR_PEN;
887 		supsmr |= UCC_UART_SUPSMR_PEN;
888 
889 		if (!(termios->c_cflag & PARODD)) {
890 			upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
891 				   UCC_UART_UPSMR_TPM_MASK);
892 			upsmr |= UCC_UART_UPSMR_RPM_EVEN |
893 				UCC_UART_UPSMR_TPM_EVEN;
894 			supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
895 				    UCC_UART_SUPSMR_TPM_MASK);
896 			supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
897 				UCC_UART_SUPSMR_TPM_EVEN;
898 		}
899 	}
900 
901 	/*
902 	 * Set up parity check flag
903 	 */
904 	port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
905 	if (termios->c_iflag & INPCK)
906 		port->read_status_mask |= BD_SC_FR | BD_SC_PR;
907 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
908 		port->read_status_mask |= BD_SC_BR;
909 
910 	/*
911 	 * Characters to ignore
912 	 */
913 	port->ignore_status_mask = 0;
914 	if (termios->c_iflag & IGNPAR)
915 		port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
916 	if (termios->c_iflag & IGNBRK) {
917 		port->ignore_status_mask |= BD_SC_BR;
918 		/*
919 		 * If we're ignore parity and break indicators, ignore
920 		 * overruns too.  (For real raw support).
921 		 */
922 		if (termios->c_iflag & IGNPAR)
923 			port->ignore_status_mask |= BD_SC_OV;
924 	}
925 	/*
926 	 * !!! ignore all characters if CREAD is not set
927 	 */
928 	if ((termios->c_cflag & CREAD) == 0)
929 		port->read_status_mask &= ~BD_SC_EMPTY;
930 
931 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
932 
933 	/* Do we really need a spinlock here? */
934 	spin_lock_irqsave(&port->lock, flags);
935 
936 	/* Update the per-port timeout. */
937 	uart_update_timeout(port, termios->c_cflag, baud);
938 
939 	iowrite16be(upsmr, &uccp->upsmr);
940 	if (soft_uart) {
941 		iowrite16be(supsmr, &uccup->supsmr);
942 		iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length);
943 
944 		/* Soft-UART requires a 1X multiplier for TX */
945 		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
946 		qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
947 	} else {
948 		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
949 		qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
950 	}
951 
952 	spin_unlock_irqrestore(&port->lock, flags);
953 }
954 
955 /*
956  * Return a pointer to a string that describes what kind of port this is.
957  */
qe_uart_type(struct uart_port * port)958 static const char *qe_uart_type(struct uart_port *port)
959 {
960 	return "QE";
961 }
962 
963 /*
964  * Allocate any memory and I/O resources required by the port.
965  */
qe_uart_request_port(struct uart_port * port)966 static int qe_uart_request_port(struct uart_port *port)
967 {
968 	int ret;
969 	struct uart_qe_port *qe_port =
970 		container_of(port, struct uart_qe_port, port);
971 	struct ucc_slow_info *us_info = &qe_port->us_info;
972 	struct ucc_slow_private *uccs;
973 	unsigned int rx_size, tx_size;
974 	void *bd_virt;
975 	dma_addr_t bd_dma_addr = 0;
976 
977 	ret = ucc_slow_init(us_info, &uccs);
978 	if (ret) {
979 		dev_err(port->dev, "could not initialize UCC%u\n",
980 		       qe_port->ucc_num);
981 		return ret;
982 	}
983 
984 	qe_port->us_private = uccs;
985 	qe_port->uccp = uccs->us_regs;
986 	qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
987 	qe_port->rx_bd_base = uccs->rx_bd;
988 	qe_port->tx_bd_base = uccs->tx_bd;
989 
990 	/*
991 	 * Allocate the transmit and receive data buffers.
992 	 */
993 
994 	rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
995 	tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
996 
997 	bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
998 		GFP_KERNEL);
999 	if (!bd_virt) {
1000 		dev_err(port->dev, "could not allocate buffer descriptors\n");
1001 		return -ENOMEM;
1002 	}
1003 
1004 	qe_port->bd_virt = bd_virt;
1005 	qe_port->bd_dma_addr = bd_dma_addr;
1006 	qe_port->bd_size = rx_size + tx_size;
1007 
1008 	qe_port->rx_buf = bd_virt;
1009 	qe_port->tx_buf = qe_port->rx_buf + rx_size;
1010 
1011 	return 0;
1012 }
1013 
1014 /*
1015  * Configure the port.
1016  *
1017  * We say we're a CPM-type port because that's mostly true.  Once the device
1018  * is configured, this driver operates almost identically to the CPM serial
1019  * driver.
1020  */
qe_uart_config_port(struct uart_port * port,int flags)1021 static void qe_uart_config_port(struct uart_port *port, int flags)
1022 {
1023 	if (flags & UART_CONFIG_TYPE) {
1024 		port->type = PORT_CPM;
1025 		qe_uart_request_port(port);
1026 	}
1027 }
1028 
1029 /*
1030  * Release any memory and I/O resources that were allocated in
1031  * qe_uart_request_port().
1032  */
qe_uart_release_port(struct uart_port * port)1033 static void qe_uart_release_port(struct uart_port *port)
1034 {
1035 	struct uart_qe_port *qe_port =
1036 		container_of(port, struct uart_qe_port, port);
1037 	struct ucc_slow_private *uccs = qe_port->us_private;
1038 
1039 	dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1040 			  qe_port->bd_dma_addr);
1041 
1042 	ucc_slow_free(uccs);
1043 }
1044 
1045 /*
1046  * Verify that the data in serial_struct is suitable for this device.
1047  */
qe_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1048 static int qe_uart_verify_port(struct uart_port *port,
1049 			       struct serial_struct *ser)
1050 {
1051 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1052 		return -EINVAL;
1053 
1054 	if (ser->irq < 0 || ser->irq >= nr_irqs)
1055 		return -EINVAL;
1056 
1057 	if (ser->baud_base < 9600)
1058 		return -EINVAL;
1059 
1060 	return 0;
1061 }
1062 /* UART operations
1063  *
1064  * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1065  */
1066 static const struct uart_ops qe_uart_pops = {
1067 	.tx_empty       = qe_uart_tx_empty,
1068 	.set_mctrl      = qe_uart_set_mctrl,
1069 	.get_mctrl      = qe_uart_get_mctrl,
1070 	.stop_tx	= qe_uart_stop_tx,
1071 	.start_tx       = qe_uart_start_tx,
1072 	.stop_rx	= qe_uart_stop_rx,
1073 	.break_ctl      = qe_uart_break_ctl,
1074 	.startup	= qe_uart_startup,
1075 	.shutdown       = qe_uart_shutdown,
1076 	.set_termios    = qe_uart_set_termios,
1077 	.type   	= qe_uart_type,
1078 	.release_port   = qe_uart_release_port,
1079 	.request_port   = qe_uart_request_port,
1080 	.config_port    = qe_uart_config_port,
1081 	.verify_port    = qe_uart_verify_port,
1082 };
1083 
1084 
1085 #ifdef CONFIG_PPC32
1086 /*
1087  * Obtain the SOC model number and revision level
1088  *
1089  * This function parses the device tree to obtain the SOC model.  It then
1090  * reads the SVR register to the revision.
1091  *
1092  * The device tree stores the SOC model two different ways.
1093  *
1094  * The new way is:
1095  *
1096  *      	cpu@0 {
1097  *      		compatible = "PowerPC,8323";
1098  *      		device_type = "cpu";
1099  *      		...
1100  *
1101  *
1102  * The old way is:
1103  *      	 PowerPC,8323@0 {
1104  *      		device_type = "cpu";
1105  *      		...
1106  *
1107  * This code first checks the new way, and then the old way.
1108  */
soc_info(unsigned int * rev_h,unsigned int * rev_l)1109 static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1110 {
1111 	struct device_node *np;
1112 	const char *soc_string;
1113 	unsigned int svr;
1114 	unsigned int soc;
1115 
1116 	/* Find the CPU node */
1117 	np = of_find_node_by_type(NULL, "cpu");
1118 	if (!np)
1119 		return 0;
1120 	/* Find the compatible property */
1121 	soc_string = of_get_property(np, "compatible", NULL);
1122 	if (!soc_string)
1123 		/* No compatible property, so try the name. */
1124 		soc_string = np->name;
1125 
1126 	of_node_put(np);
1127 
1128 	/* Extract the SOC number from the "PowerPC," string */
1129 	if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1130 		return 0;
1131 
1132 	/* Get the revision from the SVR */
1133 	svr = mfspr(SPRN_SVR);
1134 	*rev_h = (svr >> 4) & 0xf;
1135 	*rev_l = svr & 0xf;
1136 
1137 	return soc;
1138 }
1139 
1140 /*
1141  * requst_firmware_nowait() callback function
1142  *
1143  * This function is called by the kernel when a firmware is made available,
1144  * or if it times out waiting for the firmware.
1145  */
uart_firmware_cont(const struct firmware * fw,void * context)1146 static void uart_firmware_cont(const struct firmware *fw, void *context)
1147 {
1148 	struct qe_firmware *firmware;
1149 	struct device *dev = context;
1150 	int ret;
1151 
1152 	if (!fw) {
1153 		dev_err(dev, "firmware not found\n");
1154 		return;
1155 	}
1156 
1157 	firmware = (struct qe_firmware *) fw->data;
1158 
1159 	if (firmware->header.length != fw->size) {
1160 		dev_err(dev, "invalid firmware\n");
1161 		goto out;
1162 	}
1163 
1164 	ret = qe_upload_firmware(firmware);
1165 	if (ret) {
1166 		dev_err(dev, "could not load firmware\n");
1167 		goto out;
1168 	}
1169 
1170 	firmware_loaded = 1;
1171  out:
1172 	release_firmware(fw);
1173 }
1174 
soft_uart_init(struct platform_device * ofdev)1175 static int soft_uart_init(struct platform_device *ofdev)
1176 {
1177 	struct device_node *np = ofdev->dev.of_node;
1178 	struct qe_firmware_info *qe_fw_info;
1179 	int ret;
1180 
1181 	if (of_property_read_bool(np, "soft-uart")) {
1182 		dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1183 		soft_uart = 1;
1184 	} else {
1185 		return 0;
1186 	}
1187 
1188 	qe_fw_info = qe_get_firmware_info();
1189 
1190 	/* Check if the firmware has been uploaded. */
1191 	if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1192 		firmware_loaded = 1;
1193 	} else {
1194 		char filename[32];
1195 		unsigned int soc;
1196 		unsigned int rev_h;
1197 		unsigned int rev_l;
1198 
1199 		soc = soc_info(&rev_h, &rev_l);
1200 		if (!soc) {
1201 			dev_err(&ofdev->dev, "unknown CPU model\n");
1202 			return -ENXIO;
1203 		}
1204 		sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1205 			soc, rev_h, rev_l);
1206 
1207 		dev_info(&ofdev->dev, "waiting for firmware %s\n",
1208 			 filename);
1209 
1210 		/*
1211 		 * We call request_firmware_nowait instead of
1212 		 * request_firmware so that the driver can load and
1213 		 * initialize the ports without holding up the rest of
1214 		 * the kernel.  If hotplug support is enabled in the
1215 		 * kernel, then we use it.
1216 		 */
1217 		ret = request_firmware_nowait(THIS_MODULE,
1218 					      FW_ACTION_UEVENT, filename, &ofdev->dev,
1219 					      GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1220 		if (ret) {
1221 			dev_err(&ofdev->dev,
1222 				"could not load firmware %s\n",
1223 				filename);
1224 			return ret;
1225 		}
1226 	}
1227 	return 0;
1228 }
1229 
1230 #else /* !CONFIG_PPC32 */
1231 
soft_uart_init(struct platform_device * ofdev)1232 static int soft_uart_init(struct platform_device *ofdev)
1233 {
1234 	return 0;
1235 }
1236 
1237 #endif
1238 
1239 
ucc_uart_probe(struct platform_device * ofdev)1240 static int ucc_uart_probe(struct platform_device *ofdev)
1241 {
1242 	struct device_node *np = ofdev->dev.of_node;
1243 	const char *sprop;      /* String OF properties */
1244 	struct uart_qe_port *qe_port = NULL;
1245 	struct resource res;
1246 	u32 val;
1247 	int ret;
1248 
1249 	/*
1250 	 * Determine if we need Soft-UART mode
1251 	 */
1252 	ret = soft_uart_init(ofdev);
1253 	if (ret)
1254 		return ret;
1255 
1256 	qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1257 	if (!qe_port) {
1258 		dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1259 		return -ENOMEM;
1260 	}
1261 
1262 	/* Search for IRQ and mapbase */
1263 	ret = of_address_to_resource(np, 0, &res);
1264 	if (ret) {
1265 		dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1266 		goto out_free;
1267 	}
1268 	if (!res.start) {
1269 		dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1270 		ret = -EINVAL;
1271 		goto out_free;
1272 	}
1273 	qe_port->port.mapbase = res.start;
1274 
1275 	/* Get the UCC number (device ID) */
1276 	/* UCCs are numbered 1-7 */
1277 	if (of_property_read_u32(np, "cell-index", &val)) {
1278 		if (of_property_read_u32(np, "device-id", &val)) {
1279 			dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
1280 			ret = -EINVAL;
1281 			goto out_free;
1282 		}
1283 	}
1284 
1285 	if (val < 1 || val > UCC_MAX_NUM) {
1286 		dev_err(&ofdev->dev, "no support for UCC%u\n", val);
1287 		ret = -ENODEV;
1288 		goto out_free;
1289 	}
1290 	qe_port->ucc_num = val - 1;
1291 
1292 	/*
1293 	 * In the future, we should not require the BRG to be specified in the
1294 	 * device tree.  If no clock-source is specified, then just pick a BRG
1295 	 * to use.  This requires a new QE library function that manages BRG
1296 	 * assignments.
1297 	 */
1298 
1299 	sprop = of_get_property(np, "rx-clock-name", NULL);
1300 	if (!sprop) {
1301 		dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1302 		ret = -ENODEV;
1303 		goto out_free;
1304 	}
1305 
1306 	qe_port->us_info.rx_clock = qe_clock_source(sprop);
1307 	if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1308 	    (qe_port->us_info.rx_clock > QE_BRG16)) {
1309 		dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1310 		ret = -ENODEV;
1311 		goto out_free;
1312 	}
1313 
1314 #ifdef LOOPBACK
1315 	/* In internal loopback mode, TX and RX must use the same clock */
1316 	qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1317 #else
1318 	sprop = of_get_property(np, "tx-clock-name", NULL);
1319 	if (!sprop) {
1320 		dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1321 		ret = -ENODEV;
1322 		goto out_free;
1323 	}
1324 	qe_port->us_info.tx_clock = qe_clock_source(sprop);
1325 #endif
1326 	if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1327 	    (qe_port->us_info.tx_clock > QE_BRG16)) {
1328 		dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1329 		ret = -ENODEV;
1330 		goto out_free;
1331 	}
1332 
1333 	/* Get the port number, numbered 0-3 */
1334 	if (of_property_read_u32(np, "port-number", &val)) {
1335 		dev_err(&ofdev->dev, "missing port-number in device tree\n");
1336 		ret = -EINVAL;
1337 		goto out_free;
1338 	}
1339 	qe_port->port.line = val;
1340 	if (qe_port->port.line >= UCC_MAX_UART) {
1341 		dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1342 			UCC_MAX_UART - 1);
1343 		ret = -EINVAL;
1344 		goto out_free;
1345 	}
1346 
1347 	qe_port->port.irq = irq_of_parse_and_map(np, 0);
1348 	if (qe_port->port.irq == 0) {
1349 		dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1350 		       qe_port->ucc_num + 1);
1351 		ret = -EINVAL;
1352 		goto out_free;
1353 	}
1354 
1355 	/*
1356 	 * Newer device trees have an "fsl,qe" compatible property for the QE
1357 	 * node, but we still need to support older device trees.
1358 	 */
1359 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1360 	if (!np) {
1361 		np = of_find_node_by_type(NULL, "qe");
1362 		if (!np) {
1363 			dev_err(&ofdev->dev, "could not find 'qe' node\n");
1364 			ret = -EINVAL;
1365 			goto out_free;
1366 		}
1367 	}
1368 
1369 	if (of_property_read_u32(np, "brg-frequency", &val)) {
1370 		dev_err(&ofdev->dev,
1371 		       "missing brg-frequency in device tree\n");
1372 		ret = -EINVAL;
1373 		goto out_np;
1374 	}
1375 
1376 	if (val)
1377 		qe_port->port.uartclk = val;
1378 	else {
1379 		if (!IS_ENABLED(CONFIG_PPC32)) {
1380 			dev_err(&ofdev->dev,
1381 				"invalid brg-frequency in device tree\n");
1382 			ret = -EINVAL;
1383 			goto out_np;
1384 		}
1385 
1386 		/*
1387 		 * Older versions of U-Boot do not initialize the brg-frequency
1388 		 * property, so in this case we assume the BRG frequency is
1389 		 * half the QE bus frequency.
1390 		 */
1391 		if (of_property_read_u32(np, "bus-frequency", &val)) {
1392 			dev_err(&ofdev->dev,
1393 				"missing QE bus-frequency in device tree\n");
1394 			ret = -EINVAL;
1395 			goto out_np;
1396 		}
1397 		if (val)
1398 			qe_port->port.uartclk = val / 2;
1399 		else {
1400 			dev_err(&ofdev->dev,
1401 				"invalid QE bus-frequency in device tree\n");
1402 			ret = -EINVAL;
1403 			goto out_np;
1404 		}
1405 	}
1406 
1407 	spin_lock_init(&qe_port->port.lock);
1408 	qe_port->np = np;
1409 	qe_port->port.dev = &ofdev->dev;
1410 	qe_port->port.ops = &qe_uart_pops;
1411 	qe_port->port.iotype = UPIO_MEM;
1412 
1413 	qe_port->tx_nrfifos = TX_NUM_FIFO;
1414 	qe_port->tx_fifosize = TX_BUF_SIZE;
1415 	qe_port->rx_nrfifos = RX_NUM_FIFO;
1416 	qe_port->rx_fifosize = RX_BUF_SIZE;
1417 
1418 	qe_port->wait_closing = UCC_WAIT_CLOSING;
1419 	qe_port->port.fifosize = 512;
1420 	qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1421 
1422 	qe_port->us_info.ucc_num = qe_port->ucc_num;
1423 	qe_port->us_info.regs = (phys_addr_t) res.start;
1424 	qe_port->us_info.irq = qe_port->port.irq;
1425 
1426 	qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1427 	qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1428 
1429 	/* Make sure ucc_slow_init() initializes both TX and RX */
1430 	qe_port->us_info.init_tx = 1;
1431 	qe_port->us_info.init_rx = 1;
1432 
1433 	/* Add the port to the uart sub-system.  This will cause
1434 	 * qe_uart_config_port() to be called, so the us_info structure must
1435 	 * be initialized.
1436 	 */
1437 	ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1438 	if (ret) {
1439 		dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1440 		       qe_port->port.line);
1441 		goto out_np;
1442 	}
1443 
1444 	platform_set_drvdata(ofdev, qe_port);
1445 
1446 	dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1447 		qe_port->ucc_num + 1, qe_port->port.line);
1448 
1449 	/* Display the mknod command for this device */
1450 	dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1451 	       qe_port->port.line, SERIAL_QE_MAJOR,
1452 	       SERIAL_QE_MINOR + qe_port->port.line);
1453 
1454 	return 0;
1455 out_np:
1456 	of_node_put(np);
1457 out_free:
1458 	kfree(qe_port);
1459 	return ret;
1460 }
1461 
ucc_uart_remove(struct platform_device * ofdev)1462 static int ucc_uart_remove(struct platform_device *ofdev)
1463 {
1464 	struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1465 
1466 	dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1467 
1468 	uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1469 
1470 	of_node_put(qe_port->np);
1471 
1472 	kfree(qe_port);
1473 
1474 	return 0;
1475 }
1476 
1477 static const struct of_device_id ucc_uart_match[] = {
1478 	{
1479 		.type = "serial",
1480 		.compatible = "ucc_uart",
1481 	},
1482 	{
1483 		.compatible = "fsl,t1040-ucc-uart",
1484 	},
1485 	{},
1486 };
1487 MODULE_DEVICE_TABLE(of, ucc_uart_match);
1488 
1489 static struct platform_driver ucc_uart_of_driver = {
1490 	.driver = {
1491 		.name = "ucc_uart",
1492 		.of_match_table    = ucc_uart_match,
1493 	},
1494 	.probe  	= ucc_uart_probe,
1495 	.remove 	= ucc_uart_remove,
1496 };
1497 
ucc_uart_init(void)1498 static int __init ucc_uart_init(void)
1499 {
1500 	int ret;
1501 
1502 	printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1503 #ifdef LOOPBACK
1504 	printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1505 #endif
1506 
1507 	ret = uart_register_driver(&ucc_uart_driver);
1508 	if (ret) {
1509 		printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1510 		return ret;
1511 	}
1512 
1513 	ret = platform_driver_register(&ucc_uart_of_driver);
1514 	if (ret) {
1515 		printk(KERN_ERR
1516 		       "ucc-uart: could not register platform driver\n");
1517 		uart_unregister_driver(&ucc_uart_driver);
1518 	}
1519 
1520 	return ret;
1521 }
1522 
ucc_uart_exit(void)1523 static void __exit ucc_uart_exit(void)
1524 {
1525 	printk(KERN_INFO
1526 	       "Freescale QUICC Engine UART device driver unloading\n");
1527 
1528 	platform_driver_unregister(&ucc_uart_of_driver);
1529 	uart_unregister_driver(&ucc_uart_driver);
1530 }
1531 
1532 module_init(ucc_uart_init);
1533 module_exit(ucc_uart_exit);
1534 
1535 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1536 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1537 MODULE_LICENSE("GPL v2");
1538 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1539 
1540