xref: /openbmc/qemu/include/hw/char/max78000_uart.h (revision 0edc2afe0c8197bbcb98f948c609fb74c9b1ffd5)
1 /*
2  * MAX78000 UART
3  *
4  * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #ifndef HW_MAX78000_UART_H
10 #define HW_MAX78000_UART_H
11 
12 #include "hw/sysbus.h"
13 #include "chardev/char-fe.h"
14 #include "qemu/fifo8.h"
15 #include "qom/object.h"
16 
17 #define UART_CTRL       0x0
18 #define UART_STATUS     0x4
19 #define UART_INT_EN     0x8
20 #define UART_INT_FL     0xc
21 #define UART_CLKDIV     0x10
22 #define UART_OSR        0x14
23 #define UART_TXPEEK     0x18
24 #define UART_PNR        0x1c
25 #define UART_FIFO       0x20
26 #define UART_DMA        0x30
27 #define UART_WKEN       0x34
28 #define UART_WKFL       0x38
29 
30 /* CTRL */
31 #define UART_CTF_DIS    (1 << 7)
32 #define UART_FLUSH_TX   (1 << 8)
33 #define UART_FLUSH_RX   (1 << 9)
34 #define UART_BCLKEN     (1 << 15)
35 #define UART_BCLKRDY    (1 << 19)
36 
37 /* STATUS */
38 #define UART_RX_LVL     8
39 #define UART_TX_EM      (1 << 6)
40 #define UART_RX_FULL    (1 << 5)
41 #define UART_RX_EM      (1 << 4)
42 
43 /* PNR (Pin Control Register) */
44 #define UART_CTS        1
45 #define UART_RTS        (1 << 1)
46 
47 /* INT_EN / INT_FL */
48 #define UART_RX_THD     (1 << 4)
49 #define UART_TX_HE      (1 << 6)
50 
51 #define UART_RXBUFLEN   0x100
52 #define TYPE_MAX78000_UART "max78000-uart"
53 OBJECT_DECLARE_SIMPLE_TYPE(Max78000UartState, MAX78000_UART)
54 
55 struct Max78000UartState {
56     SysBusDevice parent_obj;
57 
58     MemoryRegion mmio;
59 
60     uint32_t ctrl;
61     uint32_t status;
62     uint32_t int_en;
63     uint32_t int_fl;
64     uint32_t clkdiv;
65     uint32_t osr;
66     uint32_t txpeek;
67     uint32_t pnr;
68     uint32_t fifo;
69     uint32_t dma;
70     uint32_t wken;
71     uint32_t wkfl;
72 
73     Fifo8 rx_fifo;
74 
75     CharBackend chr;
76     qemu_irq irq;
77 };
78 #endif /* HW_STM32F2XX_USART_H */
79