1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef PPC_XIVE2_H 10 #define PPC_XIVE2_H 11 12 #include "hw/ppc/xive.h" 13 #include "hw/ppc/xive2_regs.h" 14 #include "hw/sysbus.h" 15 16 /* 17 * XIVE2 Router (POWER10) 18 */ 19 typedef struct Xive2Router { 20 SysBusDevice parent; 21 22 XiveFabric *xfb; 23 } Xive2Router; 24 25 #define TYPE_XIVE2_ROUTER "xive2-router" 26 OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER); 27 28 /* 29 * Configuration flags 30 */ 31 32 #define XIVE2_GEN1_TIMA_OS 0x00000001 33 #define XIVE2_VP_SAVE_RESTORE 0x00000002 34 #define XIVE2_THREADID_8BITS 0x00000004 35 #define XIVE2_EN_VP_GRP_PRIORITY 0x00000008 36 #define XIVE2_VP_INT_PRIO 0x00000030 37 38 typedef struct Xive2RouterClass { 39 SysBusDeviceClass parent; 40 41 /* XIVE table accessors */ 42 int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 43 Xive2Eas *eas); 44 int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 45 uint8_t *pq); 46 int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 47 uint8_t *pq); 48 int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 49 Xive2End *end); 50 int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 51 Xive2End *end, uint8_t word_number); 52 int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 53 Xive2Nvp *nvp); 54 int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 55 Xive2Nvp *nvp, uint8_t word_number); 56 int (*get_nvgc)(Xive2Router *xrtr, bool crowd, 57 uint8_t nvgc_blk, uint32_t nvgc_idx, 58 Xive2Nvgc *nvgc); 59 int (*write_nvgc)(Xive2Router *xrtr, bool crowd, 60 uint8_t nvgc_blk, uint32_t nvgc_idx, 61 Xive2Nvgc *nvgc); 62 uint8_t (*get_block_id)(Xive2Router *xrtr); 63 uint32_t (*get_config)(Xive2Router *xrtr); 64 } Xive2RouterClass; 65 66 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 67 Xive2Eas *eas); 68 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 69 Xive2End *end); 70 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 71 Xive2End *end, uint8_t word_number); 72 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 73 Xive2Nvp *nvp); 74 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 75 Xive2Nvp *nvp, uint8_t word_number); 76 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 77 uint8_t nvgc_blk, uint32_t nvgc_idx, 78 Xive2Nvgc *nvgc); 79 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 80 uint8_t nvgc_blk, uint32_t nvgc_idx, 81 Xive2Nvgc *nvgc); 82 uint32_t xive2_router_get_config(Xive2Router *xrtr); 83 84 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); 85 void xive2_notify(Xive2Router *xrtr, uint32_t lisn, bool pq_checked); 86 87 /* 88 * XIVE2 Presenter (POWER10) 89 */ 90 91 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 92 uint8_t format, 93 uint8_t nvt_blk, uint32_t nvt_idx, 94 bool crowd, bool cam_ignore, 95 uint32_t logic_serv); 96 97 uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr, 98 uint8_t blk, uint32_t idx, 99 uint16_t offset); 100 101 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr, 102 bool crowd, 103 uint8_t blk, uint32_t idx, 104 uint16_t offset, uint16_t val); 105 106 /* 107 * XIVE2 END ESBs (POWER10) 108 */ 109 110 #define TYPE_XIVE2_END_SOURCE "xive2-end-source" 111 OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE) 112 113 typedef struct Xive2EndSource { 114 DeviceState parent; 115 116 uint32_t nr_ends; 117 118 /* ESB memory region */ 119 uint32_t esb_shift; 120 MemoryRegion esb_mmio; 121 122 Xive2Router *xrtr; 123 } Xive2EndSource; 124 125 /* 126 * XIVE2 Thread Interrupt Management Area (POWER10) 127 */ 128 129 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 130 hwaddr offset, uint64_t value, unsigned size); 131 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 132 hwaddr offset, uint64_t value, unsigned size); 133 void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 134 hwaddr offset, uint64_t value, unsigned size); 135 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 136 uint64_t value, unsigned size); 137 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 138 hwaddr offset, unsigned size); 139 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 140 hwaddr offset, uint64_t value, unsigned size); 141 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority); 142 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority); 143 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 144 hwaddr offset, uint64_t value, unsigned size); 145 void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 146 hwaddr offset, uint64_t value, unsigned size); 147 uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 148 hwaddr offset, unsigned size); 149 void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 150 hwaddr offset, uint64_t value, unsigned size); 151 uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 152 hwaddr offset, unsigned size); 153 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 154 hwaddr offset, uint64_t value, unsigned size); 155 void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, 156 hwaddr offset, uint64_t value, unsigned size); 157 #endif /* PPC_XIVE2_H */ 158