1 #include "qemu/osdep.h"
2 #include "hw/pci/pci.h"
3 #include "hw/qdev-properties.h"
4 #include "hw/virtio/virtio-gpu.h"
5 #include "qapi/error.h"
6 #include "qemu/module.h"
7 #include "virtio-vga.h"
8 #include "qom/object.h"
9
virtio_vga_base_invalidate_display(void * opaque)10 static void virtio_vga_base_invalidate_display(void *opaque)
11 {
12 VirtIOVGABase *vvga = opaque;
13 VirtIOGPUBase *g = vvga->vgpu;
14
15 if (g->enable) {
16 g->hw_ops->invalidate(g);
17 } else {
18 vvga->vga.hw_ops->invalidate(&vvga->vga);
19 }
20 }
21
virtio_vga_base_update_display(void * opaque)22 static void virtio_vga_base_update_display(void *opaque)
23 {
24 VirtIOVGABase *vvga = opaque;
25 VirtIOGPUBase *g = vvga->vgpu;
26
27 if (g->enable) {
28 g->hw_ops->gfx_update(g);
29 } else {
30 vvga->vga.hw_ops->gfx_update(&vvga->vga);
31 }
32 }
33
virtio_vga_base_text_update(void * opaque,console_ch_t * chardata)34 static void virtio_vga_base_text_update(void *opaque, console_ch_t *chardata)
35 {
36 VirtIOVGABase *vvga = opaque;
37 VirtIOGPUBase *g = vvga->vgpu;
38
39 if (g->enable) {
40 if (g->hw_ops->text_update) {
41 g->hw_ops->text_update(g, chardata);
42 }
43 } else {
44 if (vvga->vga.hw_ops->text_update) {
45 vvga->vga.hw_ops->text_update(&vvga->vga, chardata);
46 }
47 }
48 }
49
virtio_vga_base_ui_info(void * opaque,uint32_t idx,QemuUIInfo * info)50 static void virtio_vga_base_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
51 {
52 VirtIOVGABase *vvga = opaque;
53 VirtIOGPUBase *g = vvga->vgpu;
54
55 if (g->hw_ops->ui_info) {
56 g->hw_ops->ui_info(g, idx, info);
57 }
58 }
59
virtio_vga_base_gl_block(void * opaque,bool block)60 static void virtio_vga_base_gl_block(void *opaque, bool block)
61 {
62 VirtIOVGABase *vvga = opaque;
63 VirtIOGPUBase *g = vvga->vgpu;
64
65 if (g->hw_ops->gl_block) {
66 g->hw_ops->gl_block(g, block);
67 }
68 }
69
virtio_vga_base_get_flags(void * opaque)70 static int virtio_vga_base_get_flags(void *opaque)
71 {
72 VirtIOVGABase *vvga = opaque;
73 VirtIOGPUBase *g = vvga->vgpu;
74
75 return g->hw_ops->get_flags(g);
76 }
77
78 static const GraphicHwOps virtio_vga_base_ops = {
79 .get_flags = virtio_vga_base_get_flags,
80 .invalidate = virtio_vga_base_invalidate_display,
81 .gfx_update = virtio_vga_base_update_display,
82 .text_update = virtio_vga_base_text_update,
83 .ui_info = virtio_vga_base_ui_info,
84 .gl_block = virtio_vga_base_gl_block,
85 };
86
87 static const VMStateDescription vmstate_virtio_vga_base = {
88 .name = "virtio-vga",
89 .version_id = 2,
90 .minimum_version_id = 2,
91 .fields = (const VMStateField[]) {
92 /* no pci stuff here, saving the virtio device will handle that */
93 VMSTATE_STRUCT(vga, VirtIOVGABase, 0,
94 vmstate_vga_common, VGACommonState),
95 VMSTATE_END_OF_LIST()
96 }
97 };
98
99 /* VGA device wrapper around PCI device around virtio GPU */
virtio_vga_base_realize(VirtIOPCIProxy * vpci_dev,Error ** errp)100 static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
101 {
102 VirtIOVGABase *vvga = VIRTIO_VGA_BASE(vpci_dev);
103 VirtIOGPUBase *g = vvga->vgpu;
104 VGACommonState *vga = &vvga->vga;
105 uint32_t offset;
106 int i;
107
108 /* init vga compat bits */
109 vga->vram_size_mb = 8;
110 if (!vga_common_init(vga, OBJECT(vpci_dev), errp)) {
111 return;
112 }
113 vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
114 pci_address_space_io(&vpci_dev->pci_dev), true);
115 pci_register_bar(&vpci_dev->pci_dev, 0,
116 PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
117
118 vpci_dev->modern_io_bar_idx = 5;
119
120 if (!virtio_gpu_hostmem_enabled(g->conf)) {
121 /*
122 * Configure virtio bar and regions
123 *
124 * We use bar #2 for the mmio regions, to be compatible with stdvga.
125 * virtio regions are moved to the end of bar #2, to make room for
126 * the stdvga mmio registers at the start of bar #2.
127 */
128 vpci_dev->modern_mem_bar_idx = 2;
129 vpci_dev->msix_bar_idx = 4;
130 } else {
131 vpci_dev->msix_bar_idx = 1;
132 vpci_dev->modern_mem_bar_idx = 2;
133 memory_region_init(&g->hostmem, OBJECT(g), "virtio-gpu-hostmem",
134 g->conf.hostmem);
135 pci_register_bar(&vpci_dev->pci_dev, 4,
136 PCI_BASE_ADDRESS_SPACE_MEMORY |
137 PCI_BASE_ADDRESS_MEM_PREFETCH |
138 PCI_BASE_ADDRESS_MEM_TYPE_64,
139 &g->hostmem);
140 virtio_pci_add_shm_cap(vpci_dev, 4, 0, g->conf.hostmem,
141 VIRTIO_GPU_SHM_ID_HOST_VISIBLE);
142 }
143
144 if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) {
145 /*
146 * with page-per-vq=off there is no padding space we can use
147 * for the stdvga registers. Make the common and isr regions
148 * smaller then.
149 */
150 vpci_dev->common.size /= 2;
151 vpci_dev->isr.size /= 2;
152 }
153
154 offset = memory_region_size(&vpci_dev->modern_bar);
155 offset -= vpci_dev->notify.size;
156 vpci_dev->notify.offset = offset;
157 offset -= vpci_dev->device.size;
158 vpci_dev->device.offset = offset;
159 offset -= vpci_dev->isr.size;
160 vpci_dev->isr.offset = offset;
161 offset -= vpci_dev->common.size;
162 vpci_dev->common.offset = offset;
163
164 /* init virtio bits */
165 virtio_pci_force_virtio_1(vpci_dev);
166 if (!qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), errp)) {
167 return;
168 }
169
170 /* add stdvga mmio regions */
171 pci_std_vga_mmio_region_init(vga, OBJECT(vvga), &vpci_dev->modern_bar,
172 vvga->vga_mrs, true, false);
173
174 vga->con = g->scanout[0].con;
175 graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga);
176
177 for (i = 0; i < g->conf.max_outputs; i++) {
178 object_property_set_link(OBJECT(g->scanout[i].con), "device",
179 OBJECT(vpci_dev), &error_abort);
180 }
181 }
182
virtio_vga_base_reset_hold(Object * obj,ResetType type)183 static void virtio_vga_base_reset_hold(Object *obj, ResetType type)
184 {
185 VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj);
186 VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj);
187
188 /* reset virtio-gpu */
189 if (klass->parent_phases.hold) {
190 klass->parent_phases.hold(obj, type);
191 }
192
193 /* reset vga */
194 vga_common_reset(&vvga->vga);
195 vga_dirty_log_start(&vvga->vga);
196 }
197
virtio_vga_get_big_endian_fb(Object * obj,Error ** errp)198 static bool virtio_vga_get_big_endian_fb(Object *obj, Error **errp)
199 {
200 VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
201
202 return d->vga.big_endian_fb;
203 }
204
virtio_vga_set_big_endian_fb(Object * obj,bool value,Error ** errp)205 static void virtio_vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
206 {
207 VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
208
209 d->vga.big_endian_fb = value;
210 }
211
212 static Property virtio_vga_base_properties[] = {
213 DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
214 DEFINE_PROP_END_OF_LIST(),
215 };
216
virtio_vga_base_class_init(ObjectClass * klass,void * data)217 static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
218 {
219 DeviceClass *dc = DEVICE_CLASS(klass);
220 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
221 VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
222 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
223 ResettableClass *rc = RESETTABLE_CLASS(klass);
224
225 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
226 device_class_set_props(dc, virtio_vga_base_properties);
227 dc->vmsd = &vmstate_virtio_vga_base;
228 dc->hotpluggable = false;
229 resettable_class_set_parent_phases(rc, NULL, virtio_vga_base_reset_hold,
230 NULL, &v->parent_phases);
231
232 k->realize = virtio_vga_base_realize;
233 pcidev_k->romfile = "vgabios-virtio.bin";
234 pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
235
236 /* Expose framebuffer byteorder via QOM */
237 object_class_property_add_bool(klass, "big-endian-framebuffer",
238 virtio_vga_get_big_endian_fb,
239 virtio_vga_set_big_endian_fb);
240 }
241
242 static const TypeInfo virtio_vga_base_info = {
243 .name = TYPE_VIRTIO_VGA_BASE,
244 .parent = TYPE_VIRTIO_PCI,
245 .instance_size = sizeof(VirtIOVGABase),
246 .class_size = sizeof(VirtIOVGABaseClass),
247 .class_init = virtio_vga_base_class_init,
248 .abstract = true,
249 };
250 module_obj(TYPE_VIRTIO_VGA_BASE);
251 module_kconfig(VIRTIO_VGA);
252
253 #define TYPE_VIRTIO_VGA "virtio-vga"
254
255 typedef struct VirtIOVGA VirtIOVGA;
256 DECLARE_INSTANCE_CHECKER(VirtIOVGA, VIRTIO_VGA,
257 TYPE_VIRTIO_VGA)
258
259 struct VirtIOVGA {
260 VirtIOVGABase parent_obj;
261
262 VirtIOGPU vdev;
263 };
264
virtio_vga_inst_initfn(Object * obj)265 static void virtio_vga_inst_initfn(Object *obj)
266 {
267 VirtIOVGA *dev = VIRTIO_VGA(obj);
268
269 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
270 TYPE_VIRTIO_GPU);
271 VIRTIO_VGA_BASE(dev)->vgpu = VIRTIO_GPU_BASE(&dev->vdev);
272 }
273
274
275 static VirtioPCIDeviceTypeInfo virtio_vga_info = {
276 .generic_name = TYPE_VIRTIO_VGA,
277 .parent = TYPE_VIRTIO_VGA_BASE,
278 .instance_size = sizeof(VirtIOVGA),
279 .instance_init = virtio_vga_inst_initfn,
280 };
281 module_obj(TYPE_VIRTIO_VGA);
282
virtio_vga_register_types(void)283 static void virtio_vga_register_types(void)
284 {
285 type_register_static(&virtio_vga_base_info);
286 virtio_pci_types_register(&virtio_vga_info);
287 }
288
289 type_init(virtio_vga_register_types)
290