xref: /openbmc/qemu/include/hw/southbridge/piix.h (revision ac433035)
1 /*
2  * QEMU PIIX South Bridge Emulation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  * Copyright (c) 2018 Hervé Poussineau
6  *
7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
8  * See the COPYING file in the top-level directory.
9  *
10  */
11 
12 #ifndef HW_SOUTHBRIDGE_PIIX_H
13 #define HW_SOUTHBRIDGE_PIIX_H
14 
15 #include "hw/pci/pci_device.h"
16 #include "hw/acpi/piix4.h"
17 #include "hw/ide/pci.h"
18 #include "hw/rtc/mc146818rtc.h"
19 #include "hw/usb/hcd-uhci.h"
20 
21 /* PIRQRC[A:D]: PIRQx Route Control Registers */
22 #define PIIX_PIRQCA 0x60
23 #define PIIX_PIRQCB 0x61
24 #define PIIX_PIRQCC 0x62
25 #define PIIX_PIRQCD 0x63
26 
27 /*
28  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
29  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
30  */
31 #define PIIX_RCR_IOPORT 0xcf9
32 
33 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
34 
35 struct PIIXState {
36     PCIDevice dev;
37 
38     /*
39      * bitmap to track pic levels.
40      * The pic level is the logical OR of all the PCI irqs mapped to it
41      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
42      *
43      * PIRQ is mapped to PIC pins, we track it by
44      * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
45      * pic_irq * PIIX_NUM_PIRQS + pirq
46      */
47 #if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
48 #error "unable to encode pic state in 64bit in pic_levels."
49 #endif
50     uint64_t pic_levels;
51 
52     qemu_irq cpu_intr;
53     qemu_irq isa_irqs_in[ISA_NUM_IRQS];
54 
55     /* This member isn't used. Just for save/load compatibility */
56     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
57 
58     MC146818RtcState rtc;
59     PCIIDEState ide;
60     UHCIState uhci;
61     PIIX4PMState pm;
62 
63     uint32_t smb_io_base;
64 
65     /* Reset Control Register contents */
66     uint8_t rcr;
67 
68     /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
69     MemoryRegion rcr_mem;
70 
71     bool has_acpi;
72     bool has_pic;
73     bool has_pit;
74     bool has_usb;
75     bool smm_enabled;
76 };
77 
78 #define TYPE_PIIX_PCI_DEVICE "pci-piix"
79 OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
80 
81 #define TYPE_PIIX3_DEVICE "PIIX3"
82 #define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
83 
84 #endif
85