xref: /openbmc/qemu/include/hw/net/allwinner_emac.h (revision c122bca9)
1 /*
2  * Emulation of Allwinner EMAC Fast Ethernet controller and
3  * Realtek RTL8201CP PHY
4  *
5  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6  *
7  * Allwinner EMAC register definitions from Linux kernel are:
8  *   Copyright 2012 Stefan Roese <sr@denx.de>
9  *   Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
10  *   Copyright 1997 Sten Wang
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License
14  * version 2 as published by the Free Software Foundation.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  */
22 
23 #ifndef ALLWINNER_EMAC_H
24 #define ALLWINNER_EMAC_H
25 
26 #include "qemu/units.h"
27 #include "net/net.h"
28 #include "qemu/fifo8.h"
29 #include "hw/net/mii.h"
30 #include "hw/sysbus.h"
31 #include "qom/object.h"
32 
33 #define TYPE_AW_EMAC "allwinner-emac"
34 OBJECT_DECLARE_SIMPLE_TYPE(AwEmacState, AW_EMAC)
35 
36 /*
37  * Allwinner EMAC register list
38  */
39 #define EMAC_CTL_REG            0x00
40 
41 #define EMAC_TX_MODE_REG        0x04
42 #define EMAC_TX_FLOW_REG        0x08
43 #define EMAC_TX_CTL0_REG        0x0C
44 #define EMAC_TX_CTL1_REG        0x10
45 #define EMAC_TX_INS_REG         0x14
46 #define EMAC_TX_PL0_REG         0x18
47 #define EMAC_TX_PL1_REG         0x1C
48 #define EMAC_TX_STA_REG         0x20
49 #define EMAC_TX_IO_DATA_REG     0x24
50 #define EMAC_TX_IO_DATA1_REG    0x28
51 #define EMAC_TX_TSVL0_REG       0x2C
52 #define EMAC_TX_TSVH0_REG       0x30
53 #define EMAC_TX_TSVL1_REG       0x34
54 #define EMAC_TX_TSVH1_REG       0x38
55 
56 #define EMAC_RX_CTL_REG         0x3C
57 #define EMAC_RX_HASH0_REG       0x40
58 #define EMAC_RX_HASH1_REG       0x44
59 #define EMAC_RX_STA_REG         0x48
60 #define EMAC_RX_IO_DATA_REG     0x4C
61 #define EMAC_RX_FBC_REG         0x50
62 
63 #define EMAC_INT_CTL_REG        0x54
64 #define EMAC_INT_STA_REG        0x58
65 
66 #define EMAC_MAC_CTL0_REG       0x5C
67 #define EMAC_MAC_CTL1_REG       0x60
68 #define EMAC_MAC_IPGT_REG       0x64
69 #define EMAC_MAC_IPGR_REG       0x68
70 #define EMAC_MAC_CLRT_REG       0x6C
71 #define EMAC_MAC_MAXF_REG       0x70
72 #define EMAC_MAC_SUPP_REG       0x74
73 #define EMAC_MAC_TEST_REG       0x78
74 #define EMAC_MAC_MCFG_REG       0x7C
75 #define EMAC_MAC_MCMD_REG       0x80
76 #define EMAC_MAC_MADR_REG       0x84
77 #define EMAC_MAC_MWTD_REG       0x88
78 #define EMAC_MAC_MRDD_REG       0x8C
79 #define EMAC_MAC_MIND_REG       0x90
80 #define EMAC_MAC_SSRR_REG       0x94
81 #define EMAC_MAC_A0_REG         0x98
82 #define EMAC_MAC_A1_REG         0x9C
83 #define EMAC_MAC_A2_REG         0xA0
84 
85 #define EMAC_SAFX_L_REG0        0xA4
86 #define EMAC_SAFX_H_REG0        0xA8
87 #define EMAC_SAFX_L_REG1        0xAC
88 #define EMAC_SAFX_H_REG1        0xB0
89 #define EMAC_SAFX_L_REG2        0xB4
90 #define EMAC_SAFX_H_REG2        0xB8
91 #define EMAC_SAFX_L_REG3        0xBC
92 #define EMAC_SAFX_H_REG3        0xC0
93 
94 /* CTL register fields */
95 #define EMAC_CTL_RESET                  (1 << 0)
96 #define EMAC_CTL_TX_EN                  (1 << 1)
97 #define EMAC_CTL_RX_EN                  (1 << 2)
98 
99 /* TX MODE register fields */
100 #define EMAC_TX_MODE_ABORTED_FRAME_EN   (1 << 0)
101 #define EMAC_TX_MODE_DMA_EN             (1 << 1)
102 
103 /* RX CTL register fields */
104 #define EMAC_RX_CTL_AUTO_DRQ_EN         (1 << 1)
105 #define EMAC_RX_CTL_DMA_EN              (1 << 2)
106 #define EMAC_RX_CTL_PASS_ALL_EN         (1 << 4)
107 #define EMAC_RX_CTL_PASS_CTL_EN         (1 << 5)
108 #define EMAC_RX_CTL_PASS_CRC_ERR_EN     (1 << 6)
109 #define EMAC_RX_CTL_PASS_LEN_ERR_EN     (1 << 7)
110 #define EMAC_RX_CTL_PASS_LEN_OOR_EN     (1 << 8)
111 #define EMAC_RX_CTL_ACCEPT_UNICAST_EN   (1 << 16)
112 #define EMAC_RX_CTL_DA_FILTER_EN        (1 << 17)
113 #define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20)
114 #define EMAC_RX_CTL_HASH_FILTER_EN      (1 << 21)
115 #define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22)
116 #define EMAC_RX_CTL_SA_FILTER_EN        (1 << 24)
117 #define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25)
118 
119 /* RX IO DATA register fields */
120 #define EMAC_RX_HEADER(len, status)     (((len) & 0xffff) | ((status) << 16))
121 #define EMAC_RX_IO_DATA_STATUS_CRC_ERR  (1 << 4)
122 #define EMAC_RX_IO_DATA_STATUS_LEN_ERR  (3 << 5)
123 #define EMAC_RX_IO_DATA_STATUS_OK       (1 << 7)
124 #define EMAC_UNDOCUMENTED_MAGIC         0x0143414d  /* header for RX frames */
125 
126 /* INT CTL and INT STA registers fields */
127 #define EMAC_INT_TX_CHAN(x) (1 << (x))
128 #define EMAC_INT_RX         (1 << 8)
129 
130 /* Due to lack of specifications, size of fifos is chosen arbitrarily */
131 #define TX_FIFO_SIZE        (4 * KiB)
132 #define RX_FIFO_SIZE        (32 * KiB)
133 
134 #define NUM_TX_FIFOS        2
135 #define RX_HDR_SIZE         8
136 #define CRC_SIZE            4
137 
138 #define PHY_REG_SHIFT       0
139 #define PHY_ADDR_SHIFT      8
140 
141 typedef struct RTL8201CPState {
142     uint16_t bmcr;
143     uint16_t bmsr;
144     uint16_t anar;
145     uint16_t anlpar;
146 } RTL8201CPState;
147 
148 struct AwEmacState {
149     /*< private >*/
150     SysBusDevice  parent_obj;
151     /*< public >*/
152 
153     MemoryRegion   iomem;
154     qemu_irq       irq;
155     NICState       *nic;
156     NICConf        conf;
157     RTL8201CPState mii;
158     uint8_t        phy_addr;
159 
160     uint32_t       ctl;
161     uint32_t       tx_mode;
162     uint32_t       rx_ctl;
163     uint32_t       int_ctl;
164     uint32_t       int_sta;
165     uint32_t       phy_target;
166 
167     Fifo8          rx_fifo;
168     uint32_t       rx_num_packets;
169     uint32_t       rx_packet_size;
170     uint32_t       rx_packet_pos;
171 
172     Fifo8          tx_fifo[NUM_TX_FIFOS];
173     uint32_t       tx_length[NUM_TX_FIFOS];
174     uint32_t       tx_channel;
175 };
176 
177 #endif
178