1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 #include "qom/object.h" 16 17 #define TYPE_ASPEED_SCU "aspeed.scu" 18 OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU) 19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700" 23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700" 24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030" 25 26 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 27 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) 28 #define ASPEED_AST2700_SCU_NR_REGS (0xE20 >> 2) 29 30 struct AspeedSCUState { 31 /*< private >*/ 32 SysBusDevice parent_obj; 33 34 /*< public >*/ 35 MemoryRegion iomem; 36 37 uint32_t regs[ASPEED_AST2700_SCU_NR_REGS]; 38 uint32_t silicon_rev; 39 uint32_t hw_strap1; 40 uint32_t hw_strap2; 41 uint32_t hw_prot_key; 42 43 MemoryRegion *ssp_sdram_remap1; 44 MemoryRegion *ssp_sdram_remap2; 45 MemoryRegion *tsp_sdram_remap; 46 }; 47 48 #define AST2400_A0_SILICON_REV 0x02000303U 49 #define AST2400_A1_SILICON_REV 0x02010303U 50 #define AST2500_A0_SILICON_REV 0x04000303U 51 #define AST2500_A1_SILICON_REV 0x04010303U 52 #define AST2600_A0_SILICON_REV 0x05000303U 53 #define AST2600_A1_SILICON_REV 0x05010303U 54 #define AST2600_A2_SILICON_REV 0x05020303U 55 #define AST2600_A3_SILICON_REV 0x05030303U 56 #define AST1030_A0_SILICON_REV 0x80000000U 57 #define AST1030_A1_SILICON_REV 0x80010000U 58 #define AST2700_A0_SILICON_REV 0x06000103U 59 #define AST2720_A0_SILICON_REV 0x06000203U 60 #define AST2750_A0_SILICON_REV 0x06000003U 61 #define AST2700_A1_SILICON_REV 0x06010103U 62 #define AST2750_A1_SILICON_REV 0x06010003U 63 64 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 65 66 bool is_supported_silicon_rev(uint32_t silicon_rev); 67 68 69 struct AspeedSCUClass { 70 SysBusDeviceClass parent_class; 71 72 const uint32_t *resets; 73 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 74 uint32_t (*get_apb)(AspeedSCUState *s); 75 uint32_t apb_divider; 76 uint32_t nr_regs; 77 bool clkin_25Mhz; 78 const MemoryRegionOps *ops; 79 }; 80 81 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 82 83 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 84 85 /* 86 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 87 * were added. 88 * 89 * Original header file : 90 * arch/arm/mach-aspeed/include/mach/regs-scu.h 91 * 92 * Copyright (C) 2012-2020 ASPEED Technology Inc. 93 * 94 * This program is free software; you can redistribute it and/or modify 95 * it under the terms of the GNU General Public License version 2 as 96 * published by the Free Software Foundation. 97 * 98 * History : 99 * 1. 2012/12/29 Ryan Chen Create 100 */ 101 102 /* 103 * SCU08 Clock Selection Register 104 * 105 * 31 Enable Video Engine clock dynamic slow down 106 * 30:28 Video Engine clock slow down setting 107 * 27 2D Engine GCLK clock source selection 108 * 26 2D Engine GCLK clock throttling enable 109 * 25:23 APB PCLK divider selection 110 * 22:20 LPC Host LHCLK divider selection 111 * 19 LPC Host LHCLK clock generation/output enable control 112 * 18:16 MAC AHB bus clock divider selection 113 * 15 SD/SDIO clock running enable 114 * 14:12 SD/SDIO divider selection 115 * 11 Reserved 116 * 10:8 Video port output clock delay control bit 117 * 7 ARM CPU/AHB clock slow down enable 118 * 6:4 ARM CPU/AHB clock slow down setting 119 * 3:2 ECLK clock source selection 120 * 1 CPU/AHB clock slow down idle timer 121 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 122 */ 123 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 124 125 /* 126 * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 127 * 128 * 18 H-PLL parameter selection 129 * 0: Select H-PLL by strapping resistors 130 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 131 * 17 Enable H-PLL bypass mode 132 * 16 Turn off H-PLL 133 * 10:5 H-PLL Numerator 134 * 4 H-PLL Output Divider 135 * 3:0 H-PLL Denumerator 136 * 137 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 138 */ 139 140 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 141 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 142 #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 143 144 /* 145 * SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 146 * 147 * 21 Enable H-PLL reset 148 * 20 Enable H-PLL bypass mode 149 * 19 Turn off H-PLL 150 * 18:13 H-PLL Post Divider 151 * 12:5 H-PLL Numerator (M) 152 * 4:0 H-PLL Denumerator (N) 153 * 154 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 155 * 156 * The default frequency is 792Mhz when CLKIN = 24MHz 157 */ 158 159 #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 160 #define SCU_H_PLL_OFF (0x1 << 19) 161 162 /* 163 * SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 164 * 165 * 31:29 Software defined strapping registers 166 * 28:27 DRAM size setting (for VGA driver use) 167 * 26:24 DRAM configuration setting 168 * 23 Enable 25 MHz reference clock input 169 * 22 Enable GPIOE pass-through mode 170 * 21 Enable GPIOD pass-through mode 171 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 172 * 19 Disable ACPI function 173 * 23,18 Clock source selection 174 * 17 Enable BMC 2nd boot watchdog timer 175 * 16 SuperIO configuration address selection 176 * 15 VGA Class Code selection 177 * 14 Enable LPC dedicated reset pin function 178 * 13:12 SPI mode selection 179 * 11:10 CPU/AHB clock frequency ratio selection 180 * 9:8 H-PLL default clock frequency selection 181 * 7 Define MAC#2 interface 182 * 6 Define MAC#1 interface 183 * 5 Enable VGA BIOS ROM 184 * 4 Boot flash memory extended option 185 * 3:2 VGA memory size selection 186 * 1:0 BMC CPU boot code selection 187 */ 188 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 189 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 190 191 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 192 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 193 #define DRAM_SIZE_64MB 0 194 #define DRAM_SIZE_128MB 1 195 #define DRAM_SIZE_256MB 2 196 #define DRAM_SIZE_512MB 3 197 198 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 199 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 200 201 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 202 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 203 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 204 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 205 206 /* bit 23, 18 [1,0] */ 207 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 208 | (((x) & 0x1) << 18)) 209 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 210 | (((x) >> 18) & 0x1)) 211 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 212 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 213 #define AST2400_CLK_24M_IN 0 214 #define AST2400_CLK_48M_IN 1 215 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 216 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 217 218 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 219 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 220 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 221 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 222 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 223 224 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 225 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 226 #define SCU_HW_STRAP_SPI_DIS 0 227 #define SCU_HW_STRAP_SPI_MASTER 1 228 #define SCU_HW_STRAP_SPI_M_S_EN 2 229 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 230 231 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 232 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 233 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 234 #define AST2400_CPU_AHB_RATIO_1_1 0 235 #define AST2400_CPU_AHB_RATIO_2_1 1 236 #define AST2400_CPU_AHB_RATIO_4_1 2 237 #define AST2400_CPU_AHB_RATIO_3_1 3 238 239 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 240 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 241 #define AST2400_CPU_384MHZ 0 242 #define AST2400_CPU_360MHZ 1 243 #define AST2400_CPU_336MHZ 2 244 #define AST2400_CPU_408MHZ 3 245 246 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 247 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 248 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 249 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 250 251 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 252 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 253 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 254 #define VGA_8M_DRAM 0 255 #define VGA_16M_DRAM 1 256 #define VGA_32M_DRAM 2 257 #define VGA_64M_DRAM 3 258 259 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 260 #define AST2400_NOR_BOOT 0 261 #define AST2400_NAND_BOOT 1 262 #define AST2400_SPI_BOOT 2 263 #define AST2400_DIS_BOOT 3 264 265 /* 266 * SCU70 Hardware strapping register definition (for Aspeed AST2500 267 * SoC and higher) 268 * 269 * 31 Enable SPI Flash Strap Auto Fetch Mode 270 * 30 Enable GPIO Strap Mode 271 * 29 Select UART Debug Port 272 * 28 Reserved (1) 273 * 27 Enable fast reset mode for ARM ICE debugger 274 * 26 Enable eSPI flash mode 275 * 25 Enable eSPI mode 276 * 24 Select DDR4 SDRAM 277 * 23 Select 25 MHz reference clock input mode 278 * 22 Enable GPIOE pass-through mode 279 * 21 Enable GPIOD pass-through mode 280 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 281 * 19 Enable ACPI function 282 * 18 Select USBCKI input frequency 283 * 17 Enable BMC 2nd boot watchdog timer 284 * 16 SuperIO configuration address selection 285 * 15 VGA Class Code selection 286 * 14 Select dedicated LPC reset input 287 * 13:12 SPI mode selection 288 * 11:9 AXI/AHB clock frequency ratio selection 289 * 8 Reserved (0) 290 * 7 Define MAC#2 interface 291 * 6 Define MAC#1 interface 292 * 5 Enable dedicated VGA BIOS ROM 293 * 4 Reserved (0) 294 * 3:2 VGA memory size selection 295 * 1 Reserved (1) 296 * 0 Disable CPU boot 297 */ 298 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 299 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 300 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 301 #define UART_DEBUG_UART1 0 302 #define UART_DEBUG_UART5 1 303 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 304 305 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 306 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 307 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 308 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 309 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) 310 311 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 312 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 313 #define USBCKI_FREQ_24MHZ 0 314 #define USBCKI_FREQ_28MHZ 1 315 316 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 317 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 318 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 319 #define AXI_AHB_RATIO_UNDEFINED 0 320 #define AXI_AHB_RATIO_2_1 1 321 #define AXI_AHB_RATIO_3_1 2 322 #define AXI_AHB_RATIO_4_1 3 323 #define AXI_AHB_RATIO_5_1 4 324 #define AXI_AHB_RATIO_6_1 5 325 #define AXI_AHB_RATIO_7_1 6 326 #define AXI_AHB_RATIO_8_1 7 327 328 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 329 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 330 331 #define AST2500_HW_STRAP1_DEFAULTS ( \ 332 SCU_AST2500_HW_STRAP_RESERVED28 | \ 333 SCU_HW_STRAP_2ND_BOOT_WDT | \ 334 SCU_HW_STRAP_VGA_CLASS_CODE | \ 335 SCU_HW_STRAP_LPC_RESET_PIN | \ 336 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 337 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 338 SCU_AST2500_HW_STRAP_RESERVED1) 339 340 /* 341 * SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC) 342 * 343 * 28:26 H-PLL Parameters 344 * 25 Enable H-PLL reset 345 * 24 Enable H-PLL bypass mode 346 * 23 Turn off H-PLL 347 * 22:19 H-PLL Post Divider (P) 348 * 18:13 H-PLL Numerator (M) 349 * 12:0 H-PLL Denumerator (N) 350 * 351 * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) 352 * 353 * The default frequency is 1200Mhz when CLKIN = 25MHz 354 */ 355 #define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) 356 #define SCU_AST2600_H_PLL_OFF (0x1 << 23) 357 358 /* STRAP1 SCU500 */ 359 #define SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC (0x1 << 2) 360 #define SCU_AST2600_HW_STRAP_BOOT_SRC_SPI (0x0 << 2) 361 362 /* 363 * SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC) 364 * 365 * 31 I3C Clock Source selection 366 * 30:28 I3C clock divider selection 367 * 26:24 MAC AHB clock divider selection 368 * 22:20 RGMII 125MHz clock divider ration 369 * 19:16 RGMII 50MHz clock divider ration 370 * 15 LHCLK clock generation/output enable control 371 * 14:12 LHCLK divider selection 372 * 11:8 APB Bus PCLK divider selection 373 * 7 Select PECI clock source 374 * 6 Select UART debug port clock source 375 * 5 Select UART6 clock source 376 * 4 Select UART5 clock source 377 * 3 Select UART4 clock source 378 * 2 Select UART3 clock source 379 * 1 Select UART2 clock source 380 * 0 Select UART1 clock source 381 */ 382 #define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf) 383 384 /* 385 * SCU280 Clock Selection 1 Register (for Aspeed AST2700 SCUIO) 386 * 387 * 31:29 MHCLK_DIV 388 * 28 Reserved 389 * 27:25 RGMIICLK_DIV 390 * 24 Reserved 391 * 23:21 RMIICLK_DIV 392 * 20:18 PCLK_DIV 393 * 17:14 SDCLK_DIV 394 * 13 SDCLK_SEL 395 * 12 UART13CLK_SEL 396 * 11 UART12CLK_SEL 397 * 10 UART11CLK_SEL 398 * 9 UART10CLK_SEL 399 * 8 UART9CLK_SEL 400 * 7 UART8CLK_SEL 401 * 6 UART7CLK_SEL 402 * 5 UART6CLK_SEL 403 * 4 UARTDBCLK_SEL 404 * 3 UART4CLK_SEL 405 * 2 UART3CLK_SEL 406 * 1 UART2CLK_SEL 407 * 0 UART1CLK_SEL 408 */ 409 #define SCUIO_AST2700_CLK_GET_PCLK_DIV(x) (((x) >> 18) & 0x7) 410 411 #endif /* ASPEED_SCU_H */ 412