xref: /openbmc/linux/drivers/net/ethernet/apple/bmac.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1  /* SPDX-License-Identifier: GPL-2.0-or-later */
2  /*
3   * mace.h - definitions for the registers in the "Big Mac"
4   *  Ethernet controller found in PowerMac G3 models.
5   *
6   * Copyright (C) 1998 Randy Gobbel.
7   */
8  
9  /* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal"
10   * (HME) controller.  See sunhme.h
11   */
12  
13  
14  /* register offsets */
15  
16  /* global status and control */
17  #define	XIFC		0x000   /* low-level interface control */
18  #	define	TxOutputEnable	0x0001 /* output driver enable */
19  #	define	XIFLoopback	0x0002 /* Loopback-mode XIF enable */
20  #	define	MIILoopback	0x0004 /* Loopback-mode MII enable */
21  #	define	MIILoopbackBits	0x0006
22  #	define	MIIBuffDisable	0x0008 /* MII receive buffer disable */
23  #	define	SQETestEnable	0x0010 /* SQE test enable */
24  #	define	SQETimeWindow	0x03e0 /* SQE time window */
25  #	define	XIFLanceMode	0x0010 /* Lance mode enable */
26  #	define	XIFLanceIPG0	0x03e0 /* Lance mode IPG0 */
27  #define	TXFIFOCSR	0x100   /* transmit FIFO control */
28  #	define	TxFIFOEnable	0x0001
29  #define	TXTH		0x110   /* transmit threshold */
30  #	define	TxThreshold	0x0004
31  #define RXFIFOCSR	0x120   /* receive FIFO control */
32  #	define	RxFIFOEnable	0x0001
33  #define MEMADD		0x130   /* memory address, unknown function */
34  #define MEMDATAHI	0x140   /* memory data high, presently unused in driver */
35  #define MEMDATALO	0x150   /* memory data low, presently unused in driver */
36  #define XCVRIF		0x160   /* transceiver interface control */
37  #	define	COLActiveLow	0x0002
38  #	define	SerialMode	0x0004
39  #	define	ClkBit		0x0008
40  #	define	LinkStatus	0x0100
41  #define CHIPID          0x170   /* chip ID */
42  #define	MIFCSR		0x180   /* ??? */
43  #define	SROMCSR		0x190   /* SROM control */
44  #	define	ChipSelect	0x0001
45  #	define	Clk		0x0002
46  #define TXPNTR		0x1a0   /* transmit pointer */
47  #define	RXPNTR		0x1b0   /* receive pointer */
48  #define	STATUS		0x200   /* status--reading this clears it */
49  #define	INTDISABLE	0x210   /* interrupt enable/disable control */
50  /* bits below are the same in both STATUS and INTDISABLE registers */
51  #	define	FrameReceived	0x00000001 /* Received a frame */
52  #	define	RxFrameCntExp	0x00000002 /* Receive frame counter expired */
53  #	define	RxAlignCntExp	0x00000004 /* Align-error counter expired */
54  #	define	RxCRCCntExp	0x00000008 /* CRC-error counter expired */
55  #	define	RxLenCntExp	0x00000010 /* Length-error counter expired */
56  #	define	RxOverFlow	0x00000020 /* Receive FIFO overflow */
57  #	define	RxCodeViolation	0x00000040 /* Code-violation counter expired */
58  #	define	SQETestError	0x00000080 /* Test error in XIF for SQE */
59  #	define	FrameSent	0x00000100 /* Transmitted a frame */
60  #	define	TxUnderrun	0x00000200 /* Transmit FIFO underrun */
61  #	define	TxMaxSizeError	0x00000400 /* Max-packet size error */
62  #	define	TxNormalCollExp	0x00000800 /* Normal-collision counter expired */
63  #	define	TxExcessCollExp	0x00001000 /* Excess-collision counter expired */
64  #	define	TxLateCollExp	0x00002000 /* Late-collision counter expired */
65  #	define	TxNetworkCollExp 0x00004000 /* First-collision counter expired */
66  #	define	TxDeferTimerExp	0x00008000 /* Defer-timer expired */
67  #	define	RxFIFOToHost	0x00010000 /* Data moved from FIFO to host */
68  #	define	RxNoDescriptors	0x00020000 /* No more receive descriptors */
69  #	define	RxDMAError	0x00040000 /* Error during receive DMA */
70  #	define	RxDMALateErr	0x00080000 /* Receive DMA, data late */
71  #	define	RxParityErr	0x00100000 /* Parity error during receive DMA */
72  #	define	RxTagError	0x00200000 /* Tag error during receive DMA */
73  #	define	TxEOPError	0x00400000 /* Tx descriptor did not have EOP set */
74  #	define	MIFIntrEvent	0x00800000 /* MIF is signaling an interrupt */
75  #	define	TxHostToFIFO	0x01000000 /* Data moved from host to FIFO  */
76  #	define	TxFIFOAllSent	0x02000000 /* Transmitted all packets in FIFO */
77  #	define	TxDMAError	0x04000000 /* Error during transmit DMA */
78  #	define	TxDMALateError	0x08000000 /* Late error during transmit DMA */
79  #	define	TxParityError	0x10000000 /* Parity error during transmit DMA */
80  #	define	TxTagError	0x20000000 /* Tag error during transmit DMA */
81  #	define	PIOError	0x40000000 /* PIO access got an error */
82  #	define	PIOParityError	0x80000000 /* PIO access got a parity error  */
83  #	define	DisableAll	0xffffffff
84  #	define	EnableAll	0x00000000
85  /* #	define	NormalIntEvents	~(FrameReceived | FrameSent | TxUnderrun) */
86  #	define	EnableNormal	~(FrameReceived | FrameSent)
87  #	define	EnableErrors	(FrameReceived | FrameSent)
88  #	define	RxErrorMask	(RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \
89  				 RxLenCntExp | RxOverFlow | RxCodeViolation)
90  #	define	TxErrorMask	(TxUnderrun | TxMaxSizeError | TxExcessCollExp | \
91  				 TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp)
92  
93  /* transmit control */
94  #define	TXRST		0x420   /* transmit reset */
95  #	define	TxResetBit	0x0001
96  #define	TXCFG		0x430   /* transmit configuration control*/
97  #	define	TxMACEnable	0x0001 /* output driver enable */
98  #	define	TxSlowMode	0x0020 /* enable slow mode */
99  #	define	TxIgnoreColl	0x0040 /* ignore transmit collisions */
100  #	define	TxNoFCS		0x0080 /* do not emit FCS */
101  #	define	TxNoBackoff	0x0100 /* no backoff in case of collisions */
102  #	define	TxFullDuplex	0x0200 /* enable full-duplex */
103  #	define	TxNeverGiveUp	0x0400 /* don't give up on transmits */
104  #define IPG1		0x440   /* Inter-packet gap 1 */
105  #define IPG2		0x450   /* Inter-packet gap 2 */
106  #define ALIMIT		0x460   /* Transmit attempt limit */
107  #define SLOT		0x470   /* Transmit slot time */
108  #define PALEN		0x480   /* Size of transmit preamble */
109  #define PAPAT		0x490   /* Pattern for transmit preamble */
110  #define TXSFD		0x4a0   /* Transmit frame delimiter */
111  #define JAM		0x4b0   /* Jam size */
112  #define TXMAX		0x4c0   /* Transmit max pkt size */
113  #define TXMIN		0x4d0   /* Transmit min pkt size */
114  #define PAREG		0x4e0   /* Count of transmit peak attempts */
115  #define DCNT		0x4f0   /* Transmit defer timer */
116  #define NCCNT		0x500   /* Transmit normal-collision counter */
117  #define NTCNT		0x510   /* Transmit first-collision counter */
118  #define EXCNT		0x520   /* Transmit excess-collision counter */
119  #define LTCNT		0x530   /* Transmit late-collision counter */
120  #define RSEED		0x540   /* Transmit random number seed */
121  #define TXSM		0x550   /* Transmit state machine */
122  
123  /* receive control */
124  #define RXRST		0x620   /* receive reset */
125  #	define	RxResetValue	0x0000
126  #define RXCFG		0x630   /* receive configuration control */
127  #	define	RxMACEnable	0x0001 /* receiver overall enable */
128  #	define	RxCFGReserved	0x0004
129  #	define	RxPadStripEnab	0x0020 /* enable pad byte stripping */
130  #	define	RxPromiscEnable	0x0040 /* turn on promiscuous mode */
131  #	define	RxNoErrCheck	0x0080 /* disable receive error checking */
132  #	define	RxCRCNoStrip	0x0100 /* disable auto-CRC-stripping */
133  #	define	RxRejectOwnPackets 0x0200 /* don't receive our own packets */
134  #	define	RxGrpPromisck	0x0400 /* enable group promiscuous mode */
135  #	define	RxHashFilterEnable 0x0800 /* enable hash filter */
136  #	define	RxAddrFilterEnable 0x1000 /* enable address filter */
137  #define RXMAX		0x640   /* Max receive packet size */
138  #define RXMIN		0x650   /* Min receive packet size */
139  #define MADD2		0x660   /* our enet address, high part */
140  #define MADD1		0x670   /* our enet address, middle part */
141  #define MADD0		0x680   /* our enet address, low part */
142  #define FRCNT		0x690   /* receive frame counter */
143  #define LECNT		0x6a0   /* Receive excess length error counter */
144  #define AECNT		0x6b0   /* Receive misaligned error counter */
145  #define FECNT		0x6c0   /* Receive CRC error counter */
146  #define RXSM		0x6d0   /* Receive state machine */
147  #define RXCV		0x6e0   /* Receive code violation */
148  
149  #define BHASH3		0x700   /* multicast hash register */
150  #define BHASH2		0x710   /* multicast hash register */
151  #define BHASH1		0x720   /* multicast hash register */
152  #define BHASH0		0x730   /* multicast hash register */
153  
154  #define AFR2		0x740   /* address filtering setup? */
155  #define AFR1		0x750   /* address filtering setup? */
156  #define AFR0		0x760   /* address filtering setup? */
157  #define AFCR		0x770   /* address filter compare register? */
158  #	define	EnableAllCompares 0x0fff
159  
160  /* bits in XIFC */
161