1 /* 2 * OpenCores Ethernet MAC 10/100 + subset of 3 * National Semiconductors DP83848C 10/100 PHY 4 * 5 * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf 6 * http://cache.national.com/ds/DP/DP83848C.pdf 7 * 8 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions are met: 13 * * Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * * Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * * Neither the name of the Open Source and Linux Lab nor the 19 * names of its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "qemu/osdep.h" 35 #include "hw/irq.h" 36 #include "hw/net/mii.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/sysbus.h" 39 #include "net/net.h" 40 #include "qemu/module.h" 41 #include "net/eth.h" 42 #include "trace.h" 43 #include "qom/object.h" 44 45 /* RECSMALL is not used because it breaks tap networking in linux: 46 * incoming ARP responses are too short 47 */ 48 #undef USE_RECSMALL 49 50 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN)) 51 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field)) 52 #define GET_REGFIELD(s, reg, field) \ 53 GET_FIELD((s)->regs[reg], reg ## _ ## field) 54 55 #define SET_FIELD(v, field, data) \ 56 ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field)))) 57 #define SET_REGFIELD(s, reg, field, data) \ 58 SET_FIELD((s)->regs[reg], reg ## _ ## field, data) 59 60 /* PHY MII registers */ 61 enum { 62 MII_REG_MAX = 16, 63 }; 64 65 typedef struct Mii { 66 uint16_t regs[MII_REG_MAX]; 67 bool link_ok; 68 } Mii; 69 mii_set_link(Mii * s,bool link_ok)70 static void mii_set_link(Mii *s, bool link_ok) 71 { 72 if (link_ok) { 73 s->regs[MII_BMSR] |= MII_BMSR_LINK_ST; 74 s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX | 75 MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD; 76 } else { 77 s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST; 78 s->regs[MII_ANLPAR] &= 0x01ff; 79 } 80 s->link_ok = link_ok; 81 } 82 mii_reset(Mii * s)83 static void mii_reset(Mii *s) 84 { 85 memset(s->regs, 0, sizeof(s->regs)); 86 s->regs[MII_BMCR] = MII_BMCR_AUTOEN; 87 s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | 88 MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS | 89 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG; 90 s->regs[MII_PHYID1] = 0x2000; 91 s->regs[MII_PHYID2] = 0x5c90; 92 s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX | 93 MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD; 94 mii_set_link(s, s->link_ok); 95 } 96 mii_ro(Mii * s,uint16_t v)97 static void mii_ro(Mii *s, uint16_t v) 98 { 99 } 100 mii_write_bmcr(Mii * s,uint16_t v)101 static void mii_write_bmcr(Mii *s, uint16_t v) 102 { 103 if (v & MII_BMCR_RESET) { 104 mii_reset(s); 105 } else { 106 s->regs[MII_BMCR] = v; 107 } 108 } 109 mii_write_host(Mii * s,unsigned idx,uint16_t v)110 static void mii_write_host(Mii *s, unsigned idx, uint16_t v) 111 { 112 static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { 113 [MII_BMCR] = mii_write_bmcr, 114 [MII_BMSR] = mii_ro, 115 [MII_PHYID1] = mii_ro, 116 [MII_PHYID2] = mii_ro, 117 }; 118 119 if (idx < MII_REG_MAX) { 120 trace_open_eth_mii_write(idx, v); 121 if (reg_write[idx]) { 122 reg_write[idx](s, v); 123 } else { 124 s->regs[idx] = v; 125 } 126 } 127 } 128 mii_read_host(Mii * s,unsigned idx)129 static uint16_t mii_read_host(Mii *s, unsigned idx) 130 { 131 trace_open_eth_mii_read(idx, s->regs[idx]); 132 return s->regs[idx]; 133 } 134 135 /* OpenCores Ethernet registers */ 136 enum { 137 MODER, 138 INT_SOURCE, 139 INT_MASK, 140 IPGT, 141 IPGR1, 142 IPGR2, 143 PACKETLEN, 144 COLLCONF, 145 TX_BD_NUM, 146 CTRLMODER, 147 MIIMODER, 148 MIICOMMAND, 149 MIIADDRESS, 150 MIITX_DATA, 151 MIIRX_DATA, 152 MIISTATUS, 153 MAC_ADDR0, 154 MAC_ADDR1, 155 HASH0, 156 HASH1, 157 TXCTRL, 158 REG_MAX, 159 }; 160 161 enum { 162 MODER_RECSMALL = 0x10000, 163 MODER_PAD = 0x8000, 164 MODER_HUGEN = 0x4000, 165 MODER_RST = 0x800, 166 MODER_LOOPBCK = 0x80, 167 MODER_PRO = 0x20, 168 MODER_IAM = 0x10, 169 MODER_BRO = 0x8, 170 MODER_TXEN = 0x2, 171 MODER_RXEN = 0x1, 172 }; 173 174 enum { 175 INT_SOURCE_BUSY = 0x10, 176 INT_SOURCE_RXB = 0x4, 177 INT_SOURCE_TXB = 0x1, 178 }; 179 180 enum { 181 PACKETLEN_MINFL = 0xffff0000, 182 PACKETLEN_MINFL_LBN = 16, 183 PACKETLEN_MAXFL = 0xffff, 184 PACKETLEN_MAXFL_LBN = 0, 185 }; 186 187 enum { 188 MIICOMMAND_WCTRLDATA = 0x4, 189 MIICOMMAND_RSTAT = 0x2, 190 MIICOMMAND_SCANSTAT = 0x1, 191 }; 192 193 enum { 194 MIIADDRESS_RGAD = 0x1f00, 195 MIIADDRESS_RGAD_LBN = 8, 196 MIIADDRESS_FIAD = 0x1f, 197 MIIADDRESS_FIAD_LBN = 0, 198 }; 199 200 enum { 201 MIITX_DATA_CTRLDATA = 0xffff, 202 MIITX_DATA_CTRLDATA_LBN = 0, 203 }; 204 205 enum { 206 MIIRX_DATA_PRSD = 0xffff, 207 MIIRX_DATA_PRSD_LBN = 0, 208 }; 209 210 enum { 211 MIISTATUS_LINKFAIL = 0x1, 212 MIISTATUS_LINKFAIL_LBN = 0, 213 }; 214 215 enum { 216 MAC_ADDR0_BYTE2 = 0xff000000, 217 MAC_ADDR0_BYTE2_LBN = 24, 218 MAC_ADDR0_BYTE3 = 0xff0000, 219 MAC_ADDR0_BYTE3_LBN = 16, 220 MAC_ADDR0_BYTE4 = 0xff00, 221 MAC_ADDR0_BYTE4_LBN = 8, 222 MAC_ADDR0_BYTE5 = 0xff, 223 MAC_ADDR0_BYTE5_LBN = 0, 224 }; 225 226 enum { 227 MAC_ADDR1_BYTE0 = 0xff00, 228 MAC_ADDR1_BYTE0_LBN = 8, 229 MAC_ADDR1_BYTE1 = 0xff, 230 MAC_ADDR1_BYTE1_LBN = 0, 231 }; 232 233 enum { 234 TXD_LEN = 0xffff0000, 235 TXD_LEN_LBN = 16, 236 TXD_RD = 0x8000, 237 TXD_IRQ = 0x4000, 238 TXD_WR = 0x2000, 239 TXD_PAD = 0x1000, 240 TXD_CRC = 0x800, 241 TXD_UR = 0x100, 242 TXD_RTRY = 0xf0, 243 TXD_RTRY_LBN = 4, 244 TXD_RL = 0x8, 245 TXD_LC = 0x4, 246 TXD_DF = 0x2, 247 TXD_CS = 0x1, 248 }; 249 250 enum { 251 RXD_LEN = 0xffff0000, 252 RXD_LEN_LBN = 16, 253 RXD_E = 0x8000, 254 RXD_IRQ = 0x4000, 255 RXD_WRAP = 0x2000, 256 RXD_CF = 0x100, 257 RXD_M = 0x80, 258 RXD_OR = 0x40, 259 RXD_IS = 0x20, 260 RXD_DN = 0x10, 261 RXD_TL = 0x8, 262 RXD_SF = 0x4, 263 RXD_CRC = 0x2, 264 RXD_LC = 0x1, 265 }; 266 267 typedef struct desc { 268 uint32_t len_flags; 269 uint32_t buf_ptr; 270 } desc; 271 272 #define DEFAULT_PHY 1 273 274 #define TYPE_OPEN_ETH "open_eth" 275 OBJECT_DECLARE_SIMPLE_TYPE(OpenEthState, OPEN_ETH) 276 277 struct OpenEthState { 278 SysBusDevice parent_obj; 279 280 NICState *nic; 281 NICConf conf; 282 MemoryRegion reg_io; 283 MemoryRegion desc_io; 284 qemu_irq irq; 285 286 Mii mii; 287 uint32_t regs[REG_MAX]; 288 unsigned tx_desc; 289 unsigned rx_desc; 290 desc desc[128]; 291 }; 292 rx_desc(OpenEthState * s)293 static desc *rx_desc(OpenEthState *s) 294 { 295 return s->desc + s->rx_desc; 296 } 297 tx_desc(OpenEthState * s)298 static desc *tx_desc(OpenEthState *s) 299 { 300 return s->desc + s->tx_desc; 301 } 302 open_eth_update_irq(OpenEthState * s,uint32_t old,uint32_t new)303 static void open_eth_update_irq(OpenEthState *s, 304 uint32_t old, uint32_t new) 305 { 306 if (!old != !new) { 307 trace_open_eth_update_irq(new); 308 qemu_set_irq(s->irq, new); 309 } 310 } 311 open_eth_int_source_write(OpenEthState * s,uint32_t val)312 static void open_eth_int_source_write(OpenEthState *s, 313 uint32_t val) 314 { 315 uint32_t old_val = s->regs[INT_SOURCE]; 316 317 s->regs[INT_SOURCE] = val; 318 open_eth_update_irq(s, old_val & s->regs[INT_MASK], 319 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 320 } 321 open_eth_set_link_status(NetClientState * nc)322 static void open_eth_set_link_status(NetClientState *nc) 323 { 324 OpenEthState *s = qemu_get_nic_opaque(nc); 325 326 if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) { 327 SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down); 328 } 329 mii_set_link(&s->mii, !nc->link_down); 330 } 331 open_eth_reset(void * opaque)332 static void open_eth_reset(void *opaque) 333 { 334 OpenEthState *s = opaque; 335 336 memset(s->regs, 0, sizeof(s->regs)); 337 s->regs[MODER] = 0xa000; 338 s->regs[IPGT] = 0x12; 339 s->regs[IPGR1] = 0xc; 340 s->regs[IPGR2] = 0x12; 341 s->regs[PACKETLEN] = 0x400600; 342 s->regs[COLLCONF] = 0xf003f; 343 s->regs[TX_BD_NUM] = 0x40; 344 s->regs[MIIMODER] = 0x64; 345 346 s->tx_desc = 0; 347 s->rx_desc = 0x40; 348 349 mii_reset(&s->mii); 350 open_eth_set_link_status(qemu_get_queue(s->nic)); 351 } 352 open_eth_can_receive(NetClientState * nc)353 static bool open_eth_can_receive(NetClientState *nc) 354 { 355 OpenEthState *s = qemu_get_nic_opaque(nc); 356 357 return GET_REGBIT(s, MODER, RXEN) && (s->regs[TX_BD_NUM] < 0x80); 358 } 359 open_eth_receive(NetClientState * nc,const uint8_t * buf,size_t size)360 static ssize_t open_eth_receive(NetClientState *nc, 361 const uint8_t *buf, size_t size) 362 { 363 OpenEthState *s = qemu_get_nic_opaque(nc); 364 size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL); 365 size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL); 366 size_t fcsl = 4; 367 bool miss = true; 368 369 trace_open_eth_receive((unsigned)size); 370 371 if (size >= 6) { 372 static const uint8_t bcast_addr[] = { 373 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 374 }; 375 if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) { 376 miss = GET_REGBIT(s, MODER, BRO); 377 } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) { 378 unsigned mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 379 miss = !(s->regs[HASH0 + mcast_idx / 32] & 380 (1 << (mcast_idx % 32))); 381 trace_open_eth_receive_mcast( 382 mcast_idx, s->regs[HASH0], s->regs[HASH1]); 383 } else { 384 miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] || 385 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] || 386 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] || 387 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] || 388 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] || 389 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5]; 390 } 391 } 392 393 if (miss && !GET_REGBIT(s, MODER, PRO)) { 394 trace_open_eth_receive_reject(); 395 return size; 396 } 397 398 #ifdef USE_RECSMALL 399 if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) { 400 #else 401 { 402 #endif 403 static const uint8_t zero[64] = {0}; 404 desc *desc = rx_desc(s); 405 size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl; 406 407 if (!(desc->len_flags & RXD_E)) { 408 open_eth_int_source_write(s, 409 s->regs[INT_SOURCE] | INT_SOURCE_BUSY); 410 return size; 411 } 412 413 desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR | 414 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC); 415 416 if (copy_size > size) { 417 copy_size = size; 418 } else { 419 fcsl = 0; 420 } 421 if (miss) { 422 desc->len_flags |= RXD_M; 423 } 424 if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) { 425 desc->len_flags |= RXD_TL; 426 } 427 #ifdef USE_RECSMALL 428 if (size < minfl) { 429 desc->len_flags |= RXD_SF; 430 } 431 #endif 432 433 cpu_physical_memory_write(desc->buf_ptr, buf, copy_size); 434 435 if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) { 436 if (minfl - copy_size > fcsl) { 437 fcsl = 0; 438 } else { 439 fcsl -= minfl - copy_size; 440 } 441 while (copy_size < minfl) { 442 size_t zero_sz = minfl - copy_size < sizeof(zero) ? 443 minfl - copy_size : sizeof(zero); 444 445 cpu_physical_memory_write(desc->buf_ptr + copy_size, 446 zero, zero_sz); 447 copy_size += zero_sz; 448 } 449 } 450 451 /* There's no FCS in the frames handed to us by the QEMU, zero fill it. 452 * Don't do it if the frame is cut at the MAXFL or padded with 4 or 453 * more bytes to the MINFL. 454 */ 455 cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl); 456 copy_size += fcsl; 457 458 SET_FIELD(desc->len_flags, RXD_LEN, copy_size); 459 460 if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) { 461 s->rx_desc = s->regs[TX_BD_NUM]; 462 } else { 463 ++s->rx_desc; 464 } 465 desc->len_flags &= ~RXD_E; 466 467 trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags); 468 469 if (desc->len_flags & RXD_IRQ) { 470 open_eth_int_source_write(s, 471 s->regs[INT_SOURCE] | INT_SOURCE_RXB); 472 } 473 } 474 return size; 475 } 476 477 static NetClientInfo net_open_eth_info = { 478 .type = NET_CLIENT_DRIVER_NIC, 479 .size = sizeof(NICState), 480 .can_receive = open_eth_can_receive, 481 .receive = open_eth_receive, 482 .link_status_changed = open_eth_set_link_status, 483 }; 484 485 static void open_eth_start_xmit(OpenEthState *s, desc *tx) 486 { 487 uint8_t *buf = NULL; 488 uint8_t buffer[0x600]; 489 unsigned len = GET_FIELD(tx->len_flags, TXD_LEN); 490 unsigned tx_len = len; 491 492 if ((tx->len_flags & TXD_PAD) && 493 tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) { 494 tx_len = GET_REGFIELD(s, PACKETLEN, MINFL); 495 } 496 if (!GET_REGBIT(s, MODER, HUGEN) && 497 tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) { 498 tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL); 499 } 500 501 trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len); 502 503 if (tx_len > sizeof(buffer)) { 504 buf = g_new(uint8_t, tx_len); 505 } else { 506 buf = buffer; 507 } 508 if (len > tx_len) { 509 len = tx_len; 510 } 511 cpu_physical_memory_read(tx->buf_ptr, buf, len); 512 if (tx_len > len) { 513 memset(buf + len, 0, tx_len - len); 514 } 515 qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len); 516 if (tx_len > sizeof(buffer)) { 517 g_free(buf); 518 } 519 520 if (tx->len_flags & TXD_WR) { 521 s->tx_desc = 0; 522 } else { 523 ++s->tx_desc; 524 if (s->tx_desc >= s->regs[TX_BD_NUM]) { 525 s->tx_desc = 0; 526 } 527 } 528 tx->len_flags &= ~(TXD_RD | TXD_UR | 529 TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS); 530 if (tx->len_flags & TXD_IRQ) { 531 open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB); 532 } 533 534 } 535 536 static void open_eth_check_start_xmit(OpenEthState *s) 537 { 538 desc *tx = tx_desc(s); 539 if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 && 540 (tx->len_flags & TXD_RD) && 541 GET_FIELD(tx->len_flags, TXD_LEN) > 4) { 542 open_eth_start_xmit(s, tx); 543 } 544 } 545 546 static uint64_t open_eth_reg_read(void *opaque, 547 hwaddr addr, unsigned int size) 548 { 549 static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = { 550 }; 551 OpenEthState *s = opaque; 552 unsigned idx = addr / 4; 553 uint64_t v = 0; 554 555 if (idx < REG_MAX) { 556 if (reg_read[idx]) { 557 v = reg_read[idx](s); 558 } else { 559 v = s->regs[idx]; 560 } 561 } 562 trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v); 563 return v; 564 } 565 566 static void open_eth_notify_can_receive(OpenEthState *s) 567 { 568 NetClientState *nc = qemu_get_queue(s->nic); 569 570 if (open_eth_can_receive(nc)) { 571 qemu_flush_queued_packets(nc); 572 } 573 } 574 575 static void open_eth_ro(OpenEthState *s, uint32_t val) 576 { 577 } 578 579 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val) 580 { 581 uint32_t set = val & ~s->regs[MODER]; 582 583 if (set & MODER_RST) { 584 open_eth_reset(s); 585 } 586 587 s->regs[MODER] = val; 588 589 if (set & MODER_RXEN) { 590 s->rx_desc = s->regs[TX_BD_NUM]; 591 open_eth_notify_can_receive(s); 592 } 593 if (set & MODER_TXEN) { 594 s->tx_desc = 0; 595 open_eth_check_start_xmit(s); 596 } 597 } 598 599 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val) 600 { 601 uint32_t old = s->regs[INT_SOURCE]; 602 603 s->regs[INT_SOURCE] &= ~val; 604 open_eth_update_irq(s, old & s->regs[INT_MASK], 605 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 606 } 607 608 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val) 609 { 610 uint32_t old = s->regs[INT_MASK]; 611 612 s->regs[INT_MASK] = val; 613 open_eth_update_irq(s, s->regs[INT_SOURCE] & old, 614 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 615 } 616 617 static void open_eth_tx_bd_num_host_write(OpenEthState *s, uint32_t val) 618 { 619 if (val < 0x80) { 620 bool enable = s->regs[TX_BD_NUM] == 0x80; 621 622 s->regs[TX_BD_NUM] = val; 623 if (enable) { 624 open_eth_notify_can_receive(s); 625 } 626 } 627 } 628 629 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val) 630 { 631 unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD); 632 unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD); 633 634 if (val & MIICOMMAND_WCTRLDATA) { 635 if (fiad == DEFAULT_PHY) { 636 mii_write_host(&s->mii, rgad, 637 GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); 638 } 639 } 640 if (val & MIICOMMAND_RSTAT) { 641 if (fiad == DEFAULT_PHY) { 642 SET_REGFIELD(s, MIIRX_DATA, PRSD, 643 mii_read_host(&s->mii, rgad)); 644 } else { 645 s->regs[MIIRX_DATA] = 0xffff; 646 } 647 SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down); 648 } 649 } 650 651 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val) 652 { 653 SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val); 654 if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) { 655 mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD), 656 GET_REGFIELD(s, MIITX_DATA, CTRLDATA)); 657 } 658 } 659 660 static void open_eth_reg_write(void *opaque, 661 hwaddr addr, uint64_t val, unsigned int size) 662 { 663 static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = { 664 [MODER] = open_eth_moder_host_write, 665 [INT_SOURCE] = open_eth_int_source_host_write, 666 [INT_MASK] = open_eth_int_mask_host_write, 667 [TX_BD_NUM] = open_eth_tx_bd_num_host_write, 668 [MIICOMMAND] = open_eth_mii_command_host_write, 669 [MIITX_DATA] = open_eth_mii_tx_host_write, 670 [MIISTATUS] = open_eth_ro, 671 }; 672 OpenEthState *s = opaque; 673 unsigned idx = addr / 4; 674 675 if (idx < REG_MAX) { 676 trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val); 677 if (reg_write[idx]) { 678 reg_write[idx](s, val); 679 } else { 680 s->regs[idx] = val; 681 } 682 } 683 } 684 685 static uint64_t open_eth_desc_read(void *opaque, 686 hwaddr addr, unsigned int size) 687 { 688 OpenEthState *s = opaque; 689 uint64_t v = 0; 690 691 addr &= 0x3ff; 692 memcpy(&v, (uint8_t *)s->desc + addr, size); 693 trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v); 694 return v; 695 } 696 697 static void open_eth_desc_write(void *opaque, 698 hwaddr addr, uint64_t val, unsigned int size) 699 { 700 OpenEthState *s = opaque; 701 702 addr &= 0x3ff; 703 trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val); 704 memcpy((uint8_t *)s->desc + addr, &val, size); 705 open_eth_check_start_xmit(s); 706 } 707 708 709 static const MemoryRegionOps open_eth_reg_ops = { 710 .read = open_eth_reg_read, 711 .write = open_eth_reg_write, 712 }; 713 714 static const MemoryRegionOps open_eth_desc_ops = { 715 .read = open_eth_desc_read, 716 .write = open_eth_desc_write, 717 }; 718 719 static void sysbus_open_eth_realize(DeviceState *dev, Error **errp) 720 { 721 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 722 OpenEthState *s = OPEN_ETH(dev); 723 724 memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s, 725 "open_eth.regs", 0x54); 726 sysbus_init_mmio(sbd, &s->reg_io); 727 728 memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s, 729 "open_eth.desc", 0x400); 730 sysbus_init_mmio(sbd, &s->desc_io); 731 732 sysbus_init_irq(sbd, &s->irq); 733 734 s->nic = qemu_new_nic(&net_open_eth_info, &s->conf, 735 object_get_typename(OBJECT(s)), dev->id, 736 &dev->mem_reentrancy_guard, s); 737 } 738 739 static void qdev_open_eth_reset(DeviceState *dev) 740 { 741 OpenEthState *d = OPEN_ETH(dev); 742 743 open_eth_reset(d); 744 } 745 746 static Property open_eth_properties[] = { 747 DEFINE_NIC_PROPERTIES(OpenEthState, conf), 748 DEFINE_PROP_END_OF_LIST(), 749 }; 750 751 static void open_eth_class_init(ObjectClass *klass, void *data) 752 { 753 DeviceClass *dc = DEVICE_CLASS(klass); 754 755 dc->realize = sysbus_open_eth_realize; 756 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 757 dc->desc = "Opencores 10/100 Mbit Ethernet"; 758 device_class_set_legacy_reset(dc, qdev_open_eth_reset); 759 device_class_set_props(dc, open_eth_properties); 760 } 761 762 static const TypeInfo open_eth_info = { 763 .name = TYPE_OPEN_ETH, 764 .parent = TYPE_SYS_BUS_DEVICE, 765 .instance_size = sizeof(OpenEthState), 766 .class_init = open_eth_class_init, 767 }; 768 769 static void open_eth_register_types(void) 770 { 771 type_register_static(&open_eth_info); 772 } 773 774 type_init(open_eth_register_types) 775