1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Libata based driver for Apple "macio" family of PATA controllers
4 *
5 * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
6 * <benh@kernel.crashing.org>
7 *
8 * Some bits and pieces from drivers/ide/ppc/pmac.c
9 *
10 */
11
12 #undef DEBUG
13 #undef DEBUG_DMA
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/blkdev.h>
19 #include <linux/ata.h>
20 #include <linux/libata.h>
21 #include <linux/adb.h>
22 #include <linux/pmu.h>
23 #include <linux/scatterlist.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of.h>
26 #include <linux/gfp.h>
27 #include <linux/pci.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32
33 #include <asm/macio.h>
34 #include <asm/io.h>
35 #include <asm/dbdma.h>
36 #include <asm/machdep.h>
37 #include <asm/pmac_feature.h>
38 #include <asm/mediabay.h>
39
40 #ifdef DEBUG_DMA
41 #define dev_dbgdma(dev, format, arg...) \
42 dev_printk(KERN_DEBUG , dev , format , ## arg)
43 #else
44 #define dev_dbgdma(dev, format, arg...) \
45 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
46 #endif
47
48 #define DRV_NAME "pata_macio"
49 #define DRV_VERSION "0.9"
50
51 /* Models of macio ATA controller */
52 enum {
53 controller_ohare, /* OHare based */
54 controller_heathrow, /* Heathrow/Paddington */
55 controller_kl_ata3, /* KeyLargo ATA-3 */
56 controller_kl_ata4, /* KeyLargo ATA-4 */
57 controller_un_ata6, /* UniNorth2 ATA-6 */
58 controller_k2_ata6, /* K2 ATA-6 */
59 controller_sh_ata6, /* Shasta ATA-6 */
60 };
61
62 static const char* macio_ata_names[] = {
63 "OHare ATA", /* OHare based */
64 "Heathrow ATA", /* Heathrow/Paddington */
65 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
66 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
67 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
68 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
69 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
70 };
71
72 /*
73 * Extra registers, both 32-bit little-endian
74 */
75 #define IDE_TIMING_CONFIG 0x200
76 #define IDE_INTERRUPT 0x300
77
78 /* Kauai (U2) ATA has different register setup */
79 #define IDE_KAUAI_PIO_CONFIG 0x200
80 #define IDE_KAUAI_ULTRA_CONFIG 0x210
81 #define IDE_KAUAI_POLL_CONFIG 0x220
82
83 /*
84 * Timing configuration register definitions
85 */
86
87 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
88 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
89 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
90 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
91 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
92
93 /* 133Mhz cell, found in shasta.
94 * See comments about 100 Mhz Uninorth 2...
95 * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
96 * weird and I don't now why .. at this stage
97 */
98 #define TR_133_PIOREG_PIO_MASK 0xff000fff
99 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
100 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
101 #define TR_133_UDMAREG_UDMA_EN 0x00000001
102
103 /* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
104 * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
105 * controlled like gem or fw. It appears to be an evolution of keylargo
106 * ATA4 with a timing register extended to 2x32bits registers (one
107 * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
108 * It has it's own local feature control register as well.
109 *
110 * After scratching my mind over the timing values, at least for PIO
111 * and MDMA, I think I've figured the format of the timing register,
112 * though I use pre-calculated tables for UDMA as usual...
113 */
114 #define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
115 #define TR_100_PIO_ADDRSETUP_SHIFT 24
116 #define TR_100_MDMA_MASK 0x00fff000
117 #define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
118 #define TR_100_MDMA_RECOVERY_SHIFT 18
119 #define TR_100_MDMA_ACCESS_MASK 0x0003f000
120 #define TR_100_MDMA_ACCESS_SHIFT 12
121 #define TR_100_PIO_MASK 0xff000fff
122 #define TR_100_PIO_RECOVERY_MASK 0x00000fc0
123 #define TR_100_PIO_RECOVERY_SHIFT 6
124 #define TR_100_PIO_ACCESS_MASK 0x0000003f
125 #define TR_100_PIO_ACCESS_SHIFT 0
126
127 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
128 #define TR_100_UDMAREG_UDMA_EN 0x00000001
129
130
131 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
132 * 40 connector cable and to 4 on 80 connector one.
133 * Clock unit is 15ns (66Mhz)
134 *
135 * 3 Values can be programmed:
136 * - Write data setup, which appears to match the cycle time. They
137 * also call it DIOW setup.
138 * - Ready to pause time (from spec)
139 * - Address setup. That one is weird. I don't see where exactly
140 * it fits in UDMA cycles, I got it's name from an obscure piece
141 * of commented out code in Darwin. They leave it to 0, we do as
142 * well, despite a comment that would lead to think it has a
143 * min value of 45ns.
144 * Apple also add 60ns to the write data setup (or cycle time ?) on
145 * reads.
146 */
147 #define TR_66_UDMA_MASK 0xfff00000
148 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
149 #define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
150 #define TR_66_PIO_ADDRSETUP_SHIFT 29
151 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
152 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
153 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
154 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
155 #define TR_66_MDMA_MASK 0x000ffc00
156 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
157 #define TR_66_MDMA_RECOVERY_SHIFT 15
158 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
159 #define TR_66_MDMA_ACCESS_SHIFT 10
160 #define TR_66_PIO_MASK 0xe00003ff
161 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
162 #define TR_66_PIO_RECOVERY_SHIFT 5
163 #define TR_66_PIO_ACCESS_MASK 0x0000001f
164 #define TR_66_PIO_ACCESS_SHIFT 0
165
166 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
167 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
168 *
169 * The access time and recovery time can be programmed. Some older
170 * Darwin code base limit OHare to 150ns cycle time. I decided to do
171 * the same here fore safety against broken old hardware ;)
172 * The HalfTick bit, when set, adds half a clock (15ns) to the access
173 * time and removes one from recovery. It's not supported on KeyLargo
174 * implementation afaik. The E bit appears to be set for PIO mode 0 and
175 * is used to reach long timings used in this mode.
176 */
177 #define TR_33_MDMA_MASK 0x003ff800
178 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
179 #define TR_33_MDMA_RECOVERY_SHIFT 16
180 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
181 #define TR_33_MDMA_ACCESS_SHIFT 11
182 #define TR_33_MDMA_HALFTICK 0x00200000
183 #define TR_33_PIO_MASK 0x000007ff
184 #define TR_33_PIO_E 0x00000400
185 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
186 #define TR_33_PIO_RECOVERY_SHIFT 5
187 #define TR_33_PIO_ACCESS_MASK 0x0000001f
188 #define TR_33_PIO_ACCESS_SHIFT 0
189
190 /*
191 * Interrupt register definitions. Only present on newer cells
192 * (Keylargo and later afaik) so we don't use it.
193 */
194 #define IDE_INTR_DMA 0x80000000
195 #define IDE_INTR_DEVICE 0x40000000
196
197 /*
198 * FCR Register on Kauai. Not sure what bit 0x4 is ...
199 */
200 #define KAUAI_FCR_UATA_MAGIC 0x00000004
201 #define KAUAI_FCR_UATA_RESET_N 0x00000002
202 #define KAUAI_FCR_UATA_ENABLE 0x00000001
203
204
205 /* Allow up to 256 DBDMA commands per xfer */
206 #define MAX_DCMDS 256
207
208 /* Don't let a DMA segment go all the way to 64K */
209 #define MAX_DBDMA_SEG 0xff00
210
211
212 /*
213 * Wait 1s for disk to answer on IDE bus after a hard reset
214 * of the device (via GPIO/FCR).
215 *
216 * Some devices seem to "pollute" the bus even after dropping
217 * the BSY bit (typically some combo drives slave on the UDMA
218 * bus) after a hard reset. Since we hard reset all drives on
219 * KeyLargo ATA66, we have to keep that delay around. I may end
220 * up not hard resetting anymore on these and keep the delay only
221 * for older interfaces instead (we have to reset when coming
222 * from MacOS...) --BenH.
223 */
224 #define IDE_WAKEUP_DELAY_MS 1000
225
226 struct pata_macio_timing;
227
228 struct pata_macio_priv {
229 int kind;
230 int aapl_bus_id;
231 int mediabay : 1;
232 struct device_node *node;
233 struct macio_dev *mdev;
234 struct pci_dev *pdev;
235 struct device *dev;
236 int irq;
237 u32 treg[2][2];
238 void __iomem *tfregs;
239 void __iomem *kauai_fcr;
240 struct dbdma_cmd * dma_table_cpu;
241 dma_addr_t dma_table_dma;
242 struct ata_host *host;
243 const struct pata_macio_timing *timings;
244 };
245
246 /* Previous variants of this driver used to calculate timings
247 * for various variants of the chip and use tables for others.
248 *
249 * Not only was this confusing, but in addition, it isn't clear
250 * whether our calculation code was correct. It didn't entirely
251 * match the darwin code and whatever documentation I could find
252 * on these cells
253 *
254 * I decided to entirely rely on a table instead for this version
255 * of the driver. Also, because I don't really care about derated
256 * modes and really old HW other than making it work, I'm not going
257 * to calculate / snoop timing values for something else than the
258 * standard modes.
259 */
260 struct pata_macio_timing {
261 int mode;
262 u32 reg1; /* Bits to set in first timing reg */
263 u32 reg2; /* Bits to set in second timing reg */
264 };
265
266 static const struct pata_macio_timing pata_macio_ohare_timings[] = {
267 { XFER_PIO_0, 0x00000526, 0, },
268 { XFER_PIO_1, 0x00000085, 0, },
269 { XFER_PIO_2, 0x00000025, 0, },
270 { XFER_PIO_3, 0x00000025, 0, },
271 { XFER_PIO_4, 0x00000025, 0, },
272 { XFER_MW_DMA_0, 0x00074000, 0, },
273 { XFER_MW_DMA_1, 0x00221000, 0, },
274 { XFER_MW_DMA_2, 0x00211000, 0, },
275 { -1, 0, 0 }
276 };
277
278 static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
279 { XFER_PIO_0, 0x00000526, 0, },
280 { XFER_PIO_1, 0x00000085, 0, },
281 { XFER_PIO_2, 0x00000025, 0, },
282 { XFER_PIO_3, 0x00000025, 0, },
283 { XFER_PIO_4, 0x00000025, 0, },
284 { XFER_MW_DMA_0, 0x00074000, 0, },
285 { XFER_MW_DMA_1, 0x00221000, 0, },
286 { XFER_MW_DMA_2, 0x00211000, 0, },
287 { -1, 0, 0 }
288 };
289
290 static const struct pata_macio_timing pata_macio_kl33_timings[] = {
291 { XFER_PIO_0, 0x00000526, 0, },
292 { XFER_PIO_1, 0x00000085, 0, },
293 { XFER_PIO_2, 0x00000025, 0, },
294 { XFER_PIO_3, 0x00000025, 0, },
295 { XFER_PIO_4, 0x00000025, 0, },
296 { XFER_MW_DMA_0, 0x00084000, 0, },
297 { XFER_MW_DMA_1, 0x00021800, 0, },
298 { XFER_MW_DMA_2, 0x00011800, 0, },
299 { -1, 0, 0 }
300 };
301
302 static const struct pata_macio_timing pata_macio_kl66_timings[] = {
303 { XFER_PIO_0, 0x0000038c, 0, },
304 { XFER_PIO_1, 0x0000020a, 0, },
305 { XFER_PIO_2, 0x00000127, 0, },
306 { XFER_PIO_3, 0x000000c6, 0, },
307 { XFER_PIO_4, 0x00000065, 0, },
308 { XFER_MW_DMA_0, 0x00084000, 0, },
309 { XFER_MW_DMA_1, 0x00029800, 0, },
310 { XFER_MW_DMA_2, 0x00019400, 0, },
311 { XFER_UDMA_0, 0x19100000, 0, },
312 { XFER_UDMA_1, 0x14d00000, 0, },
313 { XFER_UDMA_2, 0x10900000, 0, },
314 { XFER_UDMA_3, 0x0c700000, 0, },
315 { XFER_UDMA_4, 0x0c500000, 0, },
316 { -1, 0, 0 }
317 };
318
319 static const struct pata_macio_timing pata_macio_kauai_timings[] = {
320 { XFER_PIO_0, 0x08000a92, 0, },
321 { XFER_PIO_1, 0x0800060f, 0, },
322 { XFER_PIO_2, 0x0800038b, 0, },
323 { XFER_PIO_3, 0x05000249, 0, },
324 { XFER_PIO_4, 0x04000148, 0, },
325 { XFER_MW_DMA_0, 0x00618000, 0, },
326 { XFER_MW_DMA_1, 0x00209000, 0, },
327 { XFER_MW_DMA_2, 0x00148000, 0, },
328 { XFER_UDMA_0, 0, 0x000070c1, },
329 { XFER_UDMA_1, 0, 0x00005d81, },
330 { XFER_UDMA_2, 0, 0x00004a61, },
331 { XFER_UDMA_3, 0, 0x00003a51, },
332 { XFER_UDMA_4, 0, 0x00002a31, },
333 { XFER_UDMA_5, 0, 0x00002921, },
334 { -1, 0, 0 }
335 };
336
337 static const struct pata_macio_timing pata_macio_shasta_timings[] = {
338 { XFER_PIO_0, 0x0a000c97, 0, },
339 { XFER_PIO_1, 0x07000712, 0, },
340 { XFER_PIO_2, 0x040003cd, 0, },
341 { XFER_PIO_3, 0x0500028b, 0, },
342 { XFER_PIO_4, 0x0400010a, 0, },
343 { XFER_MW_DMA_0, 0x00820800, 0, },
344 { XFER_MW_DMA_1, 0x0028b000, 0, },
345 { XFER_MW_DMA_2, 0x001ca000, 0, },
346 { XFER_UDMA_0, 0, 0x00035901, },
347 { XFER_UDMA_1, 0, 0x000348b1, },
348 { XFER_UDMA_2, 0, 0x00033881, },
349 { XFER_UDMA_3, 0, 0x00033861, },
350 { XFER_UDMA_4, 0, 0x00033841, },
351 { XFER_UDMA_5, 0, 0x00033031, },
352 { XFER_UDMA_6, 0, 0x00033021, },
353 { -1, 0, 0 }
354 };
355
pata_macio_find_timing(struct pata_macio_priv * priv,int mode)356 static const struct pata_macio_timing *pata_macio_find_timing(
357 struct pata_macio_priv *priv,
358 int mode)
359 {
360 int i;
361
362 for (i = 0; priv->timings[i].mode > 0; i++) {
363 if (priv->timings[i].mode == mode)
364 return &priv->timings[i];
365 }
366 return NULL;
367 }
368
369
pata_macio_apply_timings(struct ata_port * ap,unsigned int device)370 static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
371 {
372 struct pata_macio_priv *priv = ap->private_data;
373 void __iomem *rbase = ap->ioaddr.cmd_addr;
374
375 if (priv->kind == controller_sh_ata6 ||
376 priv->kind == controller_un_ata6 ||
377 priv->kind == controller_k2_ata6) {
378 writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
379 writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
380 } else
381 writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
382 }
383
pata_macio_dev_select(struct ata_port * ap,unsigned int device)384 static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
385 {
386 ata_sff_dev_select(ap, device);
387
388 /* Apply timings */
389 pata_macio_apply_timings(ap, device);
390 }
391
pata_macio_set_timings(struct ata_port * ap,struct ata_device * adev)392 static void pata_macio_set_timings(struct ata_port *ap,
393 struct ata_device *adev)
394 {
395 struct pata_macio_priv *priv = ap->private_data;
396 const struct pata_macio_timing *t;
397
398 dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
399 adev->devno,
400 adev->pio_mode,
401 ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
402 adev->dma_mode,
403 ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
404
405 /* First clear timings */
406 priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
407
408 /* Now get the PIO timings */
409 t = pata_macio_find_timing(priv, adev->pio_mode);
410 if (t == NULL) {
411 dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
412 adev->pio_mode);
413 t = pata_macio_find_timing(priv, XFER_PIO_0);
414 }
415 BUG_ON(t == NULL);
416
417 /* PIO timings only ever use the first treg */
418 priv->treg[adev->devno][0] |= t->reg1;
419
420 /* Now get DMA timings */
421 t = pata_macio_find_timing(priv, adev->dma_mode);
422 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
423 dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
424 t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
425 }
426 BUG_ON(t == NULL);
427
428 /* DMA timings can use both tregs */
429 priv->treg[adev->devno][0] |= t->reg1;
430 priv->treg[adev->devno][1] |= t->reg2;
431
432 dev_dbg(priv->dev, " -> %08x %08x\n",
433 priv->treg[adev->devno][0],
434 priv->treg[adev->devno][1]);
435
436 /* Apply to hardware */
437 pata_macio_apply_timings(ap, adev->devno);
438 }
439
440 /*
441 * Blast some well known "safe" values to the timing registers at init or
442 * wakeup from sleep time, before we do real calculation
443 */
pata_macio_default_timings(struct pata_macio_priv * priv)444 static void pata_macio_default_timings(struct pata_macio_priv *priv)
445 {
446 unsigned int value, value2 = 0;
447
448 switch(priv->kind) {
449 case controller_sh_ata6:
450 value = 0x0a820c97;
451 value2 = 0x00033031;
452 break;
453 case controller_un_ata6:
454 case controller_k2_ata6:
455 value = 0x08618a92;
456 value2 = 0x00002921;
457 break;
458 case controller_kl_ata4:
459 value = 0x0008438c;
460 break;
461 case controller_kl_ata3:
462 value = 0x00084526;
463 break;
464 case controller_heathrow:
465 case controller_ohare:
466 default:
467 value = 0x00074526;
468 break;
469 }
470 priv->treg[0][0] = priv->treg[1][0] = value;
471 priv->treg[0][1] = priv->treg[1][1] = value2;
472 }
473
pata_macio_cable_detect(struct ata_port * ap)474 static int pata_macio_cable_detect(struct ata_port *ap)
475 {
476 struct pata_macio_priv *priv = ap->private_data;
477
478 /* Get cable type from device-tree */
479 if (priv->kind == controller_kl_ata4 ||
480 priv->kind == controller_un_ata6 ||
481 priv->kind == controller_k2_ata6 ||
482 priv->kind == controller_sh_ata6) {
483 const char* cable = of_get_property(priv->node, "cable-type",
484 NULL);
485 struct device_node *root = of_find_node_by_path("/");
486 const char *model = of_get_property(root, "model", NULL);
487
488 of_node_put(root);
489
490 if (cable && !strncmp(cable, "80-", 3)) {
491 /* Some drives fail to detect 80c cable in PowerBook
492 * These machine use proprietary short IDE cable
493 * anyway
494 */
495 if (!strncmp(model, "PowerBook", 9))
496 return ATA_CBL_PATA40_SHORT;
497 else
498 return ATA_CBL_PATA80;
499 }
500 }
501
502 /* G5's seem to have incorrect cable type in device-tree.
503 * Let's assume they always have a 80 conductor cable, this seem to
504 * be always the case unless the user mucked around
505 */
506 if (of_device_is_compatible(priv->node, "K2-UATA") ||
507 of_device_is_compatible(priv->node, "shasta-ata"))
508 return ATA_CBL_PATA80;
509
510 /* Anything else is 40 connectors */
511 return ATA_CBL_PATA40;
512 }
513
pata_macio_qc_prep(struct ata_queued_cmd * qc)514 static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)
515 {
516 unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
517 struct ata_port *ap = qc->ap;
518 struct pata_macio_priv *priv = ap->private_data;
519 struct scatterlist *sg;
520 struct dbdma_cmd *table;
521 unsigned int si, pi;
522
523 dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
524 __func__, qc, qc->flags, write, qc->dev->devno);
525
526 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
527 return AC_ERR_OK;
528
529 table = (struct dbdma_cmd *) priv->dma_table_cpu;
530
531 pi = 0;
532 for_each_sg(qc->sg, sg, qc->n_elem, si) {
533 u32 addr, sg_len, len;
534
535 /* determine if physical DMA addr spans 64K boundary.
536 * Note h/w doesn't support 64-bit, so we unconditionally
537 * truncate dma_addr_t to u32.
538 */
539 addr = (u32) sg_dma_address(sg);
540 sg_len = sg_dma_len(sg);
541
542 while (sg_len) {
543 /* table overflow should never happen */
544 if (WARN_ON_ONCE(pi >= MAX_DCMDS))
545 return AC_ERR_SYSTEM;
546
547 len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
548 table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);
549 table->req_count = cpu_to_le16(len);
550 table->phy_addr = cpu_to_le32(addr);
551 table->cmd_dep = 0;
552 table->xfer_status = 0;
553 table->res_count = 0;
554 addr += len;
555 sg_len -= len;
556 ++table;
557 ++pi;
558 }
559 }
560
561 /* Should never happen according to Tejun */
562 if (WARN_ON_ONCE(!pi))
563 return AC_ERR_SYSTEM;
564
565 /* Convert the last command to an input/output */
566 table--;
567 table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST);
568 table++;
569
570 /* Add the stop command to the end of the list */
571 memset(table, 0, sizeof(struct dbdma_cmd));
572 table->command = cpu_to_le16(DBDMA_STOP);
573
574 dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
575
576 return AC_ERR_OK;
577 }
578
579
pata_macio_freeze(struct ata_port * ap)580 static void pata_macio_freeze(struct ata_port *ap)
581 {
582 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
583
584 if (dma_regs) {
585 unsigned int timeout = 1000000;
586
587 /* Make sure DMA controller is stopped */
588 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
589 while (--timeout && (readl(&dma_regs->status) & RUN))
590 udelay(1);
591 }
592
593 ata_sff_freeze(ap);
594 }
595
596
pata_macio_bmdma_setup(struct ata_queued_cmd * qc)597 static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
598 {
599 struct ata_port *ap = qc->ap;
600 struct pata_macio_priv *priv = ap->private_data;
601 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
602 int dev = qc->dev->devno;
603
604 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
605
606 /* Make sure DMA commands updates are visible */
607 writel(priv->dma_table_dma, &dma_regs->cmdptr);
608
609 /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
610 * UDMA reads
611 */
612 if (priv->kind == controller_kl_ata4 &&
613 (priv->treg[dev][0] & TR_66_UDMA_EN)) {
614 void __iomem *rbase = ap->ioaddr.cmd_addr;
615 u32 reg = priv->treg[dev][0];
616
617 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
618 reg += 0x00800000;
619 writel(reg, rbase + IDE_TIMING_CONFIG);
620 }
621
622 /* issue r/w command */
623 ap->ops->sff_exec_command(ap, &qc->tf);
624 }
625
pata_macio_bmdma_start(struct ata_queued_cmd * qc)626 static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
627 {
628 struct ata_port *ap = qc->ap;
629 struct pata_macio_priv *priv = ap->private_data;
630 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
631
632 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
633
634 writel((RUN << 16) | RUN, &dma_regs->control);
635 /* Make sure it gets to the controller right now */
636 (void)readl(&dma_regs->control);
637 }
638
pata_macio_bmdma_stop(struct ata_queued_cmd * qc)639 static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
640 {
641 struct ata_port *ap = qc->ap;
642 struct pata_macio_priv *priv = ap->private_data;
643 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
644 unsigned int timeout = 1000000;
645
646 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
647
648 /* Stop the DMA engine and wait for it to full halt */
649 writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
650 while (--timeout && (readl(&dma_regs->status) & RUN))
651 udelay(1);
652 }
653
pata_macio_bmdma_status(struct ata_port * ap)654 static u8 pata_macio_bmdma_status(struct ata_port *ap)
655 {
656 struct pata_macio_priv *priv = ap->private_data;
657 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
658 u32 dstat, rstat = ATA_DMA_INTR;
659 unsigned long timeout = 0;
660
661 dstat = readl(&dma_regs->status);
662
663 dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
664
665 /* We have two things to deal with here:
666 *
667 * - The dbdma won't stop if the command was started
668 * but completed with an error without transferring all
669 * datas. This happens when bad blocks are met during
670 * a multi-block transfer.
671 *
672 * - The dbdma fifo hasn't yet finished flushing to
673 * system memory when the disk interrupt occurs.
674 */
675
676 /* First check for errors */
677 if ((dstat & (RUN|DEAD)) != RUN)
678 rstat |= ATA_DMA_ERR;
679
680 /* If ACTIVE is cleared, the STOP command has been hit and
681 * the transfer is complete. If not, we have to flush the
682 * channel.
683 */
684 if ((dstat & ACTIVE) == 0)
685 return rstat;
686
687 dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
688
689 /* If dbdma didn't execute the STOP command yet, the
690 * active bit is still set. We consider that we aren't
691 * sharing interrupts (which is hopefully the case with
692 * those controllers) and so we just try to flush the
693 * channel for pending data in the fifo
694 */
695 udelay(1);
696 writel((FLUSH << 16) | FLUSH, &dma_regs->control);
697 for (;;) {
698 udelay(1);
699 dstat = readl(&dma_regs->status);
700 if ((dstat & FLUSH) == 0)
701 break;
702 if (++timeout > 1000) {
703 dev_warn(priv->dev, "timeout flushing DMA\n");
704 rstat |= ATA_DMA_ERR;
705 break;
706 }
707 }
708 return rstat;
709 }
710
711 /* port_start is when we allocate the DMA command list */
pata_macio_port_start(struct ata_port * ap)712 static int pata_macio_port_start(struct ata_port *ap)
713 {
714 struct pata_macio_priv *priv = ap->private_data;
715
716 if (ap->ioaddr.bmdma_addr == NULL)
717 return 0;
718
719 /* Allocate space for the DBDMA commands.
720 *
721 * The +2 is +1 for the stop command and +1 to allow for
722 * aligning the start address to a multiple of 16 bytes.
723 */
724 priv->dma_table_cpu =
725 dmam_alloc_coherent(priv->dev,
726 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
727 &priv->dma_table_dma, GFP_KERNEL);
728 if (priv->dma_table_cpu == NULL) {
729 dev_err(priv->dev, "Unable to allocate DMA command list\n");
730 ap->ioaddr.bmdma_addr = NULL;
731 ap->mwdma_mask = 0;
732 ap->udma_mask = 0;
733 }
734 return 0;
735 }
736
pata_macio_irq_clear(struct ata_port * ap)737 static void pata_macio_irq_clear(struct ata_port *ap)
738 {
739 struct pata_macio_priv *priv = ap->private_data;
740
741 /* Nothing to do here */
742
743 dev_dbgdma(priv->dev, "%s\n", __func__);
744 }
745
pata_macio_reset_hw(struct pata_macio_priv * priv,int resume)746 static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
747 {
748 dev_dbg(priv->dev, "Enabling & resetting... \n");
749
750 if (priv->mediabay)
751 return;
752
753 if (priv->kind == controller_ohare && !resume) {
754 /* The code below is having trouble on some ohare machines
755 * (timing related ?). Until I can put my hand on one of these
756 * units, I keep the old way
757 */
758 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
759 } else {
760 int rc;
761
762 /* Reset and enable controller */
763 rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
764 priv->node, priv->aapl_bus_id, 1);
765 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
766 priv->node, priv->aapl_bus_id, 1);
767 msleep(10);
768 /* Only bother waiting if there's a reset control */
769 if (rc == 0) {
770 ppc_md.feature_call(PMAC_FTR_IDE_RESET,
771 priv->node, priv->aapl_bus_id, 0);
772 msleep(IDE_WAKEUP_DELAY_MS);
773 }
774 }
775
776 /* If resuming a PCI device, restore the config space here */
777 if (priv->pdev && resume) {
778 int rc;
779
780 pci_restore_state(priv->pdev);
781 rc = pcim_enable_device(priv->pdev);
782 if (rc)
783 dev_err(&priv->pdev->dev,
784 "Failed to enable device after resume (%d)\n",
785 rc);
786 else
787 pci_set_master(priv->pdev);
788 }
789
790 /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
791 * seem necessary and speeds up the boot process
792 */
793 if (priv->kauai_fcr)
794 writel(KAUAI_FCR_UATA_MAGIC |
795 KAUAI_FCR_UATA_RESET_N |
796 KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
797 }
798
799 /* Hook the standard slave config to fixup some HW related alignment
800 * restrictions
801 */
pata_macio_slave_config(struct scsi_device * sdev)802 static int pata_macio_slave_config(struct scsi_device *sdev)
803 {
804 struct ata_port *ap = ata_shost_to_port(sdev->host);
805 struct pata_macio_priv *priv = ap->private_data;
806 struct ata_device *dev;
807 u16 cmd;
808 int rc;
809
810 /* First call original */
811 rc = ata_scsi_slave_config(sdev);
812 if (rc)
813 return rc;
814
815 /* This is lifted from sata_nv */
816 dev = &ap->link.device[sdev->id];
817
818 /* OHare has issues with non cache aligned DMA on some chipsets */
819 if (priv->kind == controller_ohare) {
820 blk_queue_update_dma_alignment(sdev->request_queue, 31);
821 blk_queue_update_dma_pad(sdev->request_queue, 31);
822
823 /* Tell the world about it */
824 ata_dev_info(dev, "OHare alignment limits applied\n");
825 return 0;
826 }
827
828 /* We only have issues with ATAPI */
829 if (dev->class != ATA_DEV_ATAPI)
830 return 0;
831
832 /* Shasta and K2 seem to have "issues" with reads ... */
833 if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
834 /* Allright these are bad, apply restrictions */
835 blk_queue_update_dma_alignment(sdev->request_queue, 15);
836 blk_queue_update_dma_pad(sdev->request_queue, 15);
837
838 /* We enable MWI and hack cache line size directly here, this
839 * is specific to this chipset and not normal values, we happen
840 * to somewhat know what we are doing here (which is basically
841 * to do the same Apple does and pray they did not get it wrong :-)
842 */
843 BUG_ON(!priv->pdev);
844 pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
845 pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
846 pci_write_config_word(priv->pdev, PCI_COMMAND,
847 cmd | PCI_COMMAND_INVALIDATE);
848
849 /* Tell the world about it */
850 ata_dev_info(dev, "K2/Shasta alignment limits applied\n");
851 }
852
853 return 0;
854 }
855
856 #ifdef CONFIG_PM_SLEEP
pata_macio_do_suspend(struct pata_macio_priv * priv,pm_message_t mesg)857 static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
858 {
859 /* First, core libata suspend to do most of the work */
860 ata_host_suspend(priv->host, mesg);
861
862 /* Restore to default timings */
863 pata_macio_default_timings(priv);
864
865 /* Mask interrupt. Not strictly necessary but old driver did
866 * it and I'd rather not change that here */
867 disable_irq(priv->irq);
868
869 /* The media bay will handle itself just fine */
870 if (priv->mediabay)
871 return 0;
872
873 /* Kauai has bus control FCRs directly here */
874 if (priv->kauai_fcr) {
875 u32 fcr = readl(priv->kauai_fcr);
876 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
877 writel(fcr, priv->kauai_fcr);
878 }
879
880 /* For PCI, save state and disable DMA. No need to call
881 * pci_set_power_state(), the HW doesn't do D states that
882 * way, the platform code will take care of suspending the
883 * ASIC properly
884 */
885 if (priv->pdev) {
886 pci_save_state(priv->pdev);
887 pci_disable_device(priv->pdev);
888 }
889
890 /* Disable the bus on older machines and the cell on kauai */
891 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
892 priv->aapl_bus_id, 0);
893
894 return 0;
895 }
896
pata_macio_do_resume(struct pata_macio_priv * priv)897 static int pata_macio_do_resume(struct pata_macio_priv *priv)
898 {
899 /* Reset and re-enable the HW */
900 pata_macio_reset_hw(priv, 1);
901
902 /* Sanitize drive timings */
903 pata_macio_apply_timings(priv->host->ports[0], 0);
904
905 /* We want our IRQ back ! */
906 enable_irq(priv->irq);
907
908 /* Let the libata core take it from there */
909 ata_host_resume(priv->host);
910
911 return 0;
912 }
913 #endif /* CONFIG_PM_SLEEP */
914
915 static const struct scsi_host_template pata_macio_sht = {
916 __ATA_BASE_SHT(DRV_NAME),
917 .sg_tablesize = MAX_DCMDS,
918 /* We may not need that strict one */
919 .dma_boundary = ATA_DMA_BOUNDARY,
920 /* Not sure what the real max is but we know it's less than 64K, let's
921 * use 64K minus 256
922 */
923 .max_segment_size = MAX_DBDMA_SEG,
924 .slave_configure = pata_macio_slave_config,
925 .sdev_groups = ata_common_sdev_groups,
926 .can_queue = ATA_DEF_QUEUE,
927 .tag_alloc_policy = BLK_TAG_ALLOC_RR,
928 };
929
930 static struct ata_port_operations pata_macio_ops = {
931 .inherits = &ata_bmdma_port_ops,
932
933 .freeze = pata_macio_freeze,
934 .set_piomode = pata_macio_set_timings,
935 .set_dmamode = pata_macio_set_timings,
936 .cable_detect = pata_macio_cable_detect,
937 .sff_dev_select = pata_macio_dev_select,
938 .qc_prep = pata_macio_qc_prep,
939 .bmdma_setup = pata_macio_bmdma_setup,
940 .bmdma_start = pata_macio_bmdma_start,
941 .bmdma_stop = pata_macio_bmdma_stop,
942 .bmdma_status = pata_macio_bmdma_status,
943 .port_start = pata_macio_port_start,
944 .sff_irq_clear = pata_macio_irq_clear,
945 };
946
pata_macio_invariants(struct pata_macio_priv * priv)947 static void pata_macio_invariants(struct pata_macio_priv *priv)
948 {
949 const int *bidp;
950
951 /* Identify the type of controller */
952 if (of_device_is_compatible(priv->node, "shasta-ata")) {
953 priv->kind = controller_sh_ata6;
954 priv->timings = pata_macio_shasta_timings;
955 } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
956 priv->kind = controller_un_ata6;
957 priv->timings = pata_macio_kauai_timings;
958 } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
959 priv->kind = controller_k2_ata6;
960 priv->timings = pata_macio_kauai_timings;
961 } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
962 if (of_node_name_eq(priv->node, "ata-4")) {
963 priv->kind = controller_kl_ata4;
964 priv->timings = pata_macio_kl66_timings;
965 } else {
966 priv->kind = controller_kl_ata3;
967 priv->timings = pata_macio_kl33_timings;
968 }
969 } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
970 priv->kind = controller_heathrow;
971 priv->timings = pata_macio_heathrow_timings;
972 } else {
973 priv->kind = controller_ohare;
974 priv->timings = pata_macio_ohare_timings;
975 }
976
977 /* XXX FIXME --- setup priv->mediabay here */
978
979 /* Get Apple bus ID (for clock and ASIC control) */
980 bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
981 priv->aapl_bus_id = bidp ? *bidp : 0;
982
983 /* Fixup missing Apple bus ID in case of media-bay */
984 if (priv->mediabay && !bidp)
985 priv->aapl_bus_id = 1;
986 }
987
pata_macio_setup_ios(struct ata_ioports * ioaddr,void __iomem * base,void __iomem * dma)988 static void pata_macio_setup_ios(struct ata_ioports *ioaddr,
989 void __iomem * base, void __iomem * dma)
990 {
991 /* cmd_addr is the base of regs for that port */
992 ioaddr->cmd_addr = base;
993
994 /* taskfile registers */
995 ioaddr->data_addr = base + (ATA_REG_DATA << 4);
996 ioaddr->error_addr = base + (ATA_REG_ERR << 4);
997 ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
998 ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
999 ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
1000 ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
1001 ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
1002 ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
1003 ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
1004 ioaddr->command_addr = base + (ATA_REG_CMD << 4);
1005 ioaddr->altstatus_addr = base + 0x160;
1006 ioaddr->ctl_addr = base + 0x160;
1007 ioaddr->bmdma_addr = dma;
1008 }
1009
pmac_macio_calc_timing_masks(struct pata_macio_priv * priv,struct ata_port_info * pinfo)1010 static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
1011 struct ata_port_info *pinfo)
1012 {
1013 int i = 0;
1014
1015 pinfo->pio_mask = 0;
1016 pinfo->mwdma_mask = 0;
1017 pinfo->udma_mask = 0;
1018
1019 while (priv->timings[i].mode > 0) {
1020 unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
1021 switch(priv->timings[i].mode & 0xf0) {
1022 case 0x00: /* PIO */
1023 pinfo->pio_mask |= (mask >> 8);
1024 break;
1025 case 0x20: /* MWDMA */
1026 pinfo->mwdma_mask |= mask;
1027 break;
1028 case 0x40: /* UDMA */
1029 pinfo->udma_mask |= mask;
1030 break;
1031 }
1032 i++;
1033 }
1034 dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n",
1035 pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
1036 }
1037
pata_macio_common_init(struct pata_macio_priv * priv,resource_size_t tfregs,resource_size_t dmaregs,resource_size_t fcregs,unsigned long irq)1038 static int pata_macio_common_init(struct pata_macio_priv *priv,
1039 resource_size_t tfregs,
1040 resource_size_t dmaregs,
1041 resource_size_t fcregs,
1042 unsigned long irq)
1043 {
1044 struct ata_port_info pinfo;
1045 const struct ata_port_info *ppi[] = { &pinfo, NULL };
1046 void __iomem *dma_regs = NULL;
1047
1048 /* Fill up privates with various invariants collected from the
1049 * device-tree
1050 */
1051 pata_macio_invariants(priv);
1052
1053 /* Make sure we have sane initial timings in the cache */
1054 pata_macio_default_timings(priv);
1055
1056 /* Allocate libata host for 1 port */
1057 memset(&pinfo, 0, sizeof(struct ata_port_info));
1058 pmac_macio_calc_timing_masks(priv, &pinfo);
1059 pinfo.flags = ATA_FLAG_SLAVE_POSS;
1060 pinfo.port_ops = &pata_macio_ops;
1061 pinfo.private_data = priv;
1062
1063 priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
1064 if (priv->host == NULL) {
1065 dev_err(priv->dev, "Failed to allocate ATA port structure\n");
1066 return -ENOMEM;
1067 }
1068
1069 /* Setup the private data in host too */
1070 priv->host->private_data = priv;
1071
1072 /* Map base registers */
1073 priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
1074 if (priv->tfregs == NULL) {
1075 dev_err(priv->dev, "Failed to map ATA ports\n");
1076 return -ENOMEM;
1077 }
1078 priv->host->iomap = &priv->tfregs;
1079
1080 /* Map DMA regs */
1081 if (dmaregs != 0) {
1082 dma_regs = devm_ioremap(priv->dev, dmaregs,
1083 sizeof(struct dbdma_regs));
1084 if (dma_regs == NULL)
1085 dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
1086 }
1087
1088 /* If chip has local feature control, map those regs too */
1089 if (fcregs != 0) {
1090 priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
1091 if (priv->kauai_fcr == NULL) {
1092 dev_err(priv->dev, "Failed to map ATA FCR register\n");
1093 return -ENOMEM;
1094 }
1095 }
1096
1097 /* Setup port data structure */
1098 pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
1099 priv->tfregs, dma_regs);
1100 priv->host->ports[0]->private_data = priv;
1101
1102 /* hard-reset the controller */
1103 pata_macio_reset_hw(priv, 0);
1104 pata_macio_apply_timings(priv->host->ports[0], 0);
1105
1106 /* Enable bus master if necessary */
1107 if (priv->pdev && dma_regs)
1108 pci_set_master(priv->pdev);
1109
1110 dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
1111 macio_ata_names[priv->kind], priv->aapl_bus_id);
1112
1113 /* Start it up */
1114 priv->irq = irq;
1115 return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
1116 &pata_macio_sht);
1117 }
1118
pata_macio_attach(struct macio_dev * mdev,const struct of_device_id * match)1119 static int pata_macio_attach(struct macio_dev *mdev,
1120 const struct of_device_id *match)
1121 {
1122 struct pata_macio_priv *priv;
1123 resource_size_t tfregs, dmaregs = 0;
1124 unsigned long irq;
1125 int rc;
1126
1127 /* Check for broken device-trees */
1128 if (macio_resource_count(mdev) == 0) {
1129 dev_err(&mdev->ofdev.dev,
1130 "No addresses for controller\n");
1131 return -ENXIO;
1132 }
1133
1134 /* Enable managed resources */
1135 macio_enable_devres(mdev);
1136
1137 /* Allocate and init private data structure */
1138 priv = devm_kzalloc(&mdev->ofdev.dev,
1139 sizeof(struct pata_macio_priv), GFP_KERNEL);
1140 if (!priv)
1141 return -ENOMEM;
1142
1143 priv->node = of_node_get(mdev->ofdev.dev.of_node);
1144 priv->mdev = mdev;
1145 priv->dev = &mdev->ofdev.dev;
1146
1147 /* Request memory resource for taskfile registers */
1148 if (macio_request_resource(mdev, 0, "pata-macio")) {
1149 dev_err(&mdev->ofdev.dev,
1150 "Cannot obtain taskfile resource\n");
1151 return -EBUSY;
1152 }
1153 tfregs = macio_resource_start(mdev, 0);
1154
1155 /* Request resources for DMA registers if any */
1156 if (macio_resource_count(mdev) >= 2) {
1157 if (macio_request_resource(mdev, 1, "pata-macio-dma"))
1158 dev_err(&mdev->ofdev.dev,
1159 "Cannot obtain DMA resource\n");
1160 else
1161 dmaregs = macio_resource_start(mdev, 1);
1162 }
1163
1164 /*
1165 * Fixup missing IRQ for some old implementations with broken
1166 * device-trees.
1167 *
1168 * This is a bit bogus, it should be fixed in the device-tree itself,
1169 * via the existing macio fixups, based on the type of interrupt
1170 * controller in the machine. However, I have no test HW for this case,
1171 * and this trick works well enough on those old machines...
1172 */
1173 if (macio_irq_count(mdev) == 0) {
1174 dev_warn(&mdev->ofdev.dev,
1175 "No interrupts for controller, using 13\n");
1176 irq = irq_create_mapping(NULL, 13);
1177 } else
1178 irq = macio_irq(mdev, 0);
1179
1180 /* Prevvent media bay callbacks until fully registered */
1181 lock_media_bay(priv->mdev->media_bay);
1182
1183 /* Get register addresses and call common initialization */
1184 rc = pata_macio_common_init(priv,
1185 tfregs, /* Taskfile regs */
1186 dmaregs, /* DBDMA regs */
1187 0, /* Feature control */
1188 irq);
1189 unlock_media_bay(priv->mdev->media_bay);
1190
1191 return rc;
1192 }
1193
pata_macio_detach(struct macio_dev * mdev)1194 static int pata_macio_detach(struct macio_dev *mdev)
1195 {
1196 struct ata_host *host = macio_get_drvdata(mdev);
1197 struct pata_macio_priv *priv = host->private_data;
1198
1199 lock_media_bay(priv->mdev->media_bay);
1200
1201 /* Make sure the mediabay callback doesn't try to access
1202 * dead stuff
1203 */
1204 priv->host->private_data = NULL;
1205
1206 ata_host_detach(host);
1207
1208 unlock_media_bay(priv->mdev->media_bay);
1209
1210 return 0;
1211 }
1212
1213 #ifdef CONFIG_PM_SLEEP
pata_macio_suspend(struct macio_dev * mdev,pm_message_t mesg)1214 static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1215 {
1216 struct ata_host *host = macio_get_drvdata(mdev);
1217
1218 return pata_macio_do_suspend(host->private_data, mesg);
1219 }
1220
pata_macio_resume(struct macio_dev * mdev)1221 static int pata_macio_resume(struct macio_dev *mdev)
1222 {
1223 struct ata_host *host = macio_get_drvdata(mdev);
1224
1225 return pata_macio_do_resume(host->private_data);
1226 }
1227 #endif /* CONFIG_PM_SLEEP */
1228
1229 #ifdef CONFIG_PMAC_MEDIABAY
pata_macio_mb_event(struct macio_dev * mdev,int mb_state)1230 static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
1231 {
1232 struct ata_host *host = macio_get_drvdata(mdev);
1233 struct ata_port *ap;
1234 struct ata_eh_info *ehi;
1235 struct ata_device *dev;
1236 unsigned long flags;
1237
1238 if (!host || !host->private_data)
1239 return;
1240 ap = host->ports[0];
1241 spin_lock_irqsave(ap->lock, flags);
1242 ehi = &ap->link.eh_info;
1243 if (mb_state == MB_CD) {
1244 ata_ehi_push_desc(ehi, "mediabay plug");
1245 ata_ehi_hotplugged(ehi);
1246 ata_port_freeze(ap);
1247 } else {
1248 ata_ehi_push_desc(ehi, "mediabay unplug");
1249 ata_for_each_dev(dev, &ap->link, ALL)
1250 dev->flags |= ATA_DFLAG_DETACH;
1251 ata_port_abort(ap);
1252 }
1253 spin_unlock_irqrestore(ap->lock, flags);
1254
1255 }
1256 #endif /* CONFIG_PMAC_MEDIABAY */
1257
1258
pata_macio_pci_attach(struct pci_dev * pdev,const struct pci_device_id * id)1259 static int pata_macio_pci_attach(struct pci_dev *pdev,
1260 const struct pci_device_id *id)
1261 {
1262 struct pata_macio_priv *priv;
1263 struct device_node *np;
1264 resource_size_t rbase;
1265
1266 /* We cannot use a MacIO controller without its OF device node */
1267 np = pci_device_to_OF_node(pdev);
1268 if (np == NULL) {
1269 dev_err(&pdev->dev,
1270 "Cannot find OF device node for controller\n");
1271 return -ENODEV;
1272 }
1273
1274 /* Check that it can be enabled */
1275 if (pcim_enable_device(pdev)) {
1276 dev_err(&pdev->dev,
1277 "Cannot enable controller PCI device\n");
1278 return -ENXIO;
1279 }
1280
1281 /* Allocate and init private data structure */
1282 priv = devm_kzalloc(&pdev->dev,
1283 sizeof(struct pata_macio_priv), GFP_KERNEL);
1284 if (!priv)
1285 return -ENOMEM;
1286
1287 priv->node = of_node_get(np);
1288 priv->pdev = pdev;
1289 priv->dev = &pdev->dev;
1290
1291 /* Get MMIO regions */
1292 if (pci_request_regions(pdev, "pata-macio")) {
1293 dev_err(&pdev->dev,
1294 "Cannot obtain PCI resources\n");
1295 return -EBUSY;
1296 }
1297
1298 /* Get register addresses and call common initialization */
1299 rbase = pci_resource_start(pdev, 0);
1300 if (pata_macio_common_init(priv,
1301 rbase + 0x2000, /* Taskfile regs */
1302 rbase + 0x1000, /* DBDMA regs */
1303 rbase, /* Feature control */
1304 pdev->irq))
1305 return -ENXIO;
1306
1307 return 0;
1308 }
1309
pata_macio_pci_detach(struct pci_dev * pdev)1310 static void pata_macio_pci_detach(struct pci_dev *pdev)
1311 {
1312 struct ata_host *host = pci_get_drvdata(pdev);
1313
1314 ata_host_detach(host);
1315 }
1316
1317 #ifdef CONFIG_PM_SLEEP
pata_macio_pci_suspend(struct pci_dev * pdev,pm_message_t mesg)1318 static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1319 {
1320 struct ata_host *host = pci_get_drvdata(pdev);
1321
1322 return pata_macio_do_suspend(host->private_data, mesg);
1323 }
1324
pata_macio_pci_resume(struct pci_dev * pdev)1325 static int pata_macio_pci_resume(struct pci_dev *pdev)
1326 {
1327 struct ata_host *host = pci_get_drvdata(pdev);
1328
1329 return pata_macio_do_resume(host->private_data);
1330 }
1331 #endif /* CONFIG_PM_SLEEP */
1332
1333 static const struct of_device_id pata_macio_match[] =
1334 {
1335 { .name = "IDE", },
1336 { .name = "ATA", },
1337 { .type = "ide", },
1338 { .type = "ata", },
1339 { /* sentinel */ }
1340 };
1341 MODULE_DEVICE_TABLE(of, pata_macio_match);
1342
1343 static struct macio_driver pata_macio_driver =
1344 {
1345 .driver = {
1346 .name = "pata-macio",
1347 .owner = THIS_MODULE,
1348 .of_match_table = pata_macio_match,
1349 },
1350 .probe = pata_macio_attach,
1351 .remove = pata_macio_detach,
1352 #ifdef CONFIG_PM_SLEEP
1353 .suspend = pata_macio_suspend,
1354 .resume = pata_macio_resume,
1355 #endif
1356 #ifdef CONFIG_PMAC_MEDIABAY
1357 .mediabay_event = pata_macio_mb_event,
1358 #endif
1359 };
1360
1361 static const struct pci_device_id pata_macio_pci_match[] = {
1362 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1363 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1364 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1365 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1366 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1367 {},
1368 };
1369
1370 static struct pci_driver pata_macio_pci_driver = {
1371 .name = "pata-pci-macio",
1372 .id_table = pata_macio_pci_match,
1373 .probe = pata_macio_pci_attach,
1374 .remove = pata_macio_pci_detach,
1375 #ifdef CONFIG_PM_SLEEP
1376 .suspend = pata_macio_pci_suspend,
1377 .resume = pata_macio_pci_resume,
1378 #endif
1379 .driver = {
1380 .owner = THIS_MODULE,
1381 },
1382 };
1383 MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
1384
1385
pata_macio_init(void)1386 static int __init pata_macio_init(void)
1387 {
1388 int rc;
1389
1390 if (!machine_is(powermac))
1391 return -ENODEV;
1392
1393 rc = pci_register_driver(&pata_macio_pci_driver);
1394 if (rc)
1395 return rc;
1396 rc = macio_register_driver(&pata_macio_driver);
1397 if (rc) {
1398 pci_unregister_driver(&pata_macio_pci_driver);
1399 return rc;
1400 }
1401 return 0;
1402 }
1403
pata_macio_exit(void)1404 static void __exit pata_macio_exit(void)
1405 {
1406 macio_unregister_driver(&pata_macio_driver);
1407 pci_unregister_driver(&pata_macio_pci_driver);
1408 }
1409
1410 module_init(pata_macio_init);
1411 module_exit(pata_macio_exit);
1412
1413 MODULE_AUTHOR("Benjamin Herrenschmidt");
1414 MODULE_DESCRIPTION("Apple MacIO PATA driver");
1415 MODULE_LICENSE("GPL");
1416 MODULE_VERSION(DRV_VERSION);
1417