xref: /openbmc/u-boot/drivers/mmc/tmio-common.h (revision e35171e9)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Socionext Inc.
4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5  */
6 
7 #ifndef __TMIO_COMMON_H__
8 #define __TMIO_COMMON_H__
9 
10 #define TMIO_SD_CMD			0x000	/* command */
11 #define   TMIO_SD_CMD_NOSTOP		BIT(14)	/* No automatic CMD12 issue */
12 #define   TMIO_SD_CMD_MULTI		BIT(13)	/* multiple block transfer */
13 #define   TMIO_SD_CMD_RD		BIT(12)	/* 1: read, 0: write */
14 #define   TMIO_SD_CMD_DATA		BIT(11)	/* data transfer */
15 #define   TMIO_SD_CMD_APP		BIT(6)	/* ACMD preceded by CMD55 */
16 #define   TMIO_SD_CMD_NORMAL		(0 << 8)/* auto-detect of resp-type */
17 #define   TMIO_SD_CMD_RSP_NONE		(3 << 8)/* response: none */
18 #define   TMIO_SD_CMD_RSP_R1		(4 << 8)/* response: R1, R5, R6, R7 */
19 #define   TMIO_SD_CMD_RSP_R1B		(5 << 8)/* response: R1b, R5b */
20 #define   TMIO_SD_CMD_RSP_R2		(6 << 8)/* response: R2 */
21 #define   TMIO_SD_CMD_RSP_R3		(7 << 8)/* response: R3, R4 */
22 #define TMIO_SD_ARG			0x008	/* command argument */
23 #define TMIO_SD_STOP			0x010	/* stop action control */
24 #define   TMIO_SD_STOP_SEC		BIT(8)	/* use sector count */
25 #define   TMIO_SD_STOP_STP		BIT(0)	/* issue CMD12 */
26 #define TMIO_SD_SECCNT			0x014	/* sector counter */
27 #define TMIO_SD_RSP10			0x018	/* response[39:8] */
28 #define TMIO_SD_RSP32			0x020	/* response[71:40] */
29 #define TMIO_SD_RSP54			0x028	/* response[103:72] */
30 #define TMIO_SD_RSP76			0x030	/* response[127:104] */
31 #define TMIO_SD_INFO1			0x038	/* IRQ status 1 */
32 #define   TMIO_SD_INFO1_CD		BIT(5)	/* state of card detect */
33 #define   TMIO_SD_INFO1_INSERT		BIT(4)	/* card inserted */
34 #define   TMIO_SD_INFO1_REMOVE		BIT(3)	/* card removed */
35 #define   TMIO_SD_INFO1_CMP		BIT(2)	/* data complete */
36 #define   TMIO_SD_INFO1_RSP		BIT(0)	/* response complete */
37 #define TMIO_SD_INFO2			0x03c	/* IRQ status 2 */
38 #define   TMIO_SD_INFO2_ERR_ILA	BIT(15)	/* illegal access err */
39 #define   TMIO_SD_INFO2_CBSY		BIT(14)	/* command busy */
40 #define   TMIO_SD_INFO2_SCLKDIVEN	BIT(13)	/* command setting reg ena */
41 #define   TMIO_SD_INFO2_BWE		BIT(9)	/* write buffer ready */
42 #define   TMIO_SD_INFO2_BRE		BIT(8)	/* read buffer ready */
43 #define   TMIO_SD_INFO2_DAT0		BIT(7)	/* SDDAT0 */
44 #define   TMIO_SD_INFO2_ERR_RTO	BIT(6)	/* response time out */
45 #define   TMIO_SD_INFO2_ERR_ILR	BIT(5)	/* illegal read err */
46 #define   TMIO_SD_INFO2_ERR_ILW	BIT(4)	/* illegal write err */
47 #define   TMIO_SD_INFO2_ERR_TO		BIT(3)	/* time out error */
48 #define   TMIO_SD_INFO2_ERR_END	BIT(2)	/* END bit error */
49 #define   TMIO_SD_INFO2_ERR_CRC	BIT(1)	/* CRC error */
50 #define   TMIO_SD_INFO2_ERR_IDX	BIT(0)	/* cmd index error */
51 #define TMIO_SD_INFO1_MASK		0x040
52 #define TMIO_SD_INFO2_MASK		0x044
53 #define TMIO_SD_CLKCTL			0x048	/* clock divisor */
54 #define   TMIO_SD_CLKCTL_DIV_MASK	0x104ff
55 #define   TMIO_SD_CLKCTL_DIV1024	BIT(16)	/* SDCLK = CLK / 1024 */
56 #define   TMIO_SD_CLKCTL_DIV512	BIT(7)	/* SDCLK = CLK / 512 */
57 #define   TMIO_SD_CLKCTL_DIV256	BIT(6)	/* SDCLK = CLK / 256 */
58 #define   TMIO_SD_CLKCTL_DIV128	BIT(5)	/* SDCLK = CLK / 128 */
59 #define   TMIO_SD_CLKCTL_DIV64		BIT(4)	/* SDCLK = CLK / 64 */
60 #define   TMIO_SD_CLKCTL_DIV32		BIT(3)	/* SDCLK = CLK / 32 */
61 #define   TMIO_SD_CLKCTL_DIV16		BIT(2)	/* SDCLK = CLK / 16 */
62 #define   TMIO_SD_CLKCTL_DIV8		BIT(1)	/* SDCLK = CLK / 8 */
63 #define   TMIO_SD_CLKCTL_DIV4		BIT(0)	/* SDCLK = CLK / 4 */
64 #define   TMIO_SD_CLKCTL_DIV2		0	/* SDCLK = CLK / 2 */
65 #define   TMIO_SD_CLKCTL_DIV1		BIT(10)	/* SDCLK = CLK */
66 #define   TMIO_SD_CLKCTL_RCAR_DIV1	0xff	/* SDCLK = CLK (RCar ver.) */
67 #define   TMIO_SD_CLKCTL_OFFEN		BIT(9)	/* stop SDCLK when unused */
68 #define   TMIO_SD_CLKCTL_SCLKEN	BIT(8)	/* SDCLK output enable */
69 #define TMIO_SD_SIZE			0x04c	/* block size */
70 #define TMIO_SD_OPTION			0x050
71 #define   TMIO_SD_OPTION_WIDTH_MASK	(5 << 13)
72 #define   TMIO_SD_OPTION_WIDTH_1	(4 << 13)
73 #define   TMIO_SD_OPTION_WIDTH_4	(0 << 13)
74 #define   TMIO_SD_OPTION_WIDTH_8	(1 << 13)
75 #define TMIO_SD_BUF			0x060	/* read/write buffer */
76 #define TMIO_SD_EXTMODE		0x1b0
77 #define   TMIO_SD_EXTMODE_DMA_EN	BIT(1)	/* transfer 1: DMA, 0: pio */
78 #define TMIO_SD_SOFT_RST		0x1c0
79 #define TMIO_SD_SOFT_RST_RSTX		BIT(0)	/* reset deassert */
80 #define TMIO_SD_VERSION		0x1c4	/* version register */
81 #define TMIO_SD_VERSION_IP		0xff	/* IP version */
82 #define TMIO_SD_HOST_MODE		0x1c8
83 #define TMIO_SD_IF_MODE		0x1cc
84 #define   TMIO_SD_IF_MODE_DDR		BIT(0)	/* DDR mode */
85 #define TMIO_SD_VOLT			0x1e4	/* voltage switch */
86 #define   TMIO_SD_VOLT_MASK		(3 << 0)
87 #define   TMIO_SD_VOLT_OFF		(0 << 0)
88 #define   TMIO_SD_VOLT_330		(1 << 0)/* 3.3V signal */
89 #define   TMIO_SD_VOLT_180		(2 << 0)/* 1.8V signal */
90 #define TMIO_SD_DMA_MODE		0x410
91 #define   TMIO_SD_DMA_MODE_DIR_RD	BIT(16)	/* 1: from device, 0: to dev */
92 #define   TMIO_SD_DMA_MODE_ADDR_INC	BIT(0)	/* 1: address inc, 0: fixed */
93 #define TMIO_SD_DMA_CTL		0x414
94 #define   TMIO_SD_DMA_CTL_START	BIT(0)	/* start DMA (auto cleared) */
95 #define TMIO_SD_DMA_RST		0x418
96 #define   TMIO_SD_DMA_RST_RD		BIT(9)
97 #define   TMIO_SD_DMA_RST_WR		BIT(8)
98 #define TMIO_SD_DMA_INFO1		0x420
99 #define   TMIO_SD_DMA_INFO1_END_RD2	BIT(20)	/* DMA from device is complete (uniphier) */
100 #define   TMIO_SD_DMA_INFO1_END_RD	BIT(17)	/* DMA from device is complete (renesas) */
101 #define   TMIO_SD_DMA_INFO1_END_WR	BIT(16)	/* DMA to device is complete */
102 #define TMIO_SD_DMA_INFO1_MASK		0x424
103 #define TMIO_SD_DMA_INFO2		0x428
104 #define   TMIO_SD_DMA_INFO2_ERR_RD	BIT(17)
105 #define   TMIO_SD_DMA_INFO2_ERR_WR	BIT(16)
106 #define TMIO_SD_DMA_INFO2_MASK		0x42c
107 #define TMIO_SD_DMA_ADDR_L		0x440
108 #define TMIO_SD_DMA_ADDR_H		0x444
109 
110 /* alignment required by the DMA engine of this controller */
111 #define TMIO_SD_DMA_MINALIGN		0x10
112 
113 struct tmio_sd_plat {
114 	struct mmc_config		cfg;
115 	struct mmc			mmc;
116 };
117 
118 struct tmio_sd_priv {
119 	void __iomem			*regbase;
120 	unsigned int			version;
121 	u32				caps;
122 	u32				read_poll_flag;
123 #define TMIO_SD_CAP_NONREMOVABLE	BIT(0)	/* Nonremovable e.g. eMMC */
124 #define TMIO_SD_CAP_DMA_INTERNAL	BIT(1)	/* have internal DMA engine */
125 #define TMIO_SD_CAP_DIV1024		BIT(2)	/* divisor 1024 is available */
126 #define TMIO_SD_CAP_64BIT		BIT(3)	/* Controller is 64bit */
127 #define TMIO_SD_CAP_16BIT		BIT(4)	/* Controller is 16bit */
128 #define TMIO_SD_CAP_RCAR_GEN2		BIT(5)	/* Renesas RCar version of IP */
129 #define TMIO_SD_CAP_RCAR_GEN3		BIT(6)	/* Renesas RCar version of IP */
130 #define TMIO_SD_CAP_RCAR_UHS		BIT(7)	/* Renesas RCar UHS/SDR modes */
131 #define TMIO_SD_CAP_RCAR		\
132 	(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
133 #ifdef CONFIG_DM_REGULATOR
134 	struct udevice *vqmmc_dev;
135 #endif
136 #if CONFIG_IS_ENABLED(CLK)
137 	struct clk			clk;
138 #endif
139 #if CONFIG_IS_ENABLED(RENESAS_SDHI)
140 	u8				tap_set;
141 	u8				nrtaps;
142 #endif
143 	ulong (*clk_get_rate)(struct tmio_sd_priv *);
144 };
145 
146 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
147 		      struct mmc_data *data);
148 int tmio_sd_set_ios(struct udevice *dev);
149 int tmio_sd_get_cd(struct udevice *dev);
150 
151 int tmio_sd_bind(struct udevice *dev);
152 int tmio_sd_probe(struct udevice *dev, u32 quirks);
153 
154 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg);
155 void tmio_sd_writel(struct tmio_sd_priv *priv,
156 		     u32 val, unsigned int reg);
157 
158 #endif /* __TMIO_COMMON_H__ */
159