xref: /openbmc/qemu/target/microblaze/mmu.h (revision 3cb1a410)
1 /*
2  *  Microblaze MMU emulation for qemu.
3  *
4  *  Copyright (c) 2009 Edgar E. Iglesias
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef TARGET_MICROBLAZE_MMU_H
21 #define TARGET_MICROBLAZE_MMU_H
22 
23 #include "cpu.h"
24 
25 #define MMU_R_PID    0
26 #define MMU_R_ZPR    1
27 #define MMU_R_TLBX   2
28 #define MMU_R_TLBLO  3
29 #define MMU_R_TLBHI  4
30 #define MMU_R_TLBSX  5
31 
32 #define RAM_DATA     1
33 #define RAM_TAG      0
34 
35 /* Tag portion */
36 #define TLB_EPN_MASK          MAKE_64BIT_MASK(10, 64 - 10)
37 #define TLB_PAGESZ_MASK       0x00000380
38 #define TLB_PAGESZ(x)         (((x) & 0x7) << 7)
39 #define PAGESZ_1K             0
40 #define PAGESZ_4K             1
41 #define PAGESZ_16K            2
42 #define PAGESZ_64K            3
43 #define PAGESZ_256K           4
44 #define PAGESZ_1M             5
45 #define PAGESZ_4M             6
46 #define PAGESZ_16M            7
47 #define TLB_VALID             0x00000040 /* Entry is valid */
48 
49 /* Data portion */
50 #define TLB_RPN_MASK          MAKE_64BIT_MASK(10, 64 - 10)
51 #define TLB_PERM_MASK         0x00000300
52 #define TLB_EX                0x00000200 /* Instruction execution allowed */
53 #define TLB_WR                0x00000100 /* Writes permitted */
54 #define TLB_ZSEL_MASK         0x000000F0
55 #define TLB_ZSEL(x)           (((x) & 0xF) << 4)
56 #define TLB_ATTR_MASK         0x0000000F
57 #define TLB_W                 0x00000008 /* Caching is write-through */
58 #define TLB_I                 0x00000004 /* Caching is inhibited */
59 #define TLB_M                 0x00000002 /* Memory is coherent */
60 #define TLB_G                 0x00000001 /* Memory is guarded from prefetch */
61 
62 /* TLBX  */
63 #define R_TBLX_MISS_SHIFT 31
64 #define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
65 
66 #define TLB_ENTRIES    64
67 
68 typedef struct {
69     /* Data and tag brams.  */
70     uint64_t rams[2][TLB_ENTRIES];
71     /* We keep a separate ram for the tids to avoid the 48 bit tag width.  */
72     uint8_t tids[TLB_ENTRIES];
73     /* Control flops.  */
74     uint32_t regs[3];
75 } MicroBlazeMMU;
76 
77 typedef struct {
78     uint32_t paddr;
79     uint32_t vaddr;
80     unsigned int size;
81     unsigned int idx;
82     int prot;
83     enum {
84         ERR_PROT, ERR_MISS, ERR_HIT
85     } err;
86 } MicroBlazeMMULookup;
87 
88 unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
89                            target_ulong vaddr, MMUAccessType rw, int mmu_idx);
90 uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
91 void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
92 void mmu_init(MicroBlazeMMU *mmu);
93 
94 #endif
95