xref: /openbmc/linux/drivers/firmware/ti_sci.h (revision 3c201753)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Texas Instruments System Control Interface (TISCI) Protocol
4  *
5  * Communication protocol with TI SCI hardware
6  * The system works in a message response protocol
7  * See: http://processors.wiki.ti.com/index.php/TISCI for details
8  *
9  * Copyright (C)  2015-2016 Texas Instruments Incorporated - https://www.ti.com/
10  */
11 
12 #ifndef __TI_SCI_H
13 #define __TI_SCI_H
14 
15 /* Generic Messages */
16 #define TI_SCI_MSG_ENABLE_WDT	0x0000
17 #define TI_SCI_MSG_WAKE_RESET	0x0001
18 #define TI_SCI_MSG_VERSION	0x0002
19 #define TI_SCI_MSG_WAKE_REASON	0x0003
20 #define TI_SCI_MSG_GOODBYE	0x0004
21 #define TI_SCI_MSG_SYS_RESET	0x0005
22 
23 /* Device requests */
24 #define TI_SCI_MSG_SET_DEVICE_STATE	0x0200
25 #define TI_SCI_MSG_GET_DEVICE_STATE	0x0201
26 #define TI_SCI_MSG_SET_DEVICE_RESETS	0x0202
27 
28 /* Clock requests */
29 #define TI_SCI_MSG_SET_CLOCK_STATE	0x0100
30 #define TI_SCI_MSG_GET_CLOCK_STATE	0x0101
31 #define TI_SCI_MSG_SET_CLOCK_PARENT	0x0102
32 #define TI_SCI_MSG_GET_CLOCK_PARENT	0x0103
33 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
34 #define TI_SCI_MSG_SET_CLOCK_FREQ	0x010c
35 #define TI_SCI_MSG_QUERY_CLOCK_FREQ	0x010d
36 #define TI_SCI_MSG_GET_CLOCK_FREQ	0x010e
37 
38 /* Resource Management Requests */
39 #define TI_SCI_MSG_GET_RESOURCE_RANGE	0x1500
40 
41 /* IRQ requests */
42 #define TI_SCI_MSG_SET_IRQ		0x1000
43 #define TI_SCI_MSG_FREE_IRQ		0x1001
44 
45 /* NAVSS resource management */
46 /* Ringacc requests */
47 #define TI_SCI_MSG_RM_RING_ALLOCATE		0x1100
48 #define TI_SCI_MSG_RM_RING_FREE			0x1101
49 #define TI_SCI_MSG_RM_RING_RECONFIG		0x1102
50 #define TI_SCI_MSG_RM_RING_RESET		0x1103
51 #define TI_SCI_MSG_RM_RING_CFG			0x1110
52 
53 /* PSI-L requests */
54 #define TI_SCI_MSG_RM_PSIL_PAIR			0x1280
55 #define TI_SCI_MSG_RM_PSIL_UNPAIR		0x1281
56 
57 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC		0x1200
58 #define TI_SCI_MSG_RM_UDMAP_TX_FREE		0x1201
59 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC		0x1210
60 #define TI_SCI_MSG_RM_UDMAP_RX_FREE		0x1211
61 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG		0x1220
62 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG	0x1221
63 
64 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG		0x1205
65 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG	0x1206
66 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG		0x1215
67 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG	0x1216
68 #define TISCI_MSG_RM_UDMAP_FLOW_CFG		0x1230
69 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG	0x1231
70 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG		0x1232
71 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG	0x1233
72 
73 /* Processor Control requests */
74 #define TI_SCI_MSG_PROC_REQUEST		0xc000
75 #define TI_SCI_MSG_PROC_RELEASE		0xc001
76 #define TI_SCI_MSG_PROC_HANDOVER	0xc005
77 #define TI_SCI_MSG_SET_CONFIG		0xc100
78 #define TI_SCI_MSG_SET_CTRL		0xc101
79 #define TI_SCI_MSG_GET_STATUS		0xc400
80 
81 /**
82  * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
83  * @type:	Type of messages: One of TI_SCI_MSG* values
84  * @host:	Host of the message
85  * @seq:	Message identifier indicating a transfer sequence
86  * @flags:	Flag for the message
87  */
88 struct ti_sci_msg_hdr {
89 	u16 type;
90 	u8 host;
91 	u8 seq;
92 #define TI_SCI_MSG_FLAG(val)			(1 << (val))
93 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE	0x0
94 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED		TI_SCI_MSG_FLAG(0)
95 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED	TI_SCI_MSG_FLAG(1)
96 #define TI_SCI_FLAG_RESP_GENERIC_NACK		0x0
97 #define TI_SCI_FLAG_RESP_GENERIC_ACK		TI_SCI_MSG_FLAG(1)
98 	/* Additional Flags */
99 	u32 flags;
100 } __packed;
101 
102 /**
103  * struct ti_sci_msg_resp_version - Response for a message
104  * @hdr:		Generic header
105  * @firmware_description: String describing the firmware
106  * @firmware_revision:	Firmware revision
107  * @abi_major:		Major version of the ABI that firmware supports
108  * @abi_minor:		Minor version of the ABI that firmware supports
109  *
110  * In general, ABI version changes follow the rule that minor version increments
111  * are backward compatible. Major revision changes in ABI may not be
112  * backward compatible.
113  *
114  * Response to a generic message with message type TI_SCI_MSG_VERSION
115  */
116 struct ti_sci_msg_resp_version {
117 	struct ti_sci_msg_hdr hdr;
118 	char firmware_description[32];
119 	u16 firmware_revision;
120 	u8 abi_major;
121 	u8 abi_minor;
122 } __packed;
123 
124 /**
125  * struct ti_sci_msg_req_reboot - Reboot the SoC
126  * @hdr:	Generic Header
127  *
128  * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
129  * ACK/NACK message.
130  */
131 struct ti_sci_msg_req_reboot {
132 	struct ti_sci_msg_hdr hdr;
133 } __packed;
134 
135 /**
136  * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
137  * @hdr:		Generic header
138  * @id:	Indicates which device to modify
139  * @reserved: Reserved space in message, must be 0 for backward compatibility
140  * @state: The desired state of the device.
141  *
142  * Certain flags can also be set to alter the device state:
143  * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
144  * The meaning of this flag will vary slightly from device to device and from
145  * SoC to SoC but it generally allows the device to wake the SoC out of deep
146  * suspend states.
147  * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
148  * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
149  * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
150  * If another host already has this device set to STATE_RETENTION or STATE_ON,
151  * the message will fail. Once successful, other hosts attempting to set
152  * STATE_RETENTION or STATE_ON will fail.
153  *
154  * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
155  * ACK/NACK message.
156  */
157 struct ti_sci_msg_req_set_device_state {
158 	/* Additional hdr->flags options */
159 #define MSG_FLAG_DEVICE_WAKE_ENABLED	TI_SCI_MSG_FLAG(8)
160 #define MSG_FLAG_DEVICE_RESET_ISO	TI_SCI_MSG_FLAG(9)
161 #define MSG_FLAG_DEVICE_EXCLUSIVE	TI_SCI_MSG_FLAG(10)
162 	struct ti_sci_msg_hdr hdr;
163 	u32 id;
164 	u32 reserved;
165 
166 #define MSG_DEVICE_SW_STATE_AUTO_OFF	0
167 #define MSG_DEVICE_SW_STATE_RETENTION	1
168 #define MSG_DEVICE_SW_STATE_ON		2
169 	u8 state;
170 } __packed;
171 
172 /**
173  * struct ti_sci_msg_req_get_device_state - Request to get device.
174  * @hdr:		Generic header
175  * @id:		Device Identifier
176  *
177  * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
178  * information
179  */
180 struct ti_sci_msg_req_get_device_state {
181 	struct ti_sci_msg_hdr hdr;
182 	u32 id;
183 } __packed;
184 
185 /**
186  * struct ti_sci_msg_resp_get_device_state - Response to get device request.
187  * @hdr:		Generic header
188  * @context_loss_count: Indicates how many times the device has lost context. A
189  *	driver can use this monotonic counter to determine if the device has
190  *	lost context since the last time this message was exchanged.
191  * @resets: Programmed state of the reset lines.
192  * @programmed_state:	The state as programmed by set_device.
193  *			- Uses the MSG_DEVICE_SW_* macros
194  * @current_state:	The actual state of the hardware.
195  *
196  * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
197  */
198 struct ti_sci_msg_resp_get_device_state {
199 	struct ti_sci_msg_hdr hdr;
200 	u32 context_loss_count;
201 	u32 resets;
202 	u8 programmed_state;
203 #define MSG_DEVICE_HW_STATE_OFF		0
204 #define MSG_DEVICE_HW_STATE_ON		1
205 #define MSG_DEVICE_HW_STATE_TRANS	2
206 	u8 current_state;
207 } __packed;
208 
209 /**
210  * struct ti_sci_msg_req_set_device_resets - Set the desired resets
211  *				configuration of the device
212  * @hdr:		Generic header
213  * @id:	Indicates which device to modify
214  * @resets: A bit field of resets for the device. The meaning, behavior,
215  *	and usage of the reset flags are device specific. 0 for a bit
216  *	indicates releasing the reset represented by that bit while 1
217  *	indicates keeping it held.
218  *
219  * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
220  * ACK/NACK message.
221  */
222 struct ti_sci_msg_req_set_device_resets {
223 	struct ti_sci_msg_hdr hdr;
224 	u32 id;
225 	u32 resets;
226 } __packed;
227 
228 /**
229  * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
230  * @hdr:	Generic Header, Certain flags can be set specific to the clocks:
231  *		MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
232  *		via spread spectrum clocking.
233  *		MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
234  *		frequency to be changed while it is running so long as it
235  *		is within the min/max limits.
236  *		MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
237  *		is only applicable to clock inputs on the SoC pseudo-device.
238  * @dev_id:	Device identifier this request is for
239  * @clk_id:	Clock identifier for the device for this request.
240  *		Each device has it's own set of clock inputs. This indexes
241  *		which clock input to modify. Set to 255 if clock ID is
242  *		greater than or equal to 255.
243  * @request_state: Request the state for the clock to be set to.
244  *		MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
245  *		it can be disabled, regardless of the state of the device
246  *		MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
247  *		automatically manage the state of this clock. If the device
248  *		is enabled, then the clock is enabled. If the device is set
249  *		to off or retention, then the clock is internally set as not
250  *		being required by the device.(default)
251  *		MSG_CLOCK_SW_STATE_REQ:  Configure the clock to be enabled,
252  *		regardless of the state of the device.
253  * @clk_id_32:	Clock identifier for the device for this request.
254  *		Only to be used if the clock ID is greater than or equal to
255  *		255.
256  *
257  * Normally, all required clocks are managed by TISCI entity, this is used
258  * only for specific control *IF* required. Auto managed state is
259  * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
260  * will explicitly control.
261  *
262  * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
263  * ACK or NACK message.
264  */
265 struct ti_sci_msg_req_set_clock_state {
266 	/* Additional hdr->flags options */
267 #define MSG_FLAG_CLOCK_ALLOW_SSC		TI_SCI_MSG_FLAG(8)
268 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE	TI_SCI_MSG_FLAG(9)
269 #define MSG_FLAG_CLOCK_INPUT_TERM		TI_SCI_MSG_FLAG(10)
270 	struct ti_sci_msg_hdr hdr;
271 	u32 dev_id;
272 	u8 clk_id;
273 #define MSG_CLOCK_SW_STATE_UNREQ	0
274 #define MSG_CLOCK_SW_STATE_AUTO		1
275 #define MSG_CLOCK_SW_STATE_REQ		2
276 	u8 request_state;
277 	u32 clk_id_32;
278 } __packed;
279 
280 /**
281  * struct ti_sci_msg_req_get_clock_state - Request for clock state
282  * @hdr:	Generic Header
283  * @dev_id:	Device identifier this request is for
284  * @clk_id:	Clock identifier for the device for this request.
285  *		Each device has it's own set of clock inputs. This indexes
286  *		which clock input to get state of. Set to 255 if the clock
287  *		ID is greater than or equal to 255.
288  * @clk_id_32:	Clock identifier for the device for the request.
289  *		Only to be used if the clock ID is greater than or equal to
290  *		255.
291  *
292  * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
293  * of the clock
294  */
295 struct ti_sci_msg_req_get_clock_state {
296 	struct ti_sci_msg_hdr hdr;
297 	u32 dev_id;
298 	u8 clk_id;
299 	u32 clk_id_32;
300 } __packed;
301 
302 /**
303  * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
304  * @hdr:	Generic Header
305  * @programmed_state: Any programmed state of the clock. This is one of
306  *		MSG_CLOCK_SW_STATE* values.
307  * @current_state: Current state of the clock. This is one of:
308  *		MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
309  *		MSG_CLOCK_HW_STATE_READY: Clock is ready
310  *
311  * Response to TI_SCI_MSG_GET_CLOCK_STATE.
312  */
313 struct ti_sci_msg_resp_get_clock_state {
314 	struct ti_sci_msg_hdr hdr;
315 	u8 programmed_state;
316 #define MSG_CLOCK_HW_STATE_NOT_READY	0
317 #define MSG_CLOCK_HW_STATE_READY	1
318 	u8 current_state;
319 } __packed;
320 
321 /**
322  * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
323  * @hdr:	Generic Header
324  * @dev_id:	Device identifier this request is for
325  * @clk_id:	Clock identifier for the device for this request.
326  *		Each device has it's own set of clock inputs. This indexes
327  *		which clock input to modify. Set to 255 if clock ID is
328  *		greater than or equal to 255.
329  * @parent_id:	The new clock parent is selectable by an index via this
330  *		parameter. Set to 255 if clock ID is greater than or
331  *		equal to 255.
332  * @clk_id_32:	Clock identifier if @clk_id field is 255.
333  * @parent_id_32:	Parent identifier if @parent_id is 255.
334  *
335  * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
336  * ACK / NACK message.
337  */
338 struct ti_sci_msg_req_set_clock_parent {
339 	struct ti_sci_msg_hdr hdr;
340 	u32 dev_id;
341 	u8 clk_id;
342 	u8 parent_id;
343 	u32 clk_id_32;
344 	u32 parent_id_32;
345 } __packed;
346 
347 /**
348  * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
349  * @hdr:	Generic Header
350  * @dev_id:	Device identifier this request is for
351  * @clk_id:	Clock identifier for the device for this request.
352  *		Each device has it's own set of clock inputs. This indexes
353  *		which clock input to get the parent for. If this field
354  *		contains 255, the actual clock identifier is stored in
355  *		@clk_id_32.
356  * @clk_id_32:	Clock identifier if the @clk_id field contains 255.
357  *
358  * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
359  */
360 struct ti_sci_msg_req_get_clock_parent {
361 	struct ti_sci_msg_hdr hdr;
362 	u32 dev_id;
363 	u8 clk_id;
364 	u32 clk_id_32;
365 } __packed;
366 
367 /**
368  * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
369  * @hdr:	Generic Header
370  * @parent_id:	The current clock parent. If set to 255, the current parent
371  *		ID can be found from the @parent_id_32 field.
372  * @parent_id_32:	Current clock parent if @parent_id field is set to
373  *			255.
374  *
375  * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
376  */
377 struct ti_sci_msg_resp_get_clock_parent {
378 	struct ti_sci_msg_hdr hdr;
379 	u8 parent_id;
380 	u32 parent_id_32;
381 } __packed;
382 
383 /**
384  * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
385  * @hdr:	Generic header
386  * @dev_id:	Device identifier this request is for
387  * @clk_id:	Clock identifier for the device for this request. Set to
388  *		255 if clock ID is greater than or equal to 255.
389  * @clk_id_32:	Clock identifier if the @clk_id field contains 255.
390  *
391  * This request provides information about how many clock parent options
392  * are available for a given clock to a device. This is typically used
393  * for input clocks.
394  *
395  * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
396  * message, or NACK in case of inability to satisfy request.
397  */
398 struct ti_sci_msg_req_get_clock_num_parents {
399 	struct ti_sci_msg_hdr hdr;
400 	u32 dev_id;
401 	u8 clk_id;
402 	u32 clk_id_32;
403 } __packed;
404 
405 /**
406  * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
407  * @hdr:		Generic header
408  * @num_parents:	Number of clock parents. If set to 255, the actual
409  *			number of parents is stored into @num_parents_32
410  *			field instead.
411  * @num_parents_32:	Number of clock parents if @num_parents field is
412  *			set to 255.
413  *
414  * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
415  */
416 struct ti_sci_msg_resp_get_clock_num_parents {
417 	struct ti_sci_msg_hdr hdr;
418 	u8 num_parents;
419 	u32 num_parents_32;
420 } __packed;
421 
422 /**
423  * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
424  * @hdr:	Generic Header
425  * @dev_id:	Device identifier this request is for
426  * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
427  *		allowable programmed frequency and does not account for clock
428  *		tolerances and jitter.
429  * @target_freq_hz: The target clock frequency. A frequency will be found
430  *		as close to this target frequency as possible.
431  * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
432  *		allowable programmed frequency and does not account for clock
433  *		tolerances and jitter.
434  * @clk_id:	Clock identifier for the device for this request. Set to
435  *		255 if clock identifier is greater than or equal to 255.
436  * @clk_id_32:	Clock identifier if @clk_id is set to 255.
437  *
438  * NOTE: Normally clock frequency management is automatically done by TISCI
439  * entity. In case of specific requests, TISCI evaluates capability to achieve
440  * requested frequency within provided range and responds with
441  * result message.
442  *
443  * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
444  * or NACK in case of inability to satisfy request.
445  */
446 struct ti_sci_msg_req_query_clock_freq {
447 	struct ti_sci_msg_hdr hdr;
448 	u32 dev_id;
449 	u64 min_freq_hz;
450 	u64 target_freq_hz;
451 	u64 max_freq_hz;
452 	u8 clk_id;
453 	u32 clk_id_32;
454 } __packed;
455 
456 /**
457  * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
458  * @hdr:	Generic Header
459  * @freq_hz:	Frequency that is the best match in Hz.
460  *
461  * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
462  * cannot be satisfied, the message will be of type NACK.
463  */
464 struct ti_sci_msg_resp_query_clock_freq {
465 	struct ti_sci_msg_hdr hdr;
466 	u64 freq_hz;
467 } __packed;
468 
469 /**
470  * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
471  * @hdr:	Generic Header
472  * @dev_id:	Device identifier this request is for
473  * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
474  *		allowable programmed frequency and does not account for clock
475  *		tolerances and jitter.
476  * @target_freq_hz: The target clock frequency. The clock will be programmed
477  *		at a rate as close to this target frequency as possible.
478  * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
479  *		allowable programmed frequency and does not account for clock
480  *		tolerances and jitter.
481  * @clk_id:	Clock identifier for the device for this request. Set to
482  *		255 if clock ID is greater than or equal to 255.
483  * @clk_id_32:	Clock identifier if @clk_id field is set to 255.
484  *
485  * NOTE: Normally clock frequency management is automatically done by TISCI
486  * entity. In case of specific requests, TISCI evaluates capability to achieve
487  * requested range and responds with success/failure message.
488  *
489  * This sets the desired frequency for a clock within an allowable
490  * range. This message will fail on an enabled clock unless
491  * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
492  * if other clocks have their frequency modified due to this message,
493  * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
494  *
495  * Calling set frequency on a clock input to the SoC pseudo-device will
496  * inform the PMMC of that clock's frequency. Setting a frequency of
497  * zero will indicate the clock is disabled.
498  *
499  * Calling set frequency on clock outputs from the SoC pseudo-device will
500  * function similarly to setting the clock frequency on a device.
501  *
502  * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
503  * message.
504  */
505 struct ti_sci_msg_req_set_clock_freq {
506 	struct ti_sci_msg_hdr hdr;
507 	u32 dev_id;
508 	u64 min_freq_hz;
509 	u64 target_freq_hz;
510 	u64 max_freq_hz;
511 	u8 clk_id;
512 	u32 clk_id_32;
513 } __packed;
514 
515 /**
516  * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
517  * @hdr:	Generic Header
518  * @dev_id:	Device identifier this request is for
519  * @clk_id:	Clock identifier for the device for this request. Set to
520  *		255 if clock ID is greater than or equal to 255.
521  * @clk_id_32:	Clock identifier if @clk_id field is set to 255.
522  *
523  * NOTE: Normally clock frequency management is automatically done by TISCI
524  * entity. In some cases, clock frequencies are configured by host.
525  *
526  * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
527  * that the clock is currently at.
528  */
529 struct ti_sci_msg_req_get_clock_freq {
530 	struct ti_sci_msg_hdr hdr;
531 	u32 dev_id;
532 	u8 clk_id;
533 	u32 clk_id_32;
534 } __packed;
535 
536 /**
537  * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
538  * @hdr:	Generic Header
539  * @freq_hz:	Frequency that the clock is currently on, in Hz.
540  *
541  * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
542  */
543 struct ti_sci_msg_resp_get_clock_freq {
544 	struct ti_sci_msg_hdr hdr;
545 	u64 freq_hz;
546 } __packed;
547 
548 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID	0xff
549 
550 /**
551  * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
552  *					      range of resources.
553  * @hdr:		Generic Header
554  * @type:		Unique resource assignment type
555  * @subtype:		Resource assignment subtype within the resource type.
556  * @secondary_host:	Host processing entity to which the resources are
557  *			allocated. This is required only when the destination
558  *			host id id different from ti sci interface host id,
559  *			else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
560  *
561  * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
562  * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
563  */
564 struct ti_sci_msg_req_get_resource_range {
565 	struct ti_sci_msg_hdr hdr;
566 #define MSG_RM_RESOURCE_TYPE_MASK	GENMASK(9, 0)
567 #define MSG_RM_RESOURCE_SUBTYPE_MASK	GENMASK(5, 0)
568 	u16 type;
569 	u8 subtype;
570 	u8 secondary_host;
571 } __packed;
572 
573 /**
574  * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
575  * @hdr:		Generic Header
576  * @range_start:	Start index of the first resource range.
577  * @range_num:		Number of resources in the first range.
578  * @range_start_sec:	Start index of the second resource range.
579  * @range_num_sec:	Number of resources in the second range.
580  *
581  * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
582  */
583 struct ti_sci_msg_resp_get_resource_range {
584 	struct ti_sci_msg_hdr hdr;
585 	u16 range_start;
586 	u16 range_num;
587 	u16 range_start_sec;
588 	u16 range_num_sec;
589 } __packed;
590 
591 /**
592  * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
593  *					between the dev and the host.
594  * @hdr:		Generic Header
595  * @valid_params:	Bit fields defining the validity of interrupt source
596  *			parameters. If a bit is not set, then corresponding
597  *			field is not valid and will not be used for route set.
598  *			Bit field definitions:
599  *			0 - Valid bit for @dst_id
600  *			1 - Valid bit for @dst_host_irq
601  *			2 - Valid bit for @ia_id
602  *			3 - Valid bit for @vint
603  *			4 - Valid bit for @global_event
604  *			5 - Valid bit for @vint_status_bit_index
605  *			31 - Valid bit for @secondary_host
606  * @src_id:		IRQ source peripheral ID.
607  * @src_index:		IRQ source index within the peripheral
608  * @dst_id:		IRQ Destination ID. Based on the architecture it can be
609  *			IRQ controller or host processor ID.
610  * @dst_host_irq:	IRQ number of the destination host IRQ controller
611  * @ia_id:		Device ID of the interrupt aggregator in which the
612  *			vint resides.
613  * @vint:		Virtual interrupt number if the interrupt route
614  *			is through an interrupt aggregator.
615  * @global_event:	Global event that is to be mapped to interrupt
616  *			aggregator virtual interrupt status bit.
617  * @vint_status_bit:	Virtual interrupt status bit if the interrupt route
618  *			utilizes an interrupt aggregator status bit.
619  * @secondary_host:	Host ID of the IRQ destination computing entity. This is
620  *			required only when destination host id is different
621  *			from ti sci interface host id.
622  *
623  * Request type is TI_SCI_MSG_SET/RELEASE_IRQ.
624  * Response is generic ACK / NACK message.
625  */
626 struct ti_sci_msg_req_manage_irq {
627 	struct ti_sci_msg_hdr hdr;
628 #define MSG_FLAG_DST_ID_VALID			TI_SCI_MSG_FLAG(0)
629 #define MSG_FLAG_DST_HOST_IRQ_VALID		TI_SCI_MSG_FLAG(1)
630 #define MSG_FLAG_IA_ID_VALID			TI_SCI_MSG_FLAG(2)
631 #define MSG_FLAG_VINT_VALID			TI_SCI_MSG_FLAG(3)
632 #define MSG_FLAG_GLB_EVNT_VALID			TI_SCI_MSG_FLAG(4)
633 #define MSG_FLAG_VINT_STS_BIT_VALID		TI_SCI_MSG_FLAG(5)
634 #define MSG_FLAG_SHOST_VALID			TI_SCI_MSG_FLAG(31)
635 	u32 valid_params;
636 	u16 src_id;
637 	u16 src_index;
638 	u16 dst_id;
639 	u16 dst_host_irq;
640 	u16 ia_id;
641 	u16 vint;
642 	u16 global_event;
643 	u8 vint_status_bit;
644 	u8 secondary_host;
645 } __packed;
646 
647 /**
648  * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
649  *
650  * Configures the non-real-time registers of a Navigator Subsystem ring.
651  * @hdr:	Generic Header
652  * @valid_params: Bitfield defining validity of ring configuration parameters.
653  *	The ring configuration fields are not valid, and will not be used for
654  *	ring configuration, if their corresponding valid bit is zero.
655  *	Valid bit usage:
656  *	0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
657  *	1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
658  *	2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
659  *	3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
660  *	4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
661  *	5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
662  *	6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
663  *	7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
664  * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
665  * @index: ring index to be configured.
666  * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
667  *	RING_BA_LO register
668  * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
669  *	RING_BA_HI register.
670  * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
671  *	modes.
672  * @mode: Specifies the mode the ring is to be configured.
673  * @size: Specifies encoded ring element size. To calculate the encoded size use
674  *	the formula (log2(size_bytes) - 2), where size_bytes cannot be
675  *	greater than 256.
676  * @order_id: Specifies the ring's bus order ID.
677  * @virtid: Ring virt ID value
678  * @asel: Ring ASEL (address select) value to be set into the ASEL field of the
679  *	ring's RING_BA_HI register.
680  */
681 struct ti_sci_msg_rm_ring_cfg_req {
682 	struct ti_sci_msg_hdr hdr;
683 	u32 valid_params;
684 	u16 nav_id;
685 	u16 index;
686 	u32 addr_lo;
687 	u32 addr_hi;
688 	u32 count;
689 	u8 mode;
690 	u8 size;
691 	u8 order_id;
692 	u16 virtid;
693 	u8 asel;
694 } __packed;
695 
696 /**
697  * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
698  *				 thread
699  * @hdr:	Generic Header
700  * @nav_id:	SoC Navigator Subsystem device ID whose PSI-L config proxy is
701  *		used to pair the source and destination threads.
702  * @src_thread:	PSI-L source thread ID within the PSI-L System thread map.
703  *
704  * UDMAP transmit channels mapped to source threads will have their
705  * TCHAN_THRD_ID register programmed with the destination thread if the pairing
706  * is successful.
707 
708  * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
709  * PSI-L destination threads start at index 0x8000.  The request is NACK'd if
710  * the destination thread is not greater than or equal to 0x8000.
711  *
712  * UDMAP receive channels mapped to destination threads will have their
713  * RCHAN_THRD_ID register programmed with the source thread if the pairing
714  * is successful.
715  *
716  * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
717  * message.
718  */
719 struct ti_sci_msg_psil_pair {
720 	struct ti_sci_msg_hdr hdr;
721 	u32 nav_id;
722 	u32 src_thread;
723 	u32 dst_thread;
724 } __packed;
725 
726 /**
727  * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
728  *				   destination thread
729  * @hdr:	Generic Header
730  * @nav_id:	SoC Navigator Subsystem device ID whose PSI-L config proxy is
731  *		used to unpair the source and destination threads.
732  * @src_thread:	PSI-L source thread ID within the PSI-L System thread map.
733  *
734  * UDMAP transmit channels mapped to source threads will have their
735  * TCHAN_THRD_ID register cleared if the unpairing is successful.
736  *
737  * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
738  * PSI-L destination threads start at index 0x8000.  The request is NACK'd if
739  * the destination thread is not greater than or equal to 0x8000.
740  *
741  * UDMAP receive channels mapped to destination threads will have their
742  * RCHAN_THRD_ID register cleared if the unpairing is successful.
743  *
744  * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
745  * message.
746  */
747 struct ti_sci_msg_psil_unpair {
748 	struct ti_sci_msg_hdr hdr;
749 	u32 nav_id;
750 	u32 src_thread;
751 	u32 dst_thread;
752 } __packed;
753 
754 /**
755  * struct ti_sci_msg_udmap_rx_flow_cfg -  UDMAP receive flow configuration
756  *					  message
757  * @hdr: Generic Header
758  * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
759  *	allocated
760  * @flow_index: UDMAP receive flow index for non-optional configuration.
761  * @rx_ch_index: Specifies the index of the receive channel using the flow_index
762  * @rx_einfo_present: UDMAP receive flow extended packet info present.
763  * @rx_psinfo_present: UDMAP receive flow PS words present.
764  * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
765  *	values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.
766  * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
767  *	TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.
768  * @rx_sop_offset: UDMAP receive flow start of packet offset.
769  * @rx_dest_qnum: UDMAP receive flow destination queue number.
770  * @rx_ps_location: UDMAP receive flow PS words location.
771  *	0 - end of packet descriptor
772  *	1 - Beginning of the data buffer
773  * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant
774  * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant
775  * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant
776  * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant
777  * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector
778  * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector
779  * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector
780  * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector
781  * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
782  *	enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be
783  *	configured and sent.
784  * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
785  * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.
786  * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
787  * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.
788  *
789  * For detailed information on the settings, see the UDMAP section of the TRM.
790  */
791 struct ti_sci_msg_udmap_rx_flow_cfg {
792 	struct ti_sci_msg_hdr hdr;
793 	u32 nav_id;
794 	u32 flow_index;
795 	u32 rx_ch_index;
796 	u8 rx_einfo_present;
797 	u8 rx_psinfo_present;
798 	u8 rx_error_handling;
799 	u8 rx_desc_type;
800 	u16 rx_sop_offset;
801 	u16 rx_dest_qnum;
802 	u8 rx_ps_location;
803 	u8 rx_src_tag_hi;
804 	u8 rx_src_tag_lo;
805 	u8 rx_dest_tag_hi;
806 	u8 rx_dest_tag_lo;
807 	u8 rx_src_tag_hi_sel;
808 	u8 rx_src_tag_lo_sel;
809 	u8 rx_dest_tag_hi_sel;
810 	u8 rx_dest_tag_lo_sel;
811 	u8 rx_size_thresh_en;
812 	u16 rx_fdq0_sz0_qnum;
813 	u16 rx_fdq1_qnum;
814 	u16 rx_fdq2_qnum;
815 	u16 rx_fdq3_qnum;
816 } __packed;
817 
818 /**
819  * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
820  *						flow optional configuration
821  * @hdr: Generic Header
822  * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
823  *	allocated
824  * @flow_index: UDMAP receive flow index for optional configuration.
825  * @rx_ch_index: Specifies the index of the receive channel using the flow_index
826  * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
827  * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
828  * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
829  * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size
830  *	threshold 1.
831  * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size
832  *	threshold 2.
833  * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size
834  *	threshold 3.
835  *
836  * For detailed information on the settings, see the UDMAP section of the TRM.
837  */
838 struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
839 	struct ti_sci_msg_hdr hdr;
840 	u32 nav_id;
841 	u32 flow_index;
842 	u32 rx_ch_index;
843 	u16 rx_size_thresh0;
844 	u16 rx_size_thresh1;
845 	u16 rx_size_thresh2;
846 	u16 rx_fdq0_sz1_qnum;
847 	u16 rx_fdq0_sz2_qnum;
848 	u16 rx_fdq0_sz3_qnum;
849 } __packed;
850 
851 /**
852  * Configures a Navigator Subsystem UDMAP transmit channel
853  *
854  * Configures the non-real-time registers of a Navigator Subsystem UDMAP
855  * transmit channel.  The channel index must be assigned to the host defined
856  * in the TISCI header via the RM board configuration resource assignment
857  * range list.
858  *
859  * @hdr: Generic Header
860  *
861  * @valid_params: Bitfield defining validity of tx channel configuration
862  * parameters. The tx channel configuration fields are not valid, and will not
863  * be used for ch configuration, if their corresponding valid bit is zero.
864  * Valid bit usage:
865  *    0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
866  *    1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
867  *    2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
868  *    3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
869  *    4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
870  *    5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
871  *    6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
872  *    7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
873  *    8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
874  *    9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
875  *   10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
876  *   11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
877  *   12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
878  *   13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
879  *   14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
880  *   15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
881  *   16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
882  *
883  * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
884  *
885  * @index: UDMAP transmit channel index.
886  *
887  * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
888  * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
889  * register.
890  *
891  * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
892  * configuration to be programmed into the tx_filt_einfo field of the
893  * channel's TCHAN_TCFG register.
894  *
895  * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
896  * configuration to be programmed into the tx_filt_pswords field of the
897  * channel's TCHAN_TCFG register.
898  *
899  * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
900  * interpretation configuration to be programmed into the tx_atype field of
901  * the channel's TCHAN_TCFG register.
902  *
903  * @tx_chan_type: UDMAP transmit channel functional channel type and work
904  * passing mechanism configuration to be programmed into the tx_chan_type
905  * field of the channel's TCHAN_TCFG register.
906  *
907  * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
908  * configuration to be programmed into the tx_supr_tdpkt field of the channel's
909  * TCHAN_TCFG register.
910  *
911  * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
912  * fetch configuration to be programmed into the tx_fetch_size field of the
913  * channel's TCHAN_TCFG register.  The user must make sure to set the maximum
914  * word count that can pass through the channel for any allowed descriptor type.
915  *
916  * @tx_credit_count: UDMAP transmit channel transfer request credit count
917  * configuration to be programmed into the count field of the TCHAN_TCREDIT
918  * register.  Specifies how many credits for complete TRs are available.
919  *
920  * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
921  * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
922  * completion queue must be assigned to the host, or a subordinate of the host,
923  * requesting configuration of the transmit channel.
924  *
925  * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
926  * into the priority field of the channel's TCHAN_TPRI_CTRL register.
927  *
928  * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
929  * qos field of the channel's TCHAN_TPRI_CTRL register.
930  *
931  * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
932  * the orderid field of the channel's TCHAN_TPRI_CTRL register.
933  *
934  * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
935  * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
936  * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
937  * section of the TRM for restrictions regarding this parameter.
938  *
939  * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
940  * configuration to be programmed into the priority field of the channel's
941  * TCHAN_TST_SCHED register.
942  *
943  * @tx_burst_size: UDMAP transmit channel burst size configuration to be
944  * programmed into the tx_burst_size field of the TCHAN_TCFG register.
945  *
946  * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
947  * programmed into the tdtype field of the TCHAN_TCFG register:
948  * 0 - Return immediately
949  * 1 - Wait for completion message from remote peer
950  *
951  * @extended_ch_type: Valid for BCDMA.
952  * 0 - the channel is split tx channel (tchan)
953  * 1 - the channel is block copy channel (bchan)
954  */
955 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
956 	struct ti_sci_msg_hdr hdr;
957 	u32 valid_params;
958 	u16 nav_id;
959 	u16 index;
960 	u8 tx_pause_on_err;
961 	u8 tx_filt_einfo;
962 	u8 tx_filt_pswords;
963 	u8 tx_atype;
964 	u8 tx_chan_type;
965 	u8 tx_supr_tdpkt;
966 	u16 tx_fetch_size;
967 	u8 tx_credit_count;
968 	u16 txcq_qnum;
969 	u8 tx_priority;
970 	u8 tx_qos;
971 	u8 tx_orderid;
972 	u16 fdepth;
973 	u8 tx_sched_priority;
974 	u8 tx_burst_size;
975 	u8 tx_tdtype;
976 	u8 extended_ch_type;
977 } __packed;
978 
979 /**
980  * Configures a Navigator Subsystem UDMAP receive channel
981  *
982  * Configures the non-real-time registers of a Navigator Subsystem UDMAP
983  * receive channel.  The channel index must be assigned to the host defined
984  * in the TISCI header via the RM board configuration resource assignment
985  * range list.
986  *
987  * @hdr: Generic Header
988  *
989  * @valid_params: Bitfield defining validity of rx channel configuration
990  * parameters.
991  * The rx channel configuration fields are not valid, and will not be used for
992  * ch configuration, if their corresponding valid bit is zero.
993  * Valid bit usage:
994  *    0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
995  *    1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
996  *    2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
997  *    3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
998  *    4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
999  *    5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1000  *    6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1001  *    7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1002  *    8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1003  *    9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1004  *   10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1005  *   11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1006  *   12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1007  *   14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
1008  *
1009  * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
1010  *
1011  * @index: UDMAP receive channel index.
1012  *
1013  * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1014  * fetch configuration to be programmed into the rx_fetch_size field of the
1015  * channel's RCHAN_RCFG register.
1016  *
1017  * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1018  * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
1019  * The specified completion queue must be assigned to the host, or a subordinate
1020  * of the host, requesting configuration of the receive channel.
1021  *
1022  * @rx_priority: UDMAP receive channel receive priority value to be programmed
1023  * into the priority field of the channel's RCHAN_RPRI_CTRL register.
1024  *
1025  * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
1026  * qos field of the channel's RCHAN_RPRI_CTRL register.
1027  *
1028  * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
1029  * the orderid field of the channel's RCHAN_RPRI_CTRL register.
1030  *
1031  * @rx_sched_priority: UDMAP receive channel rx scheduling priority
1032  * configuration to be programmed into the priority field of the channel's
1033  * RCHAN_RST_SCHED register.
1034  *
1035  * @flowid_start: UDMAP receive channel additional flows starting index
1036  * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1037  * register. Specifies the starting index for flow IDs the receive channel is to
1038  * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
1039  * set as valid and configured together. The starting flow ID set by
1040  * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
1041  * of flows beyond the default flows statically mapped to receive channels.
1042  * The additional flows must be assigned to the host, or a subordinate of the
1043  * host, requesting configuration of the receive channel.
1044  *
1045  * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1046  * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
1047  * This field specifies how many flow IDs are in the additional contiguous range
1048  * of legal flow IDs for the channel.  @ref flowid_start and flowid_cnt must be
1049  * set as valid and configured together. Disabling the valid_params field bit
1050  * for flowid_cnt indicates no flow IDs other than the default are to be
1051  * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
1052  * cannot be greater than the number of receive flows in the receive channel's
1053  * Navigator Subsystem.  The additional flows must be assigned to the host, or a
1054  * subordinate of the host, requesting configuration of the receive channel.
1055  *
1056  * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1057  * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
1058  * register.
1059  *
1060  * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
1061  * interpretation configuration to be programmed into the rx_atype field of the
1062  * channel's RCHAN_RCFG register.
1063  *
1064  * @rx_chan_type: UDMAP receive channel functional channel type and work passing
1065  * mechanism configuration to be programmed into the rx_chan_type field of the
1066  * channel's RCHAN_RCFG register.
1067  *
1068  * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1069  * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
1070  *
1071  * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1072  * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
1073  *
1074  * @rx_burst_size: UDMAP receive channel burst size configuration to be
1075  * programmed into the rx_burst_size field of the RCHAN_RCFG register.
1076  */
1077 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
1078 	struct ti_sci_msg_hdr hdr;
1079 	u32 valid_params;
1080 	u16 nav_id;
1081 	u16 index;
1082 	u16 rx_fetch_size;
1083 	u16 rxcq_qnum;
1084 	u8 rx_priority;
1085 	u8 rx_qos;
1086 	u8 rx_orderid;
1087 	u8 rx_sched_priority;
1088 	u16 flowid_start;
1089 	u16 flowid_cnt;
1090 	u8 rx_pause_on_err;
1091 	u8 rx_atype;
1092 	u8 rx_chan_type;
1093 	u8 rx_ignore_short;
1094 	u8 rx_ignore_long;
1095 	u8 rx_burst_size;
1096 } __packed;
1097 
1098 /**
1099  * Configures a Navigator Subsystem UDMAP receive flow
1100  *
1101  * Configures a Navigator Subsystem UDMAP receive flow's registers.
1102  * Configuration does not include the flow registers which handle size-based
1103  * free descriptor queue routing.
1104  *
1105  * The flow index must be assigned to the host defined in the TISCI header via
1106  * the RM board configuration resource assignment range list.
1107  *
1108  * @hdr: Standard TISCI header
1109  *
1110  * @valid_params
1111  * Bitfield defining validity of rx flow configuration parameters.  The
1112  * rx flow configuration fields are not valid, and will not be used for flow
1113  * configuration, if their corresponding valid bit is zero.  Valid bit usage:
1114  *     0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1115  *     1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1116  *     2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1117  *     3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1118  *     4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1119  *     5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1120  *     6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1121  *     7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1122  *     8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1123  *     9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1124  *    10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1125  *    11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1126  *    12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1127  *    13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1128  *    14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1129  *    15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1130  *    16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1131  *    17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1132  *    18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1133  *
1134  * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
1135  * allocated
1136  *
1137  * @flow_index: UDMAP receive flow index for non-optional configuration.
1138  *
1139  * @rx_einfo_present:
1140  * UDMAP receive flow extended packet info present configuration to be
1141  * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
1142  *
1143  * @rx_psinfo_present:
1144  * UDMAP receive flow PS words present configuration to be programmed into the
1145  * rx_psinfo_present field of the flow's RFLOW_RFA register.
1146  *
1147  * @rx_error_handling:
1148  * UDMAP receive flow error handling configuration to be programmed into the
1149  * rx_error_handling field of the flow's RFLOW_RFA register.
1150  *
1151  * @rx_desc_type:
1152  * UDMAP receive flow descriptor type configuration to be programmed into the
1153  * rx_desc_type field field of the flow's RFLOW_RFA register.
1154  *
1155  * @rx_sop_offset:
1156  * UDMAP receive flow start of packet offset configuration to be programmed
1157  * into the rx_sop_offset field of the RFLOW_RFA register.  See the UDMAP
1158  * section of the TRM for more information on this setting.  Valid values for
1159  * this field are 0-255 bytes.
1160  *
1161  * @rx_dest_qnum:
1162  * UDMAP receive flow destination queue configuration to be programmed into the
1163  * rx_dest_qnum field of the flow's RFLOW_RFA register.  The specified
1164  * destination queue must be valid within the Navigator Subsystem and must be
1165  * owned by the host, or a subordinate of the host, requesting allocation and
1166  * configuration of the receive flow.
1167  *
1168  * @rx_src_tag_hi:
1169  * UDMAP receive flow source tag high byte constant configuration to be
1170  * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
1171  * See the UDMAP section of the TRM for more information on this setting.
1172  *
1173  * @rx_src_tag_lo:
1174  * UDMAP receive flow source tag low byte constant configuration to be
1175  * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
1176  * See the UDMAP section of the TRM for more information on this setting.
1177  *
1178  * @rx_dest_tag_hi:
1179  * UDMAP receive flow destination tag high byte constant configuration to be
1180  * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
1181  * See the UDMAP section of the TRM for more information on this setting.
1182  *
1183  * @rx_dest_tag_lo:
1184  * UDMAP receive flow destination tag low byte constant configuration to be
1185  * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
1186  * See the UDMAP section of the TRM for more information on this setting.
1187  *
1188  * @rx_src_tag_hi_sel:
1189  * UDMAP receive flow source tag high byte selector configuration to be
1190  * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register.  See
1191  * the UDMAP section of the TRM for more information on this setting.
1192  *
1193  * @rx_src_tag_lo_sel:
1194  * UDMAP receive flow source tag low byte selector configuration to be
1195  * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register.  See
1196  * the UDMAP section of the TRM for more information on this setting.
1197  *
1198  * @rx_dest_tag_hi_sel:
1199  * UDMAP receive flow destination tag high byte selector configuration to be
1200  * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register.  See
1201  * the UDMAP section of the TRM for more information on this setting.
1202  *
1203  * @rx_dest_tag_lo_sel:
1204  * UDMAP receive flow destination tag low byte selector configuration to be
1205  * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register.  See
1206  * the UDMAP section of the TRM for more information on this setting.
1207  *
1208  * @rx_fdq0_sz0_qnum:
1209  * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1210  * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register.  See the
1211  * UDMAP section of the TRM for more information on this setting. The specified
1212  * free queue must be valid within the Navigator Subsystem and must be owned
1213  * by the host, or a subordinate of the host, requesting allocation and
1214  * configuration of the receive flow.
1215  *
1216  * @rx_fdq1_qnum:
1217  * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1218  * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register.  See the
1219  * UDMAP section of the TRM for more information on this setting.  The specified
1220  * free queue must be valid within the Navigator Subsystem and must be owned
1221  * by the host, or a subordinate of the host, requesting allocation and
1222  * configuration of the receive flow.
1223  *
1224  * @rx_fdq2_qnum:
1225  * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1226  * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register.  See the
1227  * UDMAP section of the TRM for more information on this setting.  The specified
1228  * free queue must be valid within the Navigator Subsystem and must be owned
1229  * by the host, or a subordinate of the host, requesting allocation and
1230  * configuration of the receive flow.
1231  *
1232  * @rx_fdq3_qnum:
1233  * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1234  * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register.  See the
1235  * UDMAP section of the TRM for more information on this setting.  The specified
1236  * free queue must be valid within the Navigator Subsystem and must be owned
1237  * by the host, or a subordinate of the host, requesting allocation and
1238  * configuration of the receive flow.
1239  *
1240  * @rx_ps_location:
1241  * UDMAP receive flow PS words location configuration to be programmed into the
1242  * rx_ps_location field of the flow's RFLOW_RFA register.
1243  */
1244 struct ti_sci_msg_rm_udmap_flow_cfg_req {
1245 	struct ti_sci_msg_hdr hdr;
1246 	u32 valid_params;
1247 	u16 nav_id;
1248 	u16 flow_index;
1249 	u8 rx_einfo_present;
1250 	u8 rx_psinfo_present;
1251 	u8 rx_error_handling;
1252 	u8 rx_desc_type;
1253 	u16 rx_sop_offset;
1254 	u16 rx_dest_qnum;
1255 	u8 rx_src_tag_hi;
1256 	u8 rx_src_tag_lo;
1257 	u8 rx_dest_tag_hi;
1258 	u8 rx_dest_tag_lo;
1259 	u8 rx_src_tag_hi_sel;
1260 	u8 rx_src_tag_lo_sel;
1261 	u8 rx_dest_tag_hi_sel;
1262 	u8 rx_dest_tag_lo_sel;
1263 	u16 rx_fdq0_sz0_qnum;
1264 	u16 rx_fdq1_qnum;
1265 	u16 rx_fdq2_qnum;
1266 	u16 rx_fdq3_qnum;
1267 	u8 rx_ps_location;
1268 } __packed;
1269 
1270 /**
1271  * struct ti_sci_msg_req_proc_request - Request a processor
1272  * @hdr:		Generic Header
1273  * @processor_id:	ID of processor being requested
1274  *
1275  * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
1276  * message.
1277  */
1278 struct ti_sci_msg_req_proc_request {
1279 	struct ti_sci_msg_hdr hdr;
1280 	u8 processor_id;
1281 } __packed;
1282 
1283 /**
1284  * struct ti_sci_msg_req_proc_release - Release a processor
1285  * @hdr:		Generic Header
1286  * @processor_id:	ID of processor being released
1287  *
1288  * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
1289  * message.
1290  */
1291 struct ti_sci_msg_req_proc_release {
1292 	struct ti_sci_msg_hdr hdr;
1293 	u8 processor_id;
1294 } __packed;
1295 
1296 /**
1297  * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
1298  * @hdr:		Generic Header
1299  * @processor_id:	ID of processor being handed over
1300  * @host_id:		Host ID the control needs to be transferred to
1301  *
1302  * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1303  * message.
1304  */
1305 struct ti_sci_msg_req_proc_handover {
1306 	struct ti_sci_msg_hdr hdr;
1307 	u8 processor_id;
1308 	u8 host_id;
1309 } __packed;
1310 
1311 /* Boot Vector masks */
1312 #define TI_SCI_ADDR_LOW_MASK			GENMASK_ULL(31, 0)
1313 #define TI_SCI_ADDR_HIGH_MASK			GENMASK_ULL(63, 32)
1314 #define TI_SCI_ADDR_HIGH_SHIFT			32
1315 
1316 /**
1317  * struct ti_sci_msg_req_set_config - Set Processor boot configuration
1318  * @hdr:		Generic Header
1319  * @processor_id:	ID of processor being configured
1320  * @bootvector_low:	Lower 32 bit address (Little Endian) of boot vector
1321  * @bootvector_high:	Higher 32 bit address (Little Endian) of boot vector
1322  * @config_flags_set:	Optional Processor specific Config Flags to set.
1323  *			Setting a bit here implies the corresponding mode
1324  *			will be set
1325  * @config_flags_clear:	Optional Processor specific Config Flags to clear.
1326  *			Setting a bit here implies the corresponding mode
1327  *			will be cleared
1328  *
1329  * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1330  * message.
1331  */
1332 struct ti_sci_msg_req_set_config {
1333 	struct ti_sci_msg_hdr hdr;
1334 	u8 processor_id;
1335 	u32 bootvector_low;
1336 	u32 bootvector_high;
1337 	u32 config_flags_set;
1338 	u32 config_flags_clear;
1339 } __packed;
1340 
1341 /**
1342  * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
1343  * @hdr:		Generic Header
1344  * @processor_id:	ID of processor being configured
1345  * @control_flags_set:	Optional Processor specific Control Flags to set.
1346  *			Setting a bit here implies the corresponding mode
1347  *			will be set
1348  * @control_flags_clear:Optional Processor specific Control Flags to clear.
1349  *			Setting a bit here implies the corresponding mode
1350  *			will be cleared
1351  *
1352  * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK
1353  * message.
1354  */
1355 struct ti_sci_msg_req_set_ctrl {
1356 	struct ti_sci_msg_hdr hdr;
1357 	u8 processor_id;
1358 	u32 control_flags_set;
1359 	u32 control_flags_clear;
1360 } __packed;
1361 
1362 /**
1363  * struct ti_sci_msg_req_get_status - Processor boot status request
1364  * @hdr:		Generic Header
1365  * @processor_id:	ID of processor whose status is being requested
1366  *
1367  * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate
1368  * message, or NACK in case of inability to satisfy request.
1369  */
1370 struct ti_sci_msg_req_get_status {
1371 	struct ti_sci_msg_hdr hdr;
1372 	u8 processor_id;
1373 } __packed;
1374 
1375 /**
1376  * struct ti_sci_msg_resp_get_status - Processor boot status response
1377  * @hdr:		Generic Header
1378  * @processor_id:	ID of processor whose status is returned
1379  * @bootvector_low:	Lower 32 bit address (Little Endian) of boot vector
1380  * @bootvector_high:	Higher 32 bit address (Little Endian) of boot vector
1381  * @config_flags:	Optional Processor specific Config Flags set currently
1382  * @control_flags:	Optional Processor specific Control Flags set currently
1383  * @status_flags:	Optional Processor specific Status Flags set currently
1384  *
1385  * Response structure to a TI_SCI_MSG_GET_STATUS request.
1386  */
1387 struct ti_sci_msg_resp_get_status {
1388 	struct ti_sci_msg_hdr hdr;
1389 	u8 processor_id;
1390 	u32 bootvector_low;
1391 	u32 bootvector_high;
1392 	u32 config_flags;
1393 	u32 control_flags;
1394 	u32 status_flags;
1395 } __packed;
1396 
1397 #endif /* __TI_SCI_H */
1398