xref: /openbmc/u-boot/arch/arm/mach-versatile/timer.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2003
4  * Texas Instruments <www.ti.com>
5  *
6  * (C) Copyright 2002
7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8  * Marius Groeger <mgroeger@sysgo.de>
9  *
10  * (C) Copyright 2002
11  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12  * Alex Zuepke <azu@sysgo.de>
13  *
14  * (C) Copyright 2002-2004
15  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
16  *
17  * (C) Copyright 2004
18  * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
19  */
20 
21 #include <common.h>
22 
23 #define TIMER_ENABLE	(1 << 7)
24 #define TIMER_MODE_MSK	(1 << 6)
25 #define TIMER_MODE_FR	(0 << 6)
26 #define TIMER_MODE_PD	(1 << 6)
27 
28 #define TIMER_INT_EN	(1 << 5)
29 #define TIMER_PRS_MSK	(3 << 2)
30 #define TIMER_PRS_8S	(1 << 3)
31 #define TIMER_SIZE_MSK	(1 << 2)
32 #define TIMER_ONE_SHT	(1 << 0)
33 
timer_init(void)34 int timer_init (void)
35 {
36 	ulong	tmr_ctrl_val;
37 
38 	/* 1st disable the Timer */
39 	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
40 	tmr_ctrl_val &= ~TIMER_ENABLE;
41 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
42 
43 	/*
44 	 * The Timer Control Register has one Undefined/Shouldn't Use Bit
45 	 * So we should do read/modify/write Operation
46 	 */
47 
48 	/*
49 	 * Timer Mode : Free Running
50 	 * Interrupt : Disabled
51 	 * Prescale : 8 Stage, Clk/256
52 	 * Tmr Siz : 16 Bit Counter
53 	 * Tmr in Wrapping Mode
54 	 */
55 	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
56 	tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
57 	tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
58 
59 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
60 
61 	return 0;
62 }
63 
64