1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #include <linux/jump_label.h> 3 #include <asm/unwind_hints.h> 4 #include <asm/cpufeatures.h> 5 #include <asm/page_types.h> 6 #include <asm/percpu.h> 7 #include <asm/asm-offsets.h> 8 #include <asm/processor-flags.h> 9 #include <asm/ptrace-abi.h> 10 #include <asm/msr.h> 11 #include <asm/nospec-branch.h> 12 13 /* 14 15 x86 function call convention, 64-bit: 16 ------------------------------------- 17 arguments | callee-saved | extra caller-saved | return 18 [callee-clobbered] | | [callee-clobbered] | 19 --------------------------------------------------------------------------- 20 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**] 21 22 ( rsp is obviously invariant across normal function calls. (gcc can 'merge' 23 functions when it sees tail-call optimization possibilities) rflags is 24 clobbered. Leftover arguments are passed over the stack frame.) 25 26 [*] In the frame-pointers case rbp is fixed to the stack frame. 27 28 [**] for struct return values wider than 64 bits the return convention is a 29 bit more complex: up to 128 bits width we return small structures 30 straight in rax, rdx. For structures larger than that (3 words or 31 larger) the caller puts a pointer to an on-stack return struct 32 [allocated in the caller's stack frame] into the first argument - i.e. 33 into rdi. All other arguments shift up by one in this case. 34 Fortunately this case is rare in the kernel. 35 36 For 32-bit we have the following conventions - kernel is built with 37 -mregparm=3 and -freg-struct-return: 38 39 x86 function calling convention, 32-bit: 40 ---------------------------------------- 41 arguments | callee-saved | extra caller-saved | return 42 [callee-clobbered] | | [callee-clobbered] | 43 ------------------------------------------------------------------------- 44 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**] 45 46 ( here too esp is obviously invariant across normal function calls. eflags 47 is clobbered. Leftover arguments are passed over the stack frame. ) 48 49 [*] In the frame-pointers case ebp is fixed to the stack frame. 50 51 [**] We build with -freg-struct-return, which on 32-bit means similar 52 semantics as on 64-bit: edx can be used for a second return value 53 (i.e. covering integer and structure sizes up to 64 bits) - after that 54 it gets more complex and more expensive: 3-word or larger struct returns 55 get done in the caller's frame and the pointer to the return struct goes 56 into regparm0, i.e. eax - the other arguments shift up and the 57 function's register parameters degenerate to regparm=2 in essence. 58 59 */ 60 61 #ifdef CONFIG_X86_64 62 63 /* 64 * 64-bit system call stack frame layout defines and helpers, 65 * for assembly code: 66 */ 67 68 .macro PUSH_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0 69 .if \save_ret 70 pushq %rsi /* pt_regs->si */ 71 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */ 72 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */ 73 /* We just clobbered the return address - use the IRET frame for unwinding: */ 74 UNWIND_HINT_IRET_REGS offset=3*8 75 .else 76 pushq %rdi /* pt_regs->di */ 77 pushq %rsi /* pt_regs->si */ 78 .endif 79 pushq \rdx /* pt_regs->dx */ 80 pushq \rcx /* pt_regs->cx */ 81 pushq \rax /* pt_regs->ax */ 82 pushq %r8 /* pt_regs->r8 */ 83 pushq %r9 /* pt_regs->r9 */ 84 pushq %r10 /* pt_regs->r10 */ 85 pushq %r11 /* pt_regs->r11 */ 86 pushq %rbx /* pt_regs->rbx */ 87 pushq %rbp /* pt_regs->rbp */ 88 pushq %r12 /* pt_regs->r12 */ 89 pushq %r13 /* pt_regs->r13 */ 90 pushq %r14 /* pt_regs->r14 */ 91 pushq %r15 /* pt_regs->r15 */ 92 UNWIND_HINT_REGS 93 94 .if \save_ret 95 pushq %rsi /* return address on top of stack */ 96 .endif 97 .endm 98 99 .macro CLEAR_REGS 100 /* 101 * Sanitize registers of values that a speculation attack might 102 * otherwise want to exploit. The lower registers are likely clobbered 103 * well before they could be put to use in a speculative execution 104 * gadget. 105 */ 106 xorl %esi, %esi /* nospec si */ 107 xorl %edx, %edx /* nospec dx */ 108 xorl %ecx, %ecx /* nospec cx */ 109 xorl %r8d, %r8d /* nospec r8 */ 110 xorl %r9d, %r9d /* nospec r9 */ 111 xorl %r10d, %r10d /* nospec r10 */ 112 xorl %r11d, %r11d /* nospec r11 */ 113 xorl %ebx, %ebx /* nospec rbx */ 114 xorl %ebp, %ebp /* nospec rbp */ 115 xorl %r12d, %r12d /* nospec r12 */ 116 xorl %r13d, %r13d /* nospec r13 */ 117 xorl %r14d, %r14d /* nospec r14 */ 118 xorl %r15d, %r15d /* nospec r15 */ 119 120 .endm 121 122 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0 123 PUSH_REGS rdx=\rdx, rcx=\rcx, rax=\rax, save_ret=\save_ret 124 CLEAR_REGS 125 .endm 126 127 .macro POP_REGS pop_rdi=1 128 popq %r15 129 popq %r14 130 popq %r13 131 popq %r12 132 popq %rbp 133 popq %rbx 134 popq %r11 135 popq %r10 136 popq %r9 137 popq %r8 138 popq %rax 139 popq %rcx 140 popq %rdx 141 popq %rsi 142 .if \pop_rdi 143 popq %rdi 144 .endif 145 .endm 146 147 #ifdef CONFIG_PAGE_TABLE_ISOLATION 148 149 /* 150 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two 151 * halves: 152 */ 153 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT 154 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT) 155 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT 156 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT) 157 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK) 158 159 .macro SET_NOFLUSH_BIT reg:req 160 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg 161 .endm 162 163 .macro ADJUST_KERNEL_CR3 reg:req 164 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID 165 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */ 166 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg 167 .endm 168 169 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 170 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 171 mov %cr3, \scratch_reg 172 ADJUST_KERNEL_CR3 \scratch_reg 173 mov \scratch_reg, %cr3 174 .Lend_\@: 175 .endm 176 177 #define THIS_CPU_user_pcid_flush_mask \ 178 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask 179 180 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 181 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 182 mov %cr3, \scratch_reg 183 184 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 185 186 /* 187 * Test if the ASID needs a flush. 188 */ 189 movq \scratch_reg, \scratch_reg2 190 andq $(0x7FF), \scratch_reg /* mask ASID */ 191 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 192 jnc .Lnoflush_\@ 193 194 /* Flush needed, clear the bit */ 195 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 196 movq \scratch_reg2, \scratch_reg 197 jmp .Lwrcr3_pcid_\@ 198 199 .Lnoflush_\@: 200 movq \scratch_reg2, \scratch_reg 201 SET_NOFLUSH_BIT \scratch_reg 202 203 .Lwrcr3_pcid_\@: 204 /* Flip the ASID to the user version */ 205 orq $(PTI_USER_PCID_MASK), \scratch_reg 206 207 .Lwrcr3_\@: 208 /* Flip the PGD to the user version */ 209 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg 210 mov \scratch_reg, %cr3 211 .Lend_\@: 212 .endm 213 214 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 215 pushq %rax 216 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax 217 popq %rax 218 .endm 219 220 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 221 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI 222 movq %cr3, \scratch_reg 223 movq \scratch_reg, \save_reg 224 /* 225 * Test the user pagetable bit. If set, then the user page tables 226 * are active. If clear CR3 already has the kernel page table 227 * active. 228 */ 229 bt $PTI_USER_PGTABLE_BIT, \scratch_reg 230 jnc .Ldone_\@ 231 232 ADJUST_KERNEL_CR3 \scratch_reg 233 movq \scratch_reg, %cr3 234 235 .Ldone_\@: 236 .endm 237 238 .macro RESTORE_CR3 scratch_reg:req save_reg:req 239 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 240 241 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 242 243 /* 244 * KERNEL pages can always resume with NOFLUSH as we do 245 * explicit flushes. 246 */ 247 bt $PTI_USER_PGTABLE_BIT, \save_reg 248 jnc .Lnoflush_\@ 249 250 /* 251 * Check if there's a pending flush for the user ASID we're 252 * about to set. 253 */ 254 movq \save_reg, \scratch_reg 255 andq $(0x7FF), \scratch_reg 256 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 257 jnc .Lnoflush_\@ 258 259 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 260 jmp .Lwrcr3_\@ 261 262 .Lnoflush_\@: 263 SET_NOFLUSH_BIT \save_reg 264 265 .Lwrcr3_\@: 266 /* 267 * The CR3 write could be avoided when not changing its value, 268 * but would require a CR3 read *and* a scratch register. 269 */ 270 movq \save_reg, %cr3 271 .Lend_\@: 272 .endm 273 274 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */ 275 276 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 277 .endm 278 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 279 .endm 280 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 281 .endm 282 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 283 .endm 284 .macro RESTORE_CR3 scratch_reg:req save_reg:req 285 .endm 286 287 #endif 288 289 /* 290 * IBRS kernel mitigation for Spectre_v2. 291 * 292 * Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers 293 * the regs it uses (AX, CX, DX). Must be called before the first RET 294 * instruction (NOTE! UNTRAIN_RET includes a RET instruction) 295 * 296 * The optional argument is used to save/restore the current value, 297 * which is used on the paranoid paths. 298 * 299 * Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set. 300 */ 301 .macro IBRS_ENTER save_reg 302 #ifdef CONFIG_CPU_IBRS_ENTRY 303 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS 304 movl $MSR_IA32_SPEC_CTRL, %ecx 305 306 .ifnb \save_reg 307 rdmsr 308 shl $32, %rdx 309 or %rdx, %rax 310 mov %rax, \save_reg 311 test $SPEC_CTRL_IBRS, %eax 312 jz .Ldo_wrmsr_\@ 313 lfence 314 jmp .Lend_\@ 315 .Ldo_wrmsr_\@: 316 .endif 317 318 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx 319 movl %edx, %eax 320 shr $32, %rdx 321 wrmsr 322 .Lend_\@: 323 #endif 324 .endm 325 326 /* 327 * Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX) 328 * regs. Must be called after the last RET. 329 */ 330 .macro IBRS_EXIT save_reg 331 #ifdef CONFIG_CPU_IBRS_ENTRY 332 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS 333 movl $MSR_IA32_SPEC_CTRL, %ecx 334 335 .ifnb \save_reg 336 mov \save_reg, %rdx 337 .else 338 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx 339 andl $(~SPEC_CTRL_IBRS), %edx 340 .endif 341 342 movl %edx, %eax 343 shr $32, %rdx 344 wrmsr 345 .Lend_\@: 346 #endif 347 .endm 348 349 /* 350 * Mitigate Spectre v1 for conditional swapgs code paths. 351 * 352 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to 353 * prevent a speculative swapgs when coming from kernel space. 354 * 355 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path, 356 * to prevent the swapgs from getting speculatively skipped when coming from 357 * user space. 358 */ 359 .macro FENCE_SWAPGS_USER_ENTRY 360 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER 361 .endm 362 .macro FENCE_SWAPGS_KERNEL_ENTRY 363 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL 364 .endm 365 366 .macro STACKLEAK_ERASE_NOCLOBBER 367 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 368 PUSH_AND_CLEAR_REGS 369 call stackleak_erase 370 POP_REGS 371 #endif 372 .endm 373 374 .macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req 375 rdgsbase \save_reg 376 GET_PERCPU_BASE \scratch_reg 377 wrgsbase \scratch_reg 378 .endm 379 380 #else /* CONFIG_X86_64 */ 381 # undef UNWIND_HINT_IRET_REGS 382 # define UNWIND_HINT_IRET_REGS 383 #endif /* !CONFIG_X86_64 */ 384 385 .macro STACKLEAK_ERASE 386 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 387 call stackleak_erase 388 #endif 389 .endm 390 391 #ifdef CONFIG_SMP 392 393 /* 394 * CPU/node NR is loaded from the limit (size) field of a special segment 395 * descriptor entry in GDT. 396 */ 397 .macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req 398 movq $__CPUNODE_SEG, \reg 399 lsl \reg, \reg 400 .endm 401 402 /* 403 * Fetch the per-CPU GSBASE value for this processor and put it in @reg. 404 * We normally use %gs for accessing per-CPU data, but we are setting up 405 * %gs here and obviously can not use %gs itself to access per-CPU data. 406 * 407 * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and 408 * may not restore the host's value until the CPU returns to userspace. 409 * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives 410 * while running KVM's run loop. 411 */ 412 .macro GET_PERCPU_BASE reg:req 413 LOAD_CPU_AND_NODE_SEG_LIMIT \reg 414 andq $VDSO_CPUNODE_MASK, \reg 415 movq __per_cpu_offset(, \reg, 8), \reg 416 .endm 417 418 #else 419 420 .macro GET_PERCPU_BASE reg:req 421 movq pcpu_unit_offsets(%rip), \reg 422 .endm 423 424 #endif /* CONFIG_SMP */ 425