1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2022 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/hte.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/seq_file.h>
17
18 #include <dt-bindings/gpio/tegra186-gpio.h>
19 #include <dt-bindings/gpio/tegra194-gpio.h>
20 #include <dt-bindings/gpio/tegra234-gpio.h>
21 #include <dt-bindings/gpio/tegra241-gpio.h>
22
23 /* security registers */
24 #define TEGRA186_GPIO_CTL_SCR 0x0c
25 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
26 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
27
28 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
29
30 #define TEGRA186_GPIO_VM 0x00
31 #define TEGRA186_GPIO_VM_RW_MASK 0x03
32 #define TEGRA186_GPIO_SCR 0x04
33 #define TEGRA186_GPIO_SCR_PIN_SIZE 0x08
34 #define TEGRA186_GPIO_SCR_PORT_SIZE 0x40
35 #define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)
36 #define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
37 #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
38 #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
39
40 /* control registers */
41 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
42 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
43 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
44 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
45 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
46 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
47 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
48 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
49 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
50 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
51 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
52 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
53
54 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
55 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
56
57 #define TEGRA186_GPIO_INPUT 0x08
58 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
59
60 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
61 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
62
63 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
64 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
65
66 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
67
68 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
69
70 struct tegra_gpio_port {
71 const char *name;
72 unsigned int bank;
73 unsigned int port;
74 unsigned int pins;
75 };
76
77 struct tegra186_pin_range {
78 unsigned int offset;
79 const char *group;
80 };
81
82 struct tegra_gpio_soc {
83 const struct tegra_gpio_port *ports;
84 unsigned int num_ports;
85 const char *name;
86 unsigned int instance;
87
88 unsigned int num_irqs_per_bank;
89
90 const struct tegra186_pin_range *pin_ranges;
91 unsigned int num_pin_ranges;
92 const char *pinmux;
93 bool has_gte;
94 bool has_vm_support;
95 };
96
97 struct tegra_gpio {
98 struct gpio_chip gpio;
99 unsigned int num_irq;
100 unsigned int *irq;
101
102 const struct tegra_gpio_soc *soc;
103 unsigned int num_irqs_per_bank;
104 unsigned int num_banks;
105
106 void __iomem *secure;
107 void __iomem *base;
108 };
109
110 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)111 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
112 {
113 unsigned int start = 0, i;
114
115 for (i = 0; i < gpio->soc->num_ports; i++) {
116 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
117
118 if (*pin >= start && *pin < start + port->pins) {
119 *pin -= start;
120 return port;
121 }
122
123 start += port->pins;
124 }
125
126 return NULL;
127 }
128
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)129 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
130 unsigned int pin)
131 {
132 const struct tegra_gpio_port *port;
133 unsigned int offset;
134
135 port = tegra186_gpio_get_port(gpio, &pin);
136 if (!port)
137 return NULL;
138
139 offset = port->bank * 0x1000 + port->port * 0x200;
140
141 return gpio->base + offset + pin * 0x20;
142 }
143
tegra186_gpio_get_secure_base(struct tegra_gpio * gpio,unsigned int pin)144 static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,
145 unsigned int pin)
146 {
147 const struct tegra_gpio_port *port;
148 unsigned int offset;
149
150 port = tegra186_gpio_get_port(gpio, &pin);
151 if (!port)
152 return NULL;
153
154 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
155
156 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;
157 }
158
tegra186_gpio_is_accessible(struct tegra_gpio * gpio,unsigned int pin)159 static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)
160 {
161 void __iomem *secure;
162 u32 value;
163
164 secure = tegra186_gpio_get_secure_base(gpio, pin);
165
166 if (gpio->soc->has_vm_support) {
167 value = readl(secure + TEGRA186_GPIO_VM);
168 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)
169 return false;
170 }
171
172 value = __raw_readl(secure + TEGRA186_GPIO_SCR);
173
174 /*
175 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
176 * registers for given GPIO pin.
177 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
178 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
179 * GPIO pin.
180 */
181
182 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
183 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
184 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
185 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
186 return true;
187
188 return false;
189 }
190
tegra186_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)191 static int tegra186_init_valid_mask(struct gpio_chip *chip,
192 unsigned long *valid_mask, unsigned int ngpios)
193 {
194 struct tegra_gpio *gpio = gpiochip_get_data(chip);
195 unsigned int j;
196
197 for (j = 0; j < ngpios; j++) {
198 if (!tegra186_gpio_is_accessible(gpio, j))
199 clear_bit(j, valid_mask);
200 }
201 return 0;
202 }
203
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)204 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
205 unsigned int offset)
206 {
207 struct tegra_gpio *gpio = gpiochip_get_data(chip);
208 void __iomem *base;
209 u32 value;
210
211 base = tegra186_gpio_get_base(gpio, offset);
212 if (WARN_ON(base == NULL))
213 return -ENODEV;
214
215 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
216 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
217 return GPIO_LINE_DIRECTION_OUT;
218
219 return GPIO_LINE_DIRECTION_IN;
220 }
221
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)222 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
223 unsigned int offset)
224 {
225 struct tegra_gpio *gpio = gpiochip_get_data(chip);
226 void __iomem *base;
227 u32 value;
228
229 base = tegra186_gpio_get_base(gpio, offset);
230 if (WARN_ON(base == NULL))
231 return -ENODEV;
232
233 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
234 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
235 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
236
237 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
238 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
239 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
240 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
241
242 return 0;
243 }
244
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)245 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
246 unsigned int offset, int level)
247 {
248 struct tegra_gpio *gpio = gpiochip_get_data(chip);
249 void __iomem *base;
250 u32 value;
251
252 /* configure output level first */
253 chip->set(chip, offset, level);
254
255 base = tegra186_gpio_get_base(gpio, offset);
256 if (WARN_ON(base == NULL))
257 return -EINVAL;
258
259 /* set the direction */
260 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
261 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
262 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
263
264 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
265 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
266 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
267 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
268
269 return 0;
270 }
271
272 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
273
tegra186_gpio_en_hw_ts(struct gpio_chip * gc,u32 offset,unsigned long flags)274 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
275 unsigned long flags)
276 {
277 struct tegra_gpio *gpio;
278 void __iomem *base;
279 int value;
280
281 if (!gc)
282 return -EINVAL;
283
284 gpio = gpiochip_get_data(gc);
285 if (!gpio)
286 return -ENODEV;
287
288 base = tegra186_gpio_get_base(gpio, offset);
289 if (WARN_ON(base == NULL))
290 return -EINVAL;
291
292 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
293 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
294
295 if (flags == HTE_BOTH_EDGES) {
296 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
297 } else if (flags == HTE_RISING_EDGE_TS) {
298 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
299 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
300 } else if (flags == HTE_FALLING_EDGE_TS) {
301 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
302 }
303
304 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
305
306 return 0;
307 }
308
tegra186_gpio_dis_hw_ts(struct gpio_chip * gc,u32 offset,unsigned long flags)309 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
310 unsigned long flags)
311 {
312 struct tegra_gpio *gpio;
313 void __iomem *base;
314 int value;
315
316 if (!gc)
317 return -EINVAL;
318
319 gpio = gpiochip_get_data(gc);
320 if (!gpio)
321 return -ENODEV;
322
323 base = tegra186_gpio_get_base(gpio, offset);
324 if (WARN_ON(base == NULL))
325 return -EINVAL;
326
327 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
328 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
329 if (flags == HTE_BOTH_EDGES) {
330 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
331 } else if (flags == HTE_RISING_EDGE_TS) {
332 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
333 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
334 } else if (flags == HTE_FALLING_EDGE_TS) {
335 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
336 }
337 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
338
339 return 0;
340 }
341
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)342 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
343 {
344 struct tegra_gpio *gpio = gpiochip_get_data(chip);
345 void __iomem *base;
346 u32 value;
347
348 base = tegra186_gpio_get_base(gpio, offset);
349 if (WARN_ON(base == NULL))
350 return -ENODEV;
351
352 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
353 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
354 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
355 else
356 value = readl(base + TEGRA186_GPIO_INPUT);
357
358 return value & BIT(0);
359 }
360
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)361 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
362 int level)
363 {
364 struct tegra_gpio *gpio = gpiochip_get_data(chip);
365 void __iomem *base;
366 u32 value;
367
368 base = tegra186_gpio_get_base(gpio, offset);
369 if (WARN_ON(base == NULL))
370 return;
371
372 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
373 if (level == 0)
374 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
375 else
376 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
377
378 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
379 }
380
tegra186_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)381 static int tegra186_gpio_set_config(struct gpio_chip *chip,
382 unsigned int offset,
383 unsigned long config)
384 {
385 struct tegra_gpio *gpio = gpiochip_get_data(chip);
386 u32 debounce, value;
387 void __iomem *base;
388
389 base = tegra186_gpio_get_base(gpio, offset);
390 if (base == NULL)
391 return -ENXIO;
392
393 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
394 return -ENOTSUPP;
395
396 debounce = pinconf_to_config_argument(config);
397
398 /*
399 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
400 * time.
401 */
402 if (debounce > 255000)
403 return -EINVAL;
404
405 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
406
407 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
408 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
409
410 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
411 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
412 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
413
414 return 0;
415 }
416
tegra186_gpio_add_pin_ranges(struct gpio_chip * chip)417 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
418 {
419 struct tegra_gpio *gpio = gpiochip_get_data(chip);
420 struct pinctrl_dev *pctldev;
421 struct device_node *np;
422 unsigned int i, j;
423 int err;
424
425 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
426 return 0;
427
428 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
429 if (!np)
430 return -ENODEV;
431
432 pctldev = of_pinctrl_get(np);
433 of_node_put(np);
434 if (!pctldev)
435 return -EPROBE_DEFER;
436
437 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
438 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
439 const char *group = gpio->soc->pin_ranges[i].group;
440
441 port = pin / 8;
442 pin = pin % 8;
443
444 if (port >= gpio->soc->num_ports) {
445 dev_warn(chip->parent, "invalid port %u for %s\n",
446 port, group);
447 continue;
448 }
449
450 for (j = 0; j < port; j++)
451 pin += gpio->soc->ports[j].pins;
452
453 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
454 if (err < 0)
455 return err;
456 }
457
458 return 0;
459 }
460
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)461 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
462 const struct of_phandle_args *spec,
463 u32 *flags)
464 {
465 struct tegra_gpio *gpio = gpiochip_get_data(chip);
466 unsigned int port, pin, i, offset = 0;
467
468 if (WARN_ON(chip->of_gpio_n_cells < 2))
469 return -EINVAL;
470
471 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
472 return -EINVAL;
473
474 port = spec->args[0] / 8;
475 pin = spec->args[0] % 8;
476
477 if (port >= gpio->soc->num_ports) {
478 dev_err(chip->parent, "invalid port number: %u\n", port);
479 return -EINVAL;
480 }
481
482 for (i = 0; i < port; i++)
483 offset += gpio->soc->ports[i].pins;
484
485 if (flags)
486 *flags = spec->args[1];
487
488 return offset + pin;
489 }
490
491 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
492
tegra186_irq_ack(struct irq_data * data)493 static void tegra186_irq_ack(struct irq_data *data)
494 {
495 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
496 struct tegra_gpio *gpio = to_tegra_gpio(gc);
497 void __iomem *base;
498
499 base = tegra186_gpio_get_base(gpio, data->hwirq);
500 if (WARN_ON(base == NULL))
501 return;
502
503 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
504 }
505
tegra186_irq_mask(struct irq_data * data)506 static void tegra186_irq_mask(struct irq_data *data)
507 {
508 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
509 struct tegra_gpio *gpio = to_tegra_gpio(gc);
510 void __iomem *base;
511 u32 value;
512
513 base = tegra186_gpio_get_base(gpio, data->hwirq);
514 if (WARN_ON(base == NULL))
515 return;
516
517 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
518 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
519 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
520
521 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
522 }
523
tegra186_irq_unmask(struct irq_data * data)524 static void tegra186_irq_unmask(struct irq_data *data)
525 {
526 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
527 struct tegra_gpio *gpio = to_tegra_gpio(gc);
528 void __iomem *base;
529 u32 value;
530
531 base = tegra186_gpio_get_base(gpio, data->hwirq);
532 if (WARN_ON(base == NULL))
533 return;
534
535 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
536
537 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
538 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
539 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
540 }
541
tegra186_irq_set_type(struct irq_data * data,unsigned int type)542 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
543 {
544 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
545 struct tegra_gpio *gpio = to_tegra_gpio(gc);
546 void __iomem *base;
547 u32 value;
548
549 base = tegra186_gpio_get_base(gpio, data->hwirq);
550 if (WARN_ON(base == NULL))
551 return -ENODEV;
552
553 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
554 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
555 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
556
557 switch (type & IRQ_TYPE_SENSE_MASK) {
558 case IRQ_TYPE_NONE:
559 break;
560
561 case IRQ_TYPE_EDGE_RISING:
562 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
563 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
564 break;
565
566 case IRQ_TYPE_EDGE_FALLING:
567 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
568 break;
569
570 case IRQ_TYPE_EDGE_BOTH:
571 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
572 break;
573
574 case IRQ_TYPE_LEVEL_HIGH:
575 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
576 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
577 break;
578
579 case IRQ_TYPE_LEVEL_LOW:
580 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
581 break;
582
583 default:
584 return -EINVAL;
585 }
586
587 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
588
589 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
590 irq_set_handler_locked(data, handle_level_irq);
591 else
592 irq_set_handler_locked(data, handle_edge_irq);
593
594 if (data->parent_data)
595 return irq_chip_set_type_parent(data, type);
596
597 return 0;
598 }
599
tegra186_irq_set_wake(struct irq_data * data,unsigned int on)600 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
601 {
602 if (data->parent_data)
603 return irq_chip_set_wake_parent(data, on);
604
605 return 0;
606 }
607
tegra186_irq_print_chip(struct irq_data * data,struct seq_file * p)608 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
609 {
610 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
611
612 seq_printf(p, dev_name(gc->parent));
613 }
614
615 static const struct irq_chip tegra186_gpio_irq_chip = {
616 .irq_ack = tegra186_irq_ack,
617 .irq_mask = tegra186_irq_mask,
618 .irq_unmask = tegra186_irq_unmask,
619 .irq_set_type = tegra186_irq_set_type,
620 .irq_set_wake = tegra186_irq_set_wake,
621 .irq_print_chip = tegra186_irq_print_chip,
622 .flags = IRQCHIP_IMMUTABLE,
623 GPIOCHIP_IRQ_RESOURCE_HELPERS,
624 };
625
tegra186_gpio_irq(struct irq_desc * desc)626 static void tegra186_gpio_irq(struct irq_desc *desc)
627 {
628 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
629 struct irq_domain *domain = gpio->gpio.irq.domain;
630 struct irq_chip *chip = irq_desc_get_chip(desc);
631 unsigned int parent = irq_desc_get_irq(desc);
632 unsigned int i, j, offset = 0;
633
634 chained_irq_enter(chip, desc);
635
636 for (i = 0; i < gpio->soc->num_ports; i++) {
637 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
638 unsigned int pin;
639 unsigned long value;
640 void __iomem *base;
641
642 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
643
644 /* skip ports that are not associated with this bank */
645 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
646 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
647 break;
648 }
649
650 if (j == gpio->num_irqs_per_bank)
651 goto skip;
652
653 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
654
655 for_each_set_bit(pin, &value, port->pins) {
656 int ret = generic_handle_domain_irq(domain, offset + pin);
657 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
658 }
659
660 skip:
661 offset += port->pins;
662 }
663
664 chained_irq_exit(chip, desc);
665 }
666
tegra186_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)667 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
668 struct irq_fwspec *fwspec,
669 unsigned long *hwirq,
670 unsigned int *type)
671 {
672 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
673 unsigned int port, pin, i, offset = 0;
674
675 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
676 return -EINVAL;
677
678 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
679 return -EINVAL;
680
681 port = fwspec->param[0] / 8;
682 pin = fwspec->param[0] % 8;
683
684 if (port >= gpio->soc->num_ports)
685 return -EINVAL;
686
687 for (i = 0; i < port; i++)
688 offset += gpio->soc->ports[i].pins;
689
690 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
691 *hwirq = offset + pin;
692
693 return 0;
694 }
695
tegra186_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)696 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
697 union gpio_irq_fwspec *gfwspec,
698 unsigned int parent_hwirq,
699 unsigned int parent_type)
700 {
701 struct tegra_gpio *gpio = gpiochip_get_data(chip);
702 struct irq_fwspec *fwspec = &gfwspec->fwspec;
703
704 fwspec->fwnode = chip->irq.parent_domain->fwnode;
705 fwspec->param_count = 3;
706 fwspec->param[0] = gpio->soc->instance;
707 fwspec->param[1] = parent_hwirq;
708 fwspec->param[2] = parent_type;
709
710 return 0;
711 }
712
tegra186_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)713 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
714 unsigned int hwirq,
715 unsigned int type,
716 unsigned int *parent_hwirq,
717 unsigned int *parent_type)
718 {
719 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
720 *parent_type = type;
721
722 return 0;
723 }
724
tegra186_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)725 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
726 unsigned int offset)
727 {
728 struct tegra_gpio *gpio = gpiochip_get_data(chip);
729 unsigned int i;
730
731 for (i = 0; i < gpio->soc->num_ports; i++) {
732 if (offset < gpio->soc->ports[i].pins)
733 break;
734
735 offset -= gpio->soc->ports[i].pins;
736 }
737
738 return offset + i * 8;
739 }
740
741 static const struct of_device_id tegra186_pmc_of_match[] = {
742 { .compatible = "nvidia,tegra186-pmc" },
743 { .compatible = "nvidia,tegra194-pmc" },
744 { .compatible = "nvidia,tegra234-pmc" },
745 { /* sentinel */ }
746 };
747
tegra186_gpio_init_route_mapping(struct tegra_gpio * gpio)748 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
749 {
750 struct device *dev = gpio->gpio.parent;
751 unsigned int i;
752 u32 value;
753
754 for (i = 0; i < gpio->soc->num_ports; i++) {
755 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
756 unsigned int offset, p = port->port;
757 void __iomem *base;
758
759 base = gpio->secure + port->bank * 0x1000 + 0x800;
760
761 value = readl(base + TEGRA186_GPIO_CTL_SCR);
762
763 /*
764 * For controllers that haven't been locked down yet, make
765 * sure to program the default interrupt route mapping.
766 */
767 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
768 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
769 /*
770 * On Tegra194 and later, each pin can be routed to one or more
771 * interrupts.
772 */
773 dev_dbg(dev, "programming default interrupt routing for port %s\n",
774 port->name);
775
776 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
777
778 /*
779 * By default we only want to route GPIO pins to IRQ 0. This works
780 * only under the assumption that we're running as the host kernel
781 * and hence all GPIO pins are owned by Linux.
782 *
783 * For cases where Linux is the guest OS, the hypervisor will have
784 * to configure the interrupt routing and pass only the valid
785 * interrupts via device tree.
786 */
787 value = readl(base + offset);
788 value = BIT(port->pins) - 1;
789 writel(value, base + offset);
790 }
791 }
792 }
793
tegra186_gpio_irqs_per_bank(struct tegra_gpio * gpio)794 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
795 {
796 struct device *dev = gpio->gpio.parent;
797
798 if (gpio->num_irq > gpio->num_banks) {
799 if (gpio->num_irq % gpio->num_banks != 0)
800 goto error;
801 }
802
803 if (gpio->num_irq < gpio->num_banks)
804 goto error;
805
806 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
807
808 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
809 goto error;
810
811 return 0;
812
813 error:
814 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
815 gpio->num_irq, gpio->num_banks);
816 return -EINVAL;
817 }
818
tegra186_gpio_probe(struct platform_device * pdev)819 static int tegra186_gpio_probe(struct platform_device *pdev)
820 {
821 unsigned int i, j, offset;
822 struct gpio_irq_chip *irq;
823 struct tegra_gpio *gpio;
824 struct device_node *np;
825 struct resource *res;
826 char **names;
827 int err;
828
829 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
830 if (!gpio)
831 return -ENOMEM;
832
833 gpio->soc = device_get_match_data(&pdev->dev);
834 gpio->gpio.label = gpio->soc->name;
835 gpio->gpio.parent = &pdev->dev;
836
837 /* count the number of banks in the controller */
838 for (i = 0; i < gpio->soc->num_ports; i++)
839 if (gpio->soc->ports[i].bank > gpio->num_banks)
840 gpio->num_banks = gpio->soc->ports[i].bank;
841
842 gpio->num_banks++;
843
844 /* get register apertures */
845 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security");
846 if (!res)
847 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 gpio->secure = devm_ioremap_resource(&pdev->dev, res);
849 if (IS_ERR(gpio->secure))
850 return PTR_ERR(gpio->secure);
851
852 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
853 if (!res)
854 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
855 gpio->base = devm_ioremap_resource(&pdev->dev, res);
856 if (IS_ERR(gpio->base))
857 return PTR_ERR(gpio->base);
858
859 err = platform_irq_count(pdev);
860 if (err < 0)
861 return err;
862
863 gpio->num_irq = err;
864
865 err = tegra186_gpio_irqs_per_bank(gpio);
866 if (err < 0)
867 return err;
868
869 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
870 GFP_KERNEL);
871 if (!gpio->irq)
872 return -ENOMEM;
873
874 for (i = 0; i < gpio->num_irq; i++) {
875 err = platform_get_irq(pdev, i);
876 if (err < 0)
877 return err;
878
879 gpio->irq[i] = err;
880 }
881
882 gpio->gpio.request = gpiochip_generic_request;
883 gpio->gpio.free = gpiochip_generic_free;
884 gpio->gpio.get_direction = tegra186_gpio_get_direction;
885 gpio->gpio.direction_input = tegra186_gpio_direction_input;
886 gpio->gpio.direction_output = tegra186_gpio_direction_output;
887 gpio->gpio.get = tegra186_gpio_get;
888 gpio->gpio.set = tegra186_gpio_set;
889 gpio->gpio.set_config = tegra186_gpio_set_config;
890 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
891 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
892 if (gpio->soc->has_gte) {
893 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
894 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
895 }
896
897 gpio->gpio.base = -1;
898
899 for (i = 0; i < gpio->soc->num_ports; i++)
900 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
901
902 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
903 sizeof(*names), GFP_KERNEL);
904 if (!names)
905 return -ENOMEM;
906
907 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
908 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
909 char *name;
910
911 for (j = 0; j < port->pins; j++) {
912 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
913 "P%s.%02x", port->name, j);
914 if (!name)
915 return -ENOMEM;
916
917 names[offset + j] = name;
918 }
919
920 offset += port->pins;
921 }
922
923 gpio->gpio.names = (const char * const *)names;
924
925 #if defined(CONFIG_OF_GPIO)
926 gpio->gpio.of_gpio_n_cells = 2;
927 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
928 #endif /* CONFIG_OF_GPIO */
929
930 irq = &gpio->gpio.irq;
931 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
932 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
933 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
934 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
935 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
936 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
937 irq->handler = handle_simple_irq;
938 irq->default_type = IRQ_TYPE_NONE;
939 irq->parent_handler = tegra186_gpio_irq;
940 irq->parent_handler_data = gpio;
941 irq->num_parents = gpio->num_irq;
942
943 /*
944 * To simplify things, use a single interrupt per bank for now. Some
945 * chips support up to 8 interrupts per bank, which can be useful to
946 * distribute the load and decrease the processing latency for GPIOs
947 * but it also requires a more complicated interrupt routing than we
948 * currently program.
949 */
950 if (gpio->num_irqs_per_bank > 1) {
951 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
952 sizeof(*irq->parents), GFP_KERNEL);
953 if (!irq->parents)
954 return -ENOMEM;
955
956 for (i = 0; i < gpio->num_banks; i++)
957 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
958
959 irq->num_parents = gpio->num_banks;
960 } else {
961 irq->num_parents = gpio->num_irq;
962 irq->parents = gpio->irq;
963 }
964
965 if (gpio->soc->num_irqs_per_bank > 1)
966 tegra186_gpio_init_route_mapping(gpio);
967
968 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
969 if (np) {
970 if (of_device_is_available(np)) {
971 irq->parent_domain = irq_find_host(np);
972 of_node_put(np);
973
974 if (!irq->parent_domain)
975 return -EPROBE_DEFER;
976 } else {
977 of_node_put(np);
978 }
979 }
980
981 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
982 sizeof(*irq->map), GFP_KERNEL);
983 if (!irq->map)
984 return -ENOMEM;
985
986 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
987 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
988
989 for (j = 0; j < port->pins; j++)
990 irq->map[offset + j] = irq->parents[port->bank];
991
992 offset += port->pins;
993 }
994
995 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
996 }
997
998 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
999 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
1000 .name = #_name, \
1001 .bank = _bank, \
1002 .port = _port, \
1003 .pins = _pins, \
1004 }
1005
1006 static const struct tegra_gpio_port tegra186_main_ports[] = {
1007 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
1008 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
1009 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
1010 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
1011 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
1012 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
1013 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
1014 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
1015 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
1016 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
1017 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
1018 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
1019 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
1020 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
1021 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
1022 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
1023 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
1024 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
1025 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
1026 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
1027 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
1028 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
1029 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1030 };
1031
1032 static const struct tegra_gpio_soc tegra186_main_soc = {
1033 .num_ports = ARRAY_SIZE(tegra186_main_ports),
1034 .ports = tegra186_main_ports,
1035 .name = "tegra186-gpio",
1036 .instance = 0,
1037 .num_irqs_per_bank = 1,
1038 .has_vm_support = false,
1039 };
1040
1041 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1042 [TEGRA186_AON_GPIO_PORT_##_name] = { \
1043 .name = #_name, \
1044 .bank = _bank, \
1045 .port = _port, \
1046 .pins = _pins, \
1047 }
1048
1049 static const struct tegra_gpio_port tegra186_aon_ports[] = {
1050 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
1051 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
1052 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
1053 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
1054 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
1055 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
1056 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
1057 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
1058 };
1059
1060 static const struct tegra_gpio_soc tegra186_aon_soc = {
1061 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
1062 .ports = tegra186_aon_ports,
1063 .name = "tegra186-gpio-aon",
1064 .instance = 1,
1065 .num_irqs_per_bank = 1,
1066 .has_vm_support = false,
1067 };
1068
1069 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1070 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
1071 .name = #_name, \
1072 .bank = _bank, \
1073 .port = _port, \
1074 .pins = _pins, \
1075 }
1076
1077 static const struct tegra_gpio_port tegra194_main_ports[] = {
1078 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1079 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1080 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1081 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1082 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1083 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1084 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1085 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1086 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1087 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1088 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1089 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1090 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1091 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1092 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1093 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1094 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1095 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1096 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1097 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1098 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1099 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1100 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1101 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1102 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1103 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1104 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1105 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1106 };
1107
1108 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1109 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1110 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1111 };
1112
1113 static const struct tegra_gpio_soc tegra194_main_soc = {
1114 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1115 .ports = tegra194_main_ports,
1116 .name = "tegra194-gpio",
1117 .instance = 0,
1118 .num_irqs_per_bank = 8,
1119 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1120 .pin_ranges = tegra194_main_pin_ranges,
1121 .pinmux = "nvidia,tegra194-pinmux",
1122 .has_vm_support = true,
1123 };
1124
1125 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1126 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1127 .name = #_name, \
1128 .bank = _bank, \
1129 .port = _port, \
1130 .pins = _pins, \
1131 }
1132
1133 static const struct tegra_gpio_port tegra194_aon_ports[] = {
1134 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1135 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1136 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1137 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1138 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1139 };
1140
1141 static const struct tegra_gpio_soc tegra194_aon_soc = {
1142 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1143 .ports = tegra194_aon_ports,
1144 .name = "tegra194-gpio-aon",
1145 .instance = 1,
1146 .num_irqs_per_bank = 8,
1147 .has_gte = true,
1148 .has_vm_support = false,
1149 };
1150
1151 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1152 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1153 .name = #_name, \
1154 .bank = _bank, \
1155 .port = _port, \
1156 .pins = _pins, \
1157 }
1158
1159 static const struct tegra_gpio_port tegra234_main_ports[] = {
1160 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1161 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1162 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1163 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1164 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1165 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1166 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1167 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1168 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1169 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1170 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1171 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1172 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1173 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1174 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1175 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1176 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1177 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1178 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1179 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1180 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1181 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1182 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1183 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1184 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1185 };
1186
1187 static const struct tegra_gpio_soc tegra234_main_soc = {
1188 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1189 .ports = tegra234_main_ports,
1190 .name = "tegra234-gpio",
1191 .instance = 0,
1192 .num_irqs_per_bank = 8,
1193 .has_vm_support = true,
1194 };
1195
1196 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1197 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1198 .name = #_name, \
1199 .bank = _bank, \
1200 .port = _port, \
1201 .pins = _pins, \
1202 }
1203
1204 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1205 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1206 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1207 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1208 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1209 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1210 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1211 };
1212
1213 static const struct tegra_gpio_soc tegra234_aon_soc = {
1214 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1215 .ports = tegra234_aon_ports,
1216 .name = "tegra234-gpio-aon",
1217 .instance = 1,
1218 .num_irqs_per_bank = 8,
1219 .has_gte = true,
1220 .has_vm_support = false,
1221 };
1222
1223 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1224 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1225 .name = #_name, \
1226 .bank = _bank, \
1227 .port = _port, \
1228 .pins = _pins, \
1229 }
1230
1231 static const struct tegra_gpio_port tegra241_main_ports[] = {
1232 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1233 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1234 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1235 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1236 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1237 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1238 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1239 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1240 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1241 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1242 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1243 };
1244
1245 static const struct tegra_gpio_soc tegra241_main_soc = {
1246 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1247 .ports = tegra241_main_ports,
1248 .name = "tegra241-gpio",
1249 .instance = 0,
1250 .num_irqs_per_bank = 8,
1251 .has_vm_support = false,
1252 };
1253
1254 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1255 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1256 .name = #_name, \
1257 .bank = _bank, \
1258 .port = _port, \
1259 .pins = _pins, \
1260 }
1261
1262 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1263 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1264 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1265 };
1266
1267 static const struct tegra_gpio_soc tegra241_aon_soc = {
1268 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1269 .ports = tegra241_aon_ports,
1270 .name = "tegra241-gpio-aon",
1271 .instance = 1,
1272 .num_irqs_per_bank = 8,
1273 .has_vm_support = false,
1274 };
1275
1276 static const struct of_device_id tegra186_gpio_of_match[] = {
1277 {
1278 .compatible = "nvidia,tegra186-gpio",
1279 .data = &tegra186_main_soc
1280 }, {
1281 .compatible = "nvidia,tegra186-gpio-aon",
1282 .data = &tegra186_aon_soc
1283 }, {
1284 .compatible = "nvidia,tegra194-gpio",
1285 .data = &tegra194_main_soc
1286 }, {
1287 .compatible = "nvidia,tegra194-gpio-aon",
1288 .data = &tegra194_aon_soc
1289 }, {
1290 .compatible = "nvidia,tegra234-gpio",
1291 .data = &tegra234_main_soc
1292 }, {
1293 .compatible = "nvidia,tegra234-gpio-aon",
1294 .data = &tegra234_aon_soc
1295 }, {
1296 /* sentinel */
1297 }
1298 };
1299 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1300
1301 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1302 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1303 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1304 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1305 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1306 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1307 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1308 {}
1309 };
1310 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1311
1312 static struct platform_driver tegra186_gpio_driver = {
1313 .driver = {
1314 .name = "tegra186-gpio",
1315 .of_match_table = tegra186_gpio_of_match,
1316 .acpi_match_table = tegra186_gpio_acpi_match,
1317 },
1318 .probe = tegra186_gpio_probe,
1319 };
1320 module_platform_driver(tegra186_gpio_driver);
1321
1322 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1323 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1324 MODULE_LICENSE("GPL v2");
1325