1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
14
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
21
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
25
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
28
29 /* max buffer size for trace and debug messages */
30 #define XHCI_MSG_MAX 500
31
32 /* xHCI PCI Configuration Registers */
33 #define XHCI_SBRN_OFFSET (0x60)
34
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
36 #define MAX_HC_SLOTS 256
37 /* Section 5.3.3 - MaxPorts */
38 #define MAX_HC_PORTS 127
39
40 /*
41 * xHCI register interface.
42 * This corresponds to the eXtensible Host Controller Interface (xHCI)
43 * Revision 0.95 specification
44 */
45
46 /**
47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
48 * @hc_capbase: length of the capabilities register and HC version number
49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
52 * @hcc_params: HCCPARAMS - Capability Parameters
53 * @db_off: DBOFF - Doorbell array offset
54 * @run_regs_off: RTSOFF - Runtime register space offset
55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
56 */
57 struct xhci_cap_regs {
58 __le32 hc_capbase;
59 __le32 hcs_params1;
60 __le32 hcs_params2;
61 __le32 hcs_params3;
62 __le32 hcc_params;
63 __le32 db_off;
64 __le32 run_regs_off;
65 __le32 hcc_params2; /* xhci 1.1 */
66 /* Reserved up to (CAPLENGTH - 0x1C) */
67 };
68
69 /* Number of registers per port */
70 #define NUM_PORT_REGS 4
71
72 #define PORTSC 0
73 #define PORTPMSC 1
74 #define PORTLI 2
75 #define PORTHLPMC 3
76
77 /**
78 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
79 * @command: USBCMD - xHC command register
80 * @status: USBSTS - xHC status register
81 * @page_size: This indicates the page size that the host controller
82 * supports. If bit n is set, the HC supports a page size
83 * of 2^(n+12), up to a 128MB page size.
84 * 4K is the minimum page size.
85 * @cmd_ring: CRP - 64-bit Command Ring Pointer
86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
87 * @config_reg: CONFIG - Configure Register
88 * @port_status_base: PORTSCn - base address for Port Status and Control
89 * Each port has a Port Status and Control register,
90 * followed by a Port Power Management Status and Control
91 * register, a Port Link Info register, and a reserved
92 * register.
93 * @port_power_base: PORTPMSCn - base address for
94 * Port Power Management Status and Control
95 * @port_link_base: PORTLIn - base address for Port Link Info (current
96 * Link PM state and control) for USB 2.1 and USB 3.0
97 * devices.
98 */
99 struct xhci_op_regs {
100 __le32 command;
101 __le32 status;
102 __le32 page_size;
103 __le32 reserved1;
104 __le32 reserved2;
105 __le32 dev_notification;
106 __le64 cmd_ring;
107 /* rsvd: offset 0x20-2F */
108 __le32 reserved3[4];
109 __le64 dcbaa_ptr;
110 __le32 config_reg;
111 /* rsvd: offset 0x3C-3FF */
112 __le32 reserved4[241];
113 /* port 1 registers, which serve as a base address for other ports */
114 __le32 port_status_base;
115 __le32 port_power_base;
116 __le32 port_link_base;
117 __le32 reserved5;
118 /* registers for ports 2-255 */
119 __le32 reserved6[NUM_PORT_REGS*254];
120 };
121
122 /* USBCMD - USB command - command bitmasks */
123 /* start/stop HC execution - do not write unless HC is halted*/
124 #define CMD_RUN XHCI_CMD_RUN
125 /* Reset HC - resets internal HC state machine and all registers (except
126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
127 * The xHCI driver must reinitialize the xHC after setting this bit.
128 */
129 #define CMD_RESET (1 << 1)
130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
131 #define CMD_EIE XHCI_CMD_EIE
132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
133 #define CMD_HSEIE XHCI_CMD_HSEIE
134 /* bits 4:6 are reserved (and should be preserved on writes). */
135 /* light reset (port status stays unchanged) - reset completed when this is 0 */
136 #define CMD_LRESET (1 << 7)
137 /* host controller save/restore state. */
138 #define CMD_CSS (1 << 8)
139 #define CMD_CRS (1 << 9)
140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
141 #define CMD_EWE XHCI_CMD_EWE
142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
144 * '0' means the xHC can power it off if all ports are in the disconnect,
145 * disabled, or powered-off state.
146 */
147 #define CMD_PM_INDEX (1 << 11)
148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
149 #define CMD_ETE (1 << 14)
150 /* bits 15:31 are reserved (and should be preserved on writes). */
151
152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
153 #define XHCI_RESET_SHORT_USEC (250 * 1000)
154
155 /* IMAN - Interrupt Management Register */
156 #define IMAN_IE (1 << 1)
157 #define IMAN_IP (1 << 0)
158
159 /* USBSTS - USB status - status bitmasks */
160 /* HC not running - set to 1 when run/stop bit is cleared. */
161 #define STS_HALT XHCI_STS_HALT
162 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
163 #define STS_FATAL (1 << 2)
164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
165 #define STS_EINT (1 << 3)
166 /* port change detect */
167 #define STS_PORT (1 << 4)
168 /* bits 5:7 reserved and zeroed */
169 /* save state status - '1' means xHC is saving state */
170 #define STS_SAVE (1 << 8)
171 /* restore state status - '1' means xHC is restoring state */
172 #define STS_RESTORE (1 << 9)
173 /* true: save or restore error */
174 #define STS_SRE (1 << 10)
175 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
176 #define STS_CNR XHCI_STS_CNR
177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
178 #define STS_HCE (1 << 12)
179 /* bits 13:31 reserved and should be preserved */
180
181 /*
182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
183 * Generate a device notification event when the HC sees a transaction with a
184 * notification type that matches a bit set in this bit field.
185 */
186 #define DEV_NOTE_MASK (0xffff)
187 #define ENABLE_DEV_NOTE(x) (1 << (x))
188 /* Most of the device notification types should only be used for debug.
189 * SW does need to pay attention to function wake notifications.
190 */
191 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
192
193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
194 /* bit 0 is the command ring cycle state */
195 /* stop ring operation after completion of the currently executing command */
196 #define CMD_RING_PAUSE (1 << 1)
197 /* stop ring immediately - abort the currently executing command */
198 #define CMD_RING_ABORT (1 << 2)
199 /* true: command ring is running */
200 #define CMD_RING_RUNNING (1 << 3)
201 /* bits 4:5 reserved and should be preserved */
202 /* Command Ring pointer - bit mask for the lower 32 bits. */
203 #define CMD_RING_RSVD_BITS (0x3f)
204
205 /* CONFIG - Configure Register - config_reg bitmasks */
206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
207 #define MAX_DEVS(p) ((p) & 0xff)
208 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
209 #define CONFIG_U3E (1 << 8)
210 /* bit 9: Configuration Information Enable, xhci 1.1 */
211 #define CONFIG_CIE (1 << 9)
212 /* bits 10:31 - reserved and should be preserved */
213
214 /**
215 * struct xhci_intr_reg - Interrupt Register Set
216 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
217 * interrupts and check for pending interrupts.
218 * @irq_control: IMOD - Interrupt Moderation Register.
219 * Used to throttle interrupts.
220 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
221 * @erst_base: ERST base address.
222 * @erst_dequeue: Event ring dequeue pointer.
223 *
224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
225 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
226 * multiple segments of the same size. The HC places events on the ring and
227 * "updates the Cycle bit in the TRBs to indicate to software the current
228 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
229 * updates the dequeue pointer.
230 */
231 struct xhci_intr_reg {
232 __le32 irq_pending;
233 __le32 irq_control;
234 __le32 erst_size;
235 __le32 rsvd;
236 __le64 erst_base;
237 __le64 erst_dequeue;
238 };
239
240 /* irq_pending bitmasks */
241 #define ER_IRQ_PENDING(p) ((p) & 0x1)
242 /* bits 2:31 need to be preserved */
243 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
244 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
245 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
246 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
247
248 /* irq_control bitmasks */
249 /* Minimum interval between interrupts (in 250ns intervals). The interval
250 * between interrupts will be longer if there are no events on the event ring.
251 * Default is 4000 (1 ms).
252 */
253 #define ER_IRQ_INTERVAL_MASK (0xffff)
254 /* Counter used to count down the time to the next interrupt - HW use only */
255 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
256
257 /* erst_size bitmasks */
258 /* Preserve bits 16:31 of erst_size */
259 #define ERST_SIZE_MASK (0xffff << 16)
260
261 /* erst_base bitmasks */
262 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
263
264 /* erst_dequeue bitmasks */
265 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
266 * where the current dequeue pointer lies. This is an optional HW hint.
267 */
268 #define ERST_DESI_MASK (0x7)
269 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
270 * a work queue (or delayed service routine)?
271 */
272 #define ERST_EHB (1 << 3)
273 #define ERST_PTR_MASK (0xf)
274
275 /**
276 * struct xhci_run_regs
277 * @microframe_index:
278 * MFINDEX - current microframe number
279 *
280 * Section 5.5 Host Controller Runtime Registers:
281 * "Software should read and write these registers using only Dword (32 bit)
282 * or larger accesses"
283 */
284 struct xhci_run_regs {
285 __le32 microframe_index;
286 __le32 rsvd[7];
287 struct xhci_intr_reg ir_set[128];
288 };
289
290 /**
291 * struct doorbell_array
292 *
293 * Bits 0 - 7: Endpoint target
294 * Bits 8 - 15: RsvdZ
295 * Bits 16 - 31: Stream ID
296 *
297 * Section 5.6
298 */
299 struct xhci_doorbell_array {
300 __le32 doorbell[256];
301 };
302
303 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
304 #define DB_VALUE_HOST 0x00000000
305
306 /**
307 * struct xhci_protocol_caps
308 * @revision: major revision, minor revision, capability ID,
309 * and next capability pointer.
310 * @name_string: Four ASCII characters to say which spec this xHC
311 * follows, typically "USB ".
312 * @port_info: Port offset, count, and protocol-defined information.
313 */
314 struct xhci_protocol_caps {
315 u32 revision;
316 u32 name_string;
317 u32 port_info;
318 };
319
320 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
321 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
322 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
323 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
324 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
325
326 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
327 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
328 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
329 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
330 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
331 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
332
333 #define PLT_MASK (0x03 << 6)
334 #define PLT_SYM (0x00 << 6)
335 #define PLT_ASYM_RX (0x02 << 6)
336 #define PLT_ASYM_TX (0x03 << 6)
337
338 /**
339 * struct xhci_container_ctx
340 * @type: Type of context. Used to calculated offsets to contained contexts.
341 * @size: Size of the context data
342 * @bytes: The raw context data given to HW
343 * @dma: dma address of the bytes
344 *
345 * Represents either a Device or Input context. Holds a pointer to the raw
346 * memory used for the context (bytes) and dma address of it (dma).
347 */
348 struct xhci_container_ctx {
349 unsigned type;
350 #define XHCI_CTX_TYPE_DEVICE 0x1
351 #define XHCI_CTX_TYPE_INPUT 0x2
352
353 int size;
354
355 u8 *bytes;
356 dma_addr_t dma;
357 };
358
359 /**
360 * struct xhci_slot_ctx
361 * @dev_info: Route string, device speed, hub info, and last valid endpoint
362 * @dev_info2: Max exit latency for device number, root hub port number
363 * @tt_info: tt_info is used to construct split transaction tokens
364 * @dev_state: slot state and device address
365 *
366 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
367 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
368 * reserved at the end of the slot context for HC internal use.
369 */
370 struct xhci_slot_ctx {
371 __le32 dev_info;
372 __le32 dev_info2;
373 __le32 tt_info;
374 __le32 dev_state;
375 /* offset 0x10 to 0x1f reserved for HC internal use */
376 __le32 reserved[4];
377 };
378
379 /* dev_info bitmasks */
380 /* Route String - 0:19 */
381 #define ROUTE_STRING_MASK (0xfffff)
382 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
383 #define DEV_SPEED (0xf << 20)
384 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
385 /* bit 24 reserved */
386 /* Is this LS/FS device connected through a HS hub? - bit 25 */
387 #define DEV_MTT (0x1 << 25)
388 /* Set if the device is a hub - bit 26 */
389 #define DEV_HUB (0x1 << 26)
390 /* Index of the last valid endpoint context in this device context - 27:31 */
391 #define LAST_CTX_MASK (0x1f << 27)
392 #define LAST_CTX(p) ((p) << 27)
393 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
394 #define SLOT_FLAG (1 << 0)
395 #define EP0_FLAG (1 << 1)
396
397 /* dev_info2 bitmasks */
398 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
399 #define MAX_EXIT (0xffff)
400 /* Root hub port number that is needed to access the USB device */
401 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
402 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
403 /* Maximum number of ports under a hub device */
404 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
405 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
406
407 /* tt_info bitmasks */
408 /*
409 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
410 * The Slot ID of the hub that isolates the high speed signaling from
411 * this low or full-speed device. '0' if attached to root hub port.
412 */
413 #define TT_SLOT (0xff)
414 /*
415 * The number of the downstream facing port of the high-speed hub
416 * '0' if the device is not low or full speed.
417 */
418 #define TT_PORT (0xff << 8)
419 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
420 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
421
422 /* dev_state bitmasks */
423 /* USB device address - assigned by the HC */
424 #define DEV_ADDR_MASK (0xff)
425 /* bits 8:26 reserved */
426 /* Slot state */
427 #define SLOT_STATE (0x1f << 27)
428 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
429
430 #define SLOT_STATE_DISABLED 0
431 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
432 #define SLOT_STATE_DEFAULT 1
433 #define SLOT_STATE_ADDRESSED 2
434 #define SLOT_STATE_CONFIGURED 3
435
436 /**
437 * struct xhci_ep_ctx
438 * @ep_info: endpoint state, streams, mult, and interval information.
439 * @ep_info2: information on endpoint type, max packet size, max burst size,
440 * error count, and whether the HC will force an event for all
441 * transactions.
442 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
443 * defines one stream, this points to the endpoint transfer ring.
444 * Otherwise, it points to a stream context array, which has a
445 * ring pointer for each flow.
446 * @tx_info:
447 * Average TRB lengths for the endpoint ring and
448 * max payload within an Endpoint Service Interval Time (ESIT).
449 *
450 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
451 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
452 * reserved at the end of the endpoint context for HC internal use.
453 */
454 struct xhci_ep_ctx {
455 __le32 ep_info;
456 __le32 ep_info2;
457 __le64 deq;
458 __le32 tx_info;
459 /* offset 0x14 - 0x1f reserved for HC internal use */
460 __le32 reserved[3];
461 };
462
463 /* ep_info bitmasks */
464 /*
465 * Endpoint State - bits 0:2
466 * 0 - disabled
467 * 1 - running
468 * 2 - halted due to halt condition - ok to manipulate endpoint ring
469 * 3 - stopped
470 * 4 - TRB error
471 * 5-7 - reserved
472 */
473 #define EP_STATE_MASK (0x7)
474 #define EP_STATE_DISABLED 0
475 #define EP_STATE_RUNNING 1
476 #define EP_STATE_HALTED 2
477 #define EP_STATE_STOPPED 3
478 #define EP_STATE_ERROR 4
479 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
480
481 /* Mult - Max number of burtst within an interval, in EP companion desc. */
482 #define EP_MULT(p) (((p) & 0x3) << 8)
483 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
484 /* bits 10:14 are Max Primary Streams */
485 /* bit 15 is Linear Stream Array */
486 /* Interval - period between requests to an endpoint - 125u increments. */
487 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
488 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
489 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
490 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
491 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
492 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
493 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
494 #define EP_HAS_LSA (1 << 15)
495 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
496 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
497
498 /* ep_info2 bitmasks */
499 /*
500 * Force Event - generate transfer events for all TRBs for this endpoint
501 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
502 */
503 #define FORCE_EVENT (0x1)
504 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
505 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
506 #define EP_TYPE(p) ((p) << 3)
507 #define ISOC_OUT_EP 1
508 #define BULK_OUT_EP 2
509 #define INT_OUT_EP 3
510 #define CTRL_EP 4
511 #define ISOC_IN_EP 5
512 #define BULK_IN_EP 6
513 #define INT_IN_EP 7
514 /* bit 6 reserved */
515 /* bit 7 is Host Initiate Disable - for disabling stream selection */
516 #define MAX_BURST(p) (((p)&0xff) << 8)
517 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
518 #define MAX_PACKET(p) (((p)&0xffff) << 16)
519 #define MAX_PACKET_MASK (0xffff << 16)
520 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
521
522 /* tx_info bitmasks */
523 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
524 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
525 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
526 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
527
528 /* deq bitmasks */
529 #define EP_CTX_CYCLE_MASK (1 << 0)
530 #define SCTX_DEQ_MASK (~0xfL)
531
532
533 /**
534 * struct xhci_input_control_context
535 * Input control context; see section 6.2.5.
536 *
537 * @drop_context: set the bit of the endpoint context you want to disable
538 * @add_context: set the bit of the endpoint context you want to enable
539 */
540 struct xhci_input_control_ctx {
541 __le32 drop_flags;
542 __le32 add_flags;
543 __le32 rsvd2[6];
544 };
545
546 #define EP_IS_ADDED(ctrl_ctx, i) \
547 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
548 #define EP_IS_DROPPED(ctrl_ctx, i) \
549 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
550
551 /* Represents everything that is needed to issue a command on the command ring.
552 * It's useful to pre-allocate these for commands that cannot fail due to
553 * out-of-memory errors, like freeing streams.
554 */
555 struct xhci_command {
556 /* Input context for changing device state */
557 struct xhci_container_ctx *in_ctx;
558 u32 status;
559 int slot_id;
560 /* If completion is null, no one is waiting on this command
561 * and the structure can be freed after the command completes.
562 */
563 struct completion *completion;
564 union xhci_trb *command_trb;
565 struct list_head cmd_list;
566 /* xHCI command response timeout in milliseconds */
567 unsigned int timeout_ms;
568 };
569
570 /* drop context bitmasks */
571 #define DROP_EP(x) (0x1 << x)
572 /* add context bitmasks */
573 #define ADD_EP(x) (0x1 << x)
574
575 struct xhci_stream_ctx {
576 /* 64-bit stream ring address, cycle state, and stream type */
577 __le64 stream_ring;
578 /* offset 0x14 - 0x1f reserved for HC internal use */
579 __le32 reserved[2];
580 };
581
582 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
583 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
584 /* Secondary stream array type, dequeue pointer is to a transfer ring */
585 #define SCT_SEC_TR 0
586 /* Primary stream array type, dequeue pointer is to a transfer ring */
587 #define SCT_PRI_TR 1
588 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
589 #define SCT_SSA_8 2
590 #define SCT_SSA_16 3
591 #define SCT_SSA_32 4
592 #define SCT_SSA_64 5
593 #define SCT_SSA_128 6
594 #define SCT_SSA_256 7
595
596 /* Assume no secondary streams for now */
597 struct xhci_stream_info {
598 struct xhci_ring **stream_rings;
599 /* Number of streams, including stream 0 (which drivers can't use) */
600 unsigned int num_streams;
601 /* The stream context array may be bigger than
602 * the number of streams the driver asked for
603 */
604 struct xhci_stream_ctx *stream_ctx_array;
605 unsigned int num_stream_ctxs;
606 dma_addr_t ctx_array_dma;
607 /* For mapping physical TRB addresses to segments in stream rings */
608 struct radix_tree_root trb_address_map;
609 struct xhci_command *free_streams_command;
610 };
611
612 #define SMALL_STREAM_ARRAY_SIZE 256
613 #define MEDIUM_STREAM_ARRAY_SIZE 1024
614
615 /* Some Intel xHCI host controllers need software to keep track of the bus
616 * bandwidth. Keep track of endpoint info here. Each root port is allocated
617 * the full bus bandwidth. We must also treat TTs (including each port under a
618 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
619 * (DMI) also limits the total bandwidth (across all domains) that can be used.
620 */
621 struct xhci_bw_info {
622 /* ep_interval is zero-based */
623 unsigned int ep_interval;
624 /* mult and num_packets are one-based */
625 unsigned int mult;
626 unsigned int num_packets;
627 unsigned int max_packet_size;
628 unsigned int max_esit_payload;
629 unsigned int type;
630 };
631
632 /* "Block" sizes in bytes the hardware uses for different device speeds.
633 * The logic in this part of the hardware limits the number of bits the hardware
634 * can use, so must represent bandwidth in a less precise manner to mimic what
635 * the scheduler hardware computes.
636 */
637 #define FS_BLOCK 1
638 #define HS_BLOCK 4
639 #define SS_BLOCK 16
640 #define DMI_BLOCK 32
641
642 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
643 * with each byte transferred. SuperSpeed devices have an initial overhead to
644 * set up bursts. These are in blocks, see above. LS overhead has already been
645 * translated into FS blocks.
646 */
647 #define DMI_OVERHEAD 8
648 #define DMI_OVERHEAD_BURST 4
649 #define SS_OVERHEAD 8
650 #define SS_OVERHEAD_BURST 32
651 #define HS_OVERHEAD 26
652 #define FS_OVERHEAD 20
653 #define LS_OVERHEAD 128
654 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
655 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
656 * of overhead associated with split transfers crossing microframe boundaries.
657 * 31 blocks is pure protocol overhead.
658 */
659 #define TT_HS_OVERHEAD (31 + 94)
660 #define TT_DMI_OVERHEAD (25 + 12)
661
662 /* Bandwidth limits in blocks */
663 #define FS_BW_LIMIT 1285
664 #define TT_BW_LIMIT 1320
665 #define HS_BW_LIMIT 1607
666 #define SS_BW_LIMIT_IN 3906
667 #define DMI_BW_LIMIT_IN 3906
668 #define SS_BW_LIMIT_OUT 3906
669 #define DMI_BW_LIMIT_OUT 3906
670
671 /* Percentage of bus bandwidth reserved for non-periodic transfers */
672 #define FS_BW_RESERVED 10
673 #define HS_BW_RESERVED 20
674 #define SS_BW_RESERVED 10
675
676 struct xhci_virt_ep {
677 struct xhci_virt_device *vdev; /* parent */
678 unsigned int ep_index;
679 struct xhci_ring *ring;
680 /* Related to endpoints that are configured to use stream IDs only */
681 struct xhci_stream_info *stream_info;
682 /* Temporary storage in case the configure endpoint command fails and we
683 * have to restore the device state to the previous state
684 */
685 struct xhci_ring *new_ring;
686 unsigned int err_count;
687 unsigned int ep_state;
688 #define SET_DEQ_PENDING (1 << 0)
689 #define EP_HALTED (1 << 1) /* For stall handling */
690 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
691 /* Transitioning the endpoint to using streams, don't enqueue URBs */
692 #define EP_GETTING_STREAMS (1 << 3)
693 #define EP_HAS_STREAMS (1 << 4)
694 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
695 #define EP_GETTING_NO_STREAMS (1 << 5)
696 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
697 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
698 /* usb_hub_clear_tt_buffer is in progress */
699 #define EP_CLEARING_TT (1 << 8)
700 /* ---- Related to URB cancellation ---- */
701 struct list_head cancelled_td_list;
702 struct xhci_hcd *xhci;
703 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
704 * command. We'll need to update the ring's dequeue segment and dequeue
705 * pointer after the command completes.
706 */
707 struct xhci_segment *queued_deq_seg;
708 union xhci_trb *queued_deq_ptr;
709 /*
710 * Sometimes the xHC can not process isochronous endpoint ring quickly
711 * enough, and it will miss some isoc tds on the ring and generate
712 * a Missed Service Error Event.
713 * Set skip flag when receive a Missed Service Error Event and
714 * process the missed tds on the endpoint ring.
715 */
716 bool skip;
717 /* Bandwidth checking storage */
718 struct xhci_bw_info bw_info;
719 struct list_head bw_endpoint_list;
720 unsigned long stop_time;
721 /* Isoch Frame ID checking storage */
722 int next_frame_id;
723 /* Use new Isoch TRB layout needed for extended TBC support */
724 bool use_extended_tbc;
725 };
726
727 enum xhci_overhead_type {
728 LS_OVERHEAD_TYPE = 0,
729 FS_OVERHEAD_TYPE,
730 HS_OVERHEAD_TYPE,
731 };
732
733 struct xhci_interval_bw {
734 unsigned int num_packets;
735 /* Sorted by max packet size.
736 * Head of the list is the greatest max packet size.
737 */
738 struct list_head endpoints;
739 /* How many endpoints of each speed are present. */
740 unsigned int overhead[3];
741 };
742
743 #define XHCI_MAX_INTERVAL 16
744
745 struct xhci_interval_bw_table {
746 unsigned int interval0_esit_payload;
747 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
748 /* Includes reserved bandwidth for async endpoints */
749 unsigned int bw_used;
750 unsigned int ss_bw_in;
751 unsigned int ss_bw_out;
752 };
753
754 #define EP_CTX_PER_DEV 31
755
756 struct xhci_virt_device {
757 int slot_id;
758 struct usb_device *udev;
759 /*
760 * Commands to the hardware are passed an "input context" that
761 * tells the hardware what to change in its data structures.
762 * The hardware will return changes in an "output context" that
763 * software must allocate for the hardware. We need to keep
764 * track of input and output contexts separately because
765 * these commands might fail and we don't trust the hardware.
766 */
767 struct xhci_container_ctx *out_ctx;
768 /* Used for addressing devices and configuration changes */
769 struct xhci_container_ctx *in_ctx;
770 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
771 u8 fake_port;
772 u8 real_port;
773 struct xhci_interval_bw_table *bw_table;
774 struct xhci_tt_bw_info *tt_info;
775 /*
776 * flags for state tracking based on events and issued commands.
777 * Software can not rely on states from output contexts because of
778 * latency between events and xHC updating output context values.
779 * See xhci 1.1 section 4.8.3 for more details
780 */
781 unsigned long flags;
782 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
783
784 /* The current max exit latency for the enabled USB3 link states. */
785 u16 current_mel;
786 /* Used for the debugfs interfaces. */
787 void *debugfs_private;
788 };
789
790 /*
791 * For each roothub, keep track of the bandwidth information for each periodic
792 * interval.
793 *
794 * If a high speed hub is attached to the roothub, each TT associated with that
795 * hub is a separate bandwidth domain. The interval information for the
796 * endpoints on the devices under that TT will appear in the TT structure.
797 */
798 struct xhci_root_port_bw_info {
799 struct list_head tts;
800 unsigned int num_active_tts;
801 struct xhci_interval_bw_table bw_table;
802 };
803
804 struct xhci_tt_bw_info {
805 struct list_head tt_list;
806 int slot_id;
807 int ttport;
808 struct xhci_interval_bw_table bw_table;
809 int active_eps;
810 };
811
812
813 /**
814 * struct xhci_device_context_array
815 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
816 */
817 struct xhci_device_context_array {
818 /* 64-bit device addresses; we only write 32-bit addresses */
819 __le64 dev_context_ptrs[MAX_HC_SLOTS];
820 /* private xHCD pointers */
821 dma_addr_t dma;
822 };
823 /* TODO: write function to set the 64-bit device DMA address */
824 /*
825 * TODO: change this to be dynamically sized at HC mem init time since the HC
826 * might not be able to handle the maximum number of devices possible.
827 */
828
829
830 struct xhci_transfer_event {
831 /* 64-bit buffer address, or immediate data */
832 __le64 buffer;
833 __le32 transfer_len;
834 /* This field is interpreted differently based on the type of TRB */
835 __le32 flags;
836 };
837
838 /* Transfer event TRB length bit mask */
839 /* bits 0:23 */
840 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
841
842 /** Transfer Event bit fields **/
843 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
844
845 /* Completion Code - only applicable for some types of TRBs */
846 #define COMP_CODE_MASK (0xff << 24)
847 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
848 #define COMP_INVALID 0
849 #define COMP_SUCCESS 1
850 #define COMP_DATA_BUFFER_ERROR 2
851 #define COMP_BABBLE_DETECTED_ERROR 3
852 #define COMP_USB_TRANSACTION_ERROR 4
853 #define COMP_TRB_ERROR 5
854 #define COMP_STALL_ERROR 6
855 #define COMP_RESOURCE_ERROR 7
856 #define COMP_BANDWIDTH_ERROR 8
857 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
858 #define COMP_INVALID_STREAM_TYPE_ERROR 10
859 #define COMP_SLOT_NOT_ENABLED_ERROR 11
860 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
861 #define COMP_SHORT_PACKET 13
862 #define COMP_RING_UNDERRUN 14
863 #define COMP_RING_OVERRUN 15
864 #define COMP_VF_EVENT_RING_FULL_ERROR 16
865 #define COMP_PARAMETER_ERROR 17
866 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
867 #define COMP_CONTEXT_STATE_ERROR 19
868 #define COMP_NO_PING_RESPONSE_ERROR 20
869 #define COMP_EVENT_RING_FULL_ERROR 21
870 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
871 #define COMP_MISSED_SERVICE_ERROR 23
872 #define COMP_COMMAND_RING_STOPPED 24
873 #define COMP_COMMAND_ABORTED 25
874 #define COMP_STOPPED 26
875 #define COMP_STOPPED_LENGTH_INVALID 27
876 #define COMP_STOPPED_SHORT_PACKET 28
877 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
878 #define COMP_ISOCH_BUFFER_OVERRUN 31
879 #define COMP_EVENT_LOST_ERROR 32
880 #define COMP_UNDEFINED_ERROR 33
881 #define COMP_INVALID_STREAM_ID_ERROR 34
882 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
883 #define COMP_SPLIT_TRANSACTION_ERROR 36
884
xhci_trb_comp_code_string(u8 status)885 static inline const char *xhci_trb_comp_code_string(u8 status)
886 {
887 switch (status) {
888 case COMP_INVALID:
889 return "Invalid";
890 case COMP_SUCCESS:
891 return "Success";
892 case COMP_DATA_BUFFER_ERROR:
893 return "Data Buffer Error";
894 case COMP_BABBLE_DETECTED_ERROR:
895 return "Babble Detected";
896 case COMP_USB_TRANSACTION_ERROR:
897 return "USB Transaction Error";
898 case COMP_TRB_ERROR:
899 return "TRB Error";
900 case COMP_STALL_ERROR:
901 return "Stall Error";
902 case COMP_RESOURCE_ERROR:
903 return "Resource Error";
904 case COMP_BANDWIDTH_ERROR:
905 return "Bandwidth Error";
906 case COMP_NO_SLOTS_AVAILABLE_ERROR:
907 return "No Slots Available Error";
908 case COMP_INVALID_STREAM_TYPE_ERROR:
909 return "Invalid Stream Type Error";
910 case COMP_SLOT_NOT_ENABLED_ERROR:
911 return "Slot Not Enabled Error";
912 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
913 return "Endpoint Not Enabled Error";
914 case COMP_SHORT_PACKET:
915 return "Short Packet";
916 case COMP_RING_UNDERRUN:
917 return "Ring Underrun";
918 case COMP_RING_OVERRUN:
919 return "Ring Overrun";
920 case COMP_VF_EVENT_RING_FULL_ERROR:
921 return "VF Event Ring Full Error";
922 case COMP_PARAMETER_ERROR:
923 return "Parameter Error";
924 case COMP_BANDWIDTH_OVERRUN_ERROR:
925 return "Bandwidth Overrun Error";
926 case COMP_CONTEXT_STATE_ERROR:
927 return "Context State Error";
928 case COMP_NO_PING_RESPONSE_ERROR:
929 return "No Ping Response Error";
930 case COMP_EVENT_RING_FULL_ERROR:
931 return "Event Ring Full Error";
932 case COMP_INCOMPATIBLE_DEVICE_ERROR:
933 return "Incompatible Device Error";
934 case COMP_MISSED_SERVICE_ERROR:
935 return "Missed Service Error";
936 case COMP_COMMAND_RING_STOPPED:
937 return "Command Ring Stopped";
938 case COMP_COMMAND_ABORTED:
939 return "Command Aborted";
940 case COMP_STOPPED:
941 return "Stopped";
942 case COMP_STOPPED_LENGTH_INVALID:
943 return "Stopped - Length Invalid";
944 case COMP_STOPPED_SHORT_PACKET:
945 return "Stopped - Short Packet";
946 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
947 return "Max Exit Latency Too Large Error";
948 case COMP_ISOCH_BUFFER_OVERRUN:
949 return "Isoch Buffer Overrun";
950 case COMP_EVENT_LOST_ERROR:
951 return "Event Lost Error";
952 case COMP_UNDEFINED_ERROR:
953 return "Undefined Error";
954 case COMP_INVALID_STREAM_ID_ERROR:
955 return "Invalid Stream ID Error";
956 case COMP_SECONDARY_BANDWIDTH_ERROR:
957 return "Secondary Bandwidth Error";
958 case COMP_SPLIT_TRANSACTION_ERROR:
959 return "Split Transaction Error";
960 default:
961 return "Unknown!!";
962 }
963 }
964
965 struct xhci_link_trb {
966 /* 64-bit segment pointer*/
967 __le64 segment_ptr;
968 __le32 intr_target;
969 __le32 control;
970 };
971
972 /* control bitfields */
973 #define LINK_TOGGLE (0x1<<1)
974
975 /* Command completion event TRB */
976 struct xhci_event_cmd {
977 /* Pointer to command TRB, or the value passed by the event data trb */
978 __le64 cmd_trb;
979 __le32 status;
980 __le32 flags;
981 };
982
983 /* flags bitmasks */
984
985 /* Address device - disable SetAddress */
986 #define TRB_BSR (1<<9)
987
988 /* Configure Endpoint - Deconfigure */
989 #define TRB_DC (1<<9)
990
991 /* Stop Ring - Transfer State Preserve */
992 #define TRB_TSP (1<<9)
993
994 enum xhci_ep_reset_type {
995 EP_HARD_RESET,
996 EP_SOFT_RESET,
997 };
998
999 /* Force Event */
1000 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1001 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1002
1003 /* Set Latency Tolerance Value */
1004 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1005
1006 /* Get Port Bandwidth */
1007 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1008
1009 /* Force Header */
1010 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1011 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1012
1013 enum xhci_setup_dev {
1014 SETUP_CONTEXT_ONLY,
1015 SETUP_CONTEXT_ADDRESS,
1016 };
1017
1018 /* bits 16:23 are the virtual function ID */
1019 /* bits 24:31 are the slot ID */
1020 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1021 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1022
1023 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1024 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1025 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1026
1027 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1028 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1029 #define LAST_EP_INDEX 30
1030
1031 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1032 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1033 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1034 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1)
1035
1036 /* Link TRB specific fields */
1037 #define TRB_TC (1<<1)
1038
1039 /* Port Status Change Event TRB fields */
1040 /* Port ID - bits 31:24 */
1041 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1042
1043 #define EVENT_DATA (1 << 2)
1044
1045 /* Normal TRB fields */
1046 /* transfer_len bitmasks - bits 0:16 */
1047 #define TRB_LEN(p) ((p) & 0x1ffff)
1048 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1049 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1050 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1051 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1052 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1053 /* Interrupter Target - which MSI-X vector to target the completion event at */
1054 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1055 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1056 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1057 #define TRB_TBC(p) (((p) & 0x3) << 7)
1058 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1059
1060 /* Cycle bit - indicates TRB ownership by HC or HCD */
1061 #define TRB_CYCLE (1<<0)
1062 /*
1063 * Force next event data TRB to be evaluated before task switch.
1064 * Used to pass OS data back after a TD completes.
1065 */
1066 #define TRB_ENT (1<<1)
1067 /* Interrupt on short packet */
1068 #define TRB_ISP (1<<2)
1069 /* Set PCIe no snoop attribute */
1070 #define TRB_NO_SNOOP (1<<3)
1071 /* Chain multiple TRBs into a TD */
1072 #define TRB_CHAIN (1<<4)
1073 /* Interrupt on completion */
1074 #define TRB_IOC (1<<5)
1075 /* The buffer pointer contains immediate data */
1076 #define TRB_IDT (1<<6)
1077 /* TDs smaller than this might use IDT */
1078 #define TRB_IDT_MAX_SIZE 8
1079
1080 /* Block Event Interrupt */
1081 #define TRB_BEI (1<<9)
1082
1083 /* Control transfer TRB specific fields */
1084 #define TRB_DIR_IN (1<<16)
1085 #define TRB_TX_TYPE(p) ((p) << 16)
1086 #define TRB_DATA_OUT 2
1087 #define TRB_DATA_IN 3
1088
1089 /* Isochronous TRB specific fields */
1090 #define TRB_SIA (1<<31)
1091 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1092
1093 /* TRB cache size for xHC with TRB cache */
1094 #define TRB_CACHE_SIZE_HS 8
1095 #define TRB_CACHE_SIZE_SS 16
1096
1097 struct xhci_generic_trb {
1098 __le32 field[4];
1099 };
1100
1101 union xhci_trb {
1102 struct xhci_link_trb link;
1103 struct xhci_transfer_event trans_event;
1104 struct xhci_event_cmd event_cmd;
1105 struct xhci_generic_trb generic;
1106 };
1107
1108 /* TRB bit mask */
1109 #define TRB_TYPE_BITMASK (0xfc00)
1110 #define TRB_TYPE(p) ((p) << 10)
1111 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1112 /* TRB type IDs */
1113 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1114 #define TRB_NORMAL 1
1115 /* setup stage for control transfers */
1116 #define TRB_SETUP 2
1117 /* data stage for control transfers */
1118 #define TRB_DATA 3
1119 /* status stage for control transfers */
1120 #define TRB_STATUS 4
1121 /* isoc transfers */
1122 #define TRB_ISOC 5
1123 /* TRB for linking ring segments */
1124 #define TRB_LINK 6
1125 #define TRB_EVENT_DATA 7
1126 /* Transfer Ring No-op (not for the command ring) */
1127 #define TRB_TR_NOOP 8
1128 /* Command TRBs */
1129 /* Enable Slot Command */
1130 #define TRB_ENABLE_SLOT 9
1131 /* Disable Slot Command */
1132 #define TRB_DISABLE_SLOT 10
1133 /* Address Device Command */
1134 #define TRB_ADDR_DEV 11
1135 /* Configure Endpoint Command */
1136 #define TRB_CONFIG_EP 12
1137 /* Evaluate Context Command */
1138 #define TRB_EVAL_CONTEXT 13
1139 /* Reset Endpoint Command */
1140 #define TRB_RESET_EP 14
1141 /* Stop Transfer Ring Command */
1142 #define TRB_STOP_RING 15
1143 /* Set Transfer Ring Dequeue Pointer Command */
1144 #define TRB_SET_DEQ 16
1145 /* Reset Device Command */
1146 #define TRB_RESET_DEV 17
1147 /* Force Event Command (opt) */
1148 #define TRB_FORCE_EVENT 18
1149 /* Negotiate Bandwidth Command (opt) */
1150 #define TRB_NEG_BANDWIDTH 19
1151 /* Set Latency Tolerance Value Command (opt) */
1152 #define TRB_SET_LT 20
1153 /* Get port bandwidth Command */
1154 #define TRB_GET_BW 21
1155 /* Force Header Command - generate a transaction or link management packet */
1156 #define TRB_FORCE_HEADER 22
1157 /* No-op Command - not for transfer rings */
1158 #define TRB_CMD_NOOP 23
1159 /* TRB IDs 24-31 reserved */
1160 /* Event TRBS */
1161 /* Transfer Event */
1162 #define TRB_TRANSFER 32
1163 /* Command Completion Event */
1164 #define TRB_COMPLETION 33
1165 /* Port Status Change Event */
1166 #define TRB_PORT_STATUS 34
1167 /* Bandwidth Request Event (opt) */
1168 #define TRB_BANDWIDTH_EVENT 35
1169 /* Doorbell Event (opt) */
1170 #define TRB_DOORBELL 36
1171 /* Host Controller Event */
1172 #define TRB_HC_EVENT 37
1173 /* Device Notification Event - device sent function wake notification */
1174 #define TRB_DEV_NOTE 38
1175 /* MFINDEX Wrap Event - microframe counter wrapped */
1176 #define TRB_MFINDEX_WRAP 39
1177 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1178 #define TRB_VENDOR_DEFINED_LOW 48
1179 /* Nec vendor-specific command completion event. */
1180 #define TRB_NEC_CMD_COMP 48
1181 /* Get NEC firmware revision. */
1182 #define TRB_NEC_GET_FW 49
1183
xhci_trb_type_string(u8 type)1184 static inline const char *xhci_trb_type_string(u8 type)
1185 {
1186 switch (type) {
1187 case TRB_NORMAL:
1188 return "Normal";
1189 case TRB_SETUP:
1190 return "Setup Stage";
1191 case TRB_DATA:
1192 return "Data Stage";
1193 case TRB_STATUS:
1194 return "Status Stage";
1195 case TRB_ISOC:
1196 return "Isoch";
1197 case TRB_LINK:
1198 return "Link";
1199 case TRB_EVENT_DATA:
1200 return "Event Data";
1201 case TRB_TR_NOOP:
1202 return "No-Op";
1203 case TRB_ENABLE_SLOT:
1204 return "Enable Slot Command";
1205 case TRB_DISABLE_SLOT:
1206 return "Disable Slot Command";
1207 case TRB_ADDR_DEV:
1208 return "Address Device Command";
1209 case TRB_CONFIG_EP:
1210 return "Configure Endpoint Command";
1211 case TRB_EVAL_CONTEXT:
1212 return "Evaluate Context Command";
1213 case TRB_RESET_EP:
1214 return "Reset Endpoint Command";
1215 case TRB_STOP_RING:
1216 return "Stop Ring Command";
1217 case TRB_SET_DEQ:
1218 return "Set TR Dequeue Pointer Command";
1219 case TRB_RESET_DEV:
1220 return "Reset Device Command";
1221 case TRB_FORCE_EVENT:
1222 return "Force Event Command";
1223 case TRB_NEG_BANDWIDTH:
1224 return "Negotiate Bandwidth Command";
1225 case TRB_SET_LT:
1226 return "Set Latency Tolerance Value Command";
1227 case TRB_GET_BW:
1228 return "Get Port Bandwidth Command";
1229 case TRB_FORCE_HEADER:
1230 return "Force Header Command";
1231 case TRB_CMD_NOOP:
1232 return "No-Op Command";
1233 case TRB_TRANSFER:
1234 return "Transfer Event";
1235 case TRB_COMPLETION:
1236 return "Command Completion Event";
1237 case TRB_PORT_STATUS:
1238 return "Port Status Change Event";
1239 case TRB_BANDWIDTH_EVENT:
1240 return "Bandwidth Request Event";
1241 case TRB_DOORBELL:
1242 return "Doorbell Event";
1243 case TRB_HC_EVENT:
1244 return "Host Controller Event";
1245 case TRB_DEV_NOTE:
1246 return "Device Notification Event";
1247 case TRB_MFINDEX_WRAP:
1248 return "MFINDEX Wrap Event";
1249 case TRB_NEC_CMD_COMP:
1250 return "NEC Command Completion Event";
1251 case TRB_NEC_GET_FW:
1252 return "NET Get Firmware Revision Command";
1253 default:
1254 return "UNKNOWN";
1255 }
1256 }
1257
1258 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1259 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1260 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1261 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1262 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1263 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1264
1265 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1266 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1267
1268 /*
1269 * TRBS_PER_SEGMENT must be a multiple of 4,
1270 * since the command ring is 64-byte aligned.
1271 * It must also be greater than 16.
1272 */
1273 #define TRBS_PER_SEGMENT 256
1274 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1275 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1276 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1277 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1278 /* TRB buffer pointers can't cross 64KB boundaries */
1279 #define TRB_MAX_BUFF_SHIFT 16
1280 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1281 /* How much data is left before the 64KB boundary? */
1282 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1283 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1284 #define MAX_SOFT_RETRY 3
1285 /*
1286 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1287 * XHCI_AVOID_BEI quirk is in use.
1288 */
1289 #define AVOID_BEI_INTERVAL_MIN 8
1290 #define AVOID_BEI_INTERVAL_MAX 32
1291
1292 struct xhci_segment {
1293 union xhci_trb *trbs;
1294 /* private to HCD */
1295 struct xhci_segment *next;
1296 unsigned int num;
1297 dma_addr_t dma;
1298 /* Max packet sized bounce buffer for td-fragmant alignment */
1299 dma_addr_t bounce_dma;
1300 void *bounce_buf;
1301 unsigned int bounce_offs;
1302 unsigned int bounce_len;
1303 };
1304
1305 enum xhci_cancelled_td_status {
1306 TD_DIRTY = 0,
1307 TD_HALTED,
1308 TD_CLEARING_CACHE,
1309 TD_CLEARING_CACHE_DEFERRED,
1310 TD_CLEARED,
1311 };
1312
1313 struct xhci_td {
1314 struct list_head td_list;
1315 struct list_head cancelled_td_list;
1316 int status;
1317 enum xhci_cancelled_td_status cancel_status;
1318 struct urb *urb;
1319 struct xhci_segment *start_seg;
1320 union xhci_trb *first_trb;
1321 union xhci_trb *last_trb;
1322 struct xhci_segment *last_trb_seg;
1323 struct xhci_segment *bounce_seg;
1324 /* actual_length of the URB has already been set */
1325 bool urb_length_set;
1326 bool error_mid_td;
1327 unsigned int num_trbs;
1328 };
1329
1330 /*
1331 * xHCI command default timeout value in milliseconds.
1332 * USB 3.2 spec, section 9.2.6.1
1333 */
1334 #define XHCI_CMD_DEFAULT_TIMEOUT 5000
1335
1336 /* command descriptor */
1337 struct xhci_cd {
1338 struct xhci_command *command;
1339 union xhci_trb *cmd_trb;
1340 };
1341
1342 enum xhci_ring_type {
1343 TYPE_CTRL = 0,
1344 TYPE_ISOC,
1345 TYPE_BULK,
1346 TYPE_INTR,
1347 TYPE_STREAM,
1348 TYPE_COMMAND,
1349 TYPE_EVENT,
1350 };
1351
xhci_ring_type_string(enum xhci_ring_type type)1352 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1353 {
1354 switch (type) {
1355 case TYPE_CTRL:
1356 return "CTRL";
1357 case TYPE_ISOC:
1358 return "ISOC";
1359 case TYPE_BULK:
1360 return "BULK";
1361 case TYPE_INTR:
1362 return "INTR";
1363 case TYPE_STREAM:
1364 return "STREAM";
1365 case TYPE_COMMAND:
1366 return "CMD";
1367 case TYPE_EVENT:
1368 return "EVENT";
1369 }
1370
1371 return "UNKNOWN";
1372 }
1373
1374 struct xhci_ring {
1375 struct xhci_segment *first_seg;
1376 struct xhci_segment *last_seg;
1377 union xhci_trb *enqueue;
1378 struct xhci_segment *enq_seg;
1379 union xhci_trb *dequeue;
1380 struct xhci_segment *deq_seg;
1381 struct list_head td_list;
1382 /*
1383 * Write the cycle state into the TRB cycle field to give ownership of
1384 * the TRB to the host controller (if we are the producer), or to check
1385 * if we own the TRB (if we are the consumer). See section 4.9.1.
1386 */
1387 u32 cycle_state;
1388 unsigned int stream_id;
1389 unsigned int num_segs;
1390 unsigned int num_trbs_free; /* used only by xhci DbC */
1391 unsigned int bounce_buf_len;
1392 enum xhci_ring_type type;
1393 bool last_td_was_short;
1394 struct radix_tree_root *trb_address_map;
1395 };
1396
1397 struct xhci_erst_entry {
1398 /* 64-bit event ring segment address */
1399 __le64 seg_addr;
1400 __le32 seg_size;
1401 /* Set to zero */
1402 __le32 rsvd;
1403 };
1404
1405 struct xhci_erst {
1406 struct xhci_erst_entry *entries;
1407 unsigned int num_entries;
1408 /* xhci->event_ring keeps track of segment dma addresses */
1409 dma_addr_t erst_dma_addr;
1410 /* Num entries the ERST can contain */
1411 unsigned int erst_size;
1412 };
1413
1414 struct xhci_scratchpad {
1415 u64 *sp_array;
1416 dma_addr_t sp_dma;
1417 void **sp_buffers;
1418 };
1419
1420 struct urb_priv {
1421 int num_tds;
1422 int num_tds_done;
1423 struct xhci_td td[];
1424 };
1425
1426 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */
1427 #define ERST_DEFAULT_SEGS 2
1428 /* Poll every 60 seconds */
1429 #define POLL_TIMEOUT 60
1430 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1431 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1432 /* XXX: Make these module parameters */
1433
1434 struct s3_save {
1435 u32 command;
1436 u32 dev_nt;
1437 u64 dcbaa_ptr;
1438 u32 config_reg;
1439 };
1440
1441 /* Use for lpm */
1442 struct dev_info {
1443 u32 dev_id;
1444 struct list_head list;
1445 };
1446
1447 struct xhci_bus_state {
1448 unsigned long bus_suspended;
1449 unsigned long next_statechange;
1450
1451 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1452 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1453 u32 port_c_suspend;
1454 u32 suspended_ports;
1455 u32 port_remote_wakeup;
1456 /* which ports have started to resume */
1457 unsigned long resuming_ports;
1458 };
1459
1460 struct xhci_interrupter {
1461 struct xhci_ring *event_ring;
1462 struct xhci_erst erst;
1463 struct xhci_intr_reg __iomem *ir_set;
1464 unsigned int intr_num;
1465 /* For interrupter registers save and restore over suspend/resume */
1466 u32 s3_irq_pending;
1467 u32 s3_irq_control;
1468 u32 s3_erst_size;
1469 u64 s3_erst_base;
1470 u64 s3_erst_dequeue;
1471 };
1472 /*
1473 * It can take up to 20 ms to transition from RExit to U0 on the
1474 * Intel Lynx Point LP xHCI host.
1475 */
1476 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1477 struct xhci_port_cap {
1478 u32 *psi; /* array of protocol speed ID entries */
1479 u8 psi_count;
1480 u8 psi_uid_count;
1481 u8 maj_rev;
1482 u8 min_rev;
1483 };
1484
1485 struct xhci_port {
1486 __le32 __iomem *addr;
1487 int hw_portnum;
1488 int hcd_portnum;
1489 struct xhci_hub *rhub;
1490 struct xhci_port_cap *port_cap;
1491 unsigned int lpm_incapable:1;
1492 unsigned long resume_timestamp;
1493 bool rexit_active;
1494 struct completion rexit_done;
1495 struct completion u3exit_done;
1496 };
1497
1498 struct xhci_hub {
1499 struct xhci_port **ports;
1500 unsigned int num_ports;
1501 struct usb_hcd *hcd;
1502 /* keep track of bus suspend info */
1503 struct xhci_bus_state bus_state;
1504 /* supported prococol extended capabiliy values */
1505 u8 maj_rev;
1506 u8 min_rev;
1507 };
1508
1509 /* There is one xhci_hcd structure per controller */
1510 struct xhci_hcd {
1511 struct usb_hcd *main_hcd;
1512 struct usb_hcd *shared_hcd;
1513 /* glue to PCI and HCD framework */
1514 struct xhci_cap_regs __iomem *cap_regs;
1515 struct xhci_op_regs __iomem *op_regs;
1516 struct xhci_run_regs __iomem *run_regs;
1517 struct xhci_doorbell_array __iomem *dba;
1518
1519 /* Cached register copies of read-only HC data */
1520 __u32 hcs_params1;
1521 __u32 hcs_params2;
1522 __u32 hcs_params3;
1523 __u32 hcc_params;
1524 __u32 hcc_params2;
1525
1526 spinlock_t lock;
1527
1528 /* packed release number */
1529 u8 sbrn;
1530 u16 hci_version;
1531 u8 max_slots;
1532 u16 max_interrupters;
1533 u8 max_ports;
1534 u8 isoc_threshold;
1535 /* imod_interval in ns (I * 250ns) */
1536 u32 imod_interval;
1537 u32 isoc_bei_interval;
1538 int event_ring_max;
1539 /* 4KB min, 128MB max */
1540 int page_size;
1541 /* Valid values are 12 to 20, inclusive */
1542 int page_shift;
1543 /* msi-x vectors */
1544 int msix_count;
1545 /* optional clocks */
1546 struct clk *clk;
1547 struct clk *reg_clk;
1548 /* optional reset controller */
1549 struct reset_control *reset;
1550 /* data structures */
1551 struct xhci_device_context_array *dcbaa;
1552 struct xhci_interrupter **interrupters;
1553 struct xhci_ring *cmd_ring;
1554 unsigned int cmd_ring_state;
1555 #define CMD_RING_STATE_RUNNING (1 << 0)
1556 #define CMD_RING_STATE_ABORTED (1 << 1)
1557 #define CMD_RING_STATE_STOPPED (1 << 2)
1558 struct list_head cmd_list;
1559 unsigned int cmd_ring_reserved_trbs;
1560 struct delayed_work cmd_timer;
1561 struct completion cmd_ring_stop_completion;
1562 struct xhci_command *current_cmd;
1563
1564 /* Scratchpad */
1565 struct xhci_scratchpad *scratchpad;
1566
1567 /* slot enabling and address device helpers */
1568 /* these are not thread safe so use mutex */
1569 struct mutex mutex;
1570 /* Internal mirror of the HW's dcbaa */
1571 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1572 /* For keeping track of bandwidth domains per roothub. */
1573 struct xhci_root_port_bw_info *rh_bw;
1574
1575 /* DMA pools */
1576 struct dma_pool *device_pool;
1577 struct dma_pool *segment_pool;
1578 struct dma_pool *small_streams_pool;
1579 struct dma_pool *medium_streams_pool;
1580
1581 /* Host controller watchdog timer structures */
1582 unsigned int xhc_state;
1583 unsigned long run_graceperiod;
1584 struct s3_save s3;
1585 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1586 *
1587 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1588 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1589 * that sees this status (other than the timer that set it) should stop touching
1590 * hardware immediately. Interrupt handlers should return immediately when
1591 * they see this status (any time they drop and re-acquire xhci->lock).
1592 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1593 * putting the TD on the canceled list, etc.
1594 *
1595 * There are no reports of xHCI host controllers that display this issue.
1596 */
1597 #define XHCI_STATE_DYING (1 << 0)
1598 #define XHCI_STATE_HALTED (1 << 1)
1599 #define XHCI_STATE_REMOVING (1 << 2)
1600 unsigned long long quirks;
1601 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1602 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1603 #define XHCI_NEC_HOST BIT_ULL(2)
1604 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1605 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1606 /*
1607 * Certain Intel host controllers have a limit to the number of endpoint
1608 * contexts they can handle. Ideally, they would signal that they can't handle
1609 * anymore endpoint contexts by returning a Resource Error for the Configure
1610 * Endpoint command, but they don't. Instead they expect software to keep track
1611 * of the number of active endpoints for them, across configure endpoint
1612 * commands, reset device commands, disable slot commands, and address device
1613 * commands.
1614 */
1615 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1616 #define XHCI_BROKEN_MSI BIT_ULL(6)
1617 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1618 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1619 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1620 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */
1621 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1622 #define XHCI_INTEL_HOST BIT_ULL(12)
1623 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1624 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1625 #define XHCI_AVOID_BEI BIT_ULL(15)
1626 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1627 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1628 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1629 /* For controllers with a broken beyond repair streams implementation */
1630 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1631 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1632 #define XHCI_MTK_HOST BIT_ULL(21)
1633 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1634 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1635 #define XHCI_MISSING_CAS BIT_ULL(24)
1636 /* For controller with a broken Port Disable implementation */
1637 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1638 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1639 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1640 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1641 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1642 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1643 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1644 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1645 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1646 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1647 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1648 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1649 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1650 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1651 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1652 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1653 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1654 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1655 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1656 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1657 #define XHCI_TRB_OVERFETCH BIT_ULL(45)
1658 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1659 #define XHCI_WRITE_64_HI_LO BIT_ULL(47)
1660 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
1661 #define XHCI_ETRON_HOST BIT_ULL(49)
1662 #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50)
1663
1664 unsigned int num_active_eps;
1665 unsigned int limit_active_eps;
1666 struct xhci_port *hw_ports;
1667 struct xhci_hub usb2_rhub;
1668 struct xhci_hub usb3_rhub;
1669 /* support xHCI 1.0 spec USB2 hardware LPM */
1670 unsigned hw_lpm_support:1;
1671 /* Broken Suspend flag for SNPS Suspend resume issue */
1672 unsigned broken_suspend:1;
1673 /* Indicates that omitting hcd is supported if root hub has no ports */
1674 unsigned allow_single_roothub:1;
1675 /* cached usb2 extened protocol capabilites */
1676 u32 *ext_caps;
1677 unsigned int num_ext_caps;
1678 /* cached extended protocol port capabilities */
1679 struct xhci_port_cap *port_caps;
1680 unsigned int num_port_caps;
1681 /* Compliance Mode Recovery Data */
1682 struct timer_list comp_mode_recovery_timer;
1683 u32 port_status_u0;
1684 u16 test_mode;
1685 /* Compliance Mode Timer Triggered every 2 seconds */
1686 #define COMP_MODE_RCVRY_MSECS 2000
1687
1688 struct dentry *debugfs_root;
1689 struct dentry *debugfs_slots;
1690 struct list_head regset_list;
1691
1692 void *dbc;
1693 /* platform-specific data -- must come last */
1694 unsigned long priv[] __aligned(sizeof(s64));
1695 };
1696
1697 /* Platform specific overrides to generic XHCI hc_driver ops */
1698 struct xhci_driver_overrides {
1699 size_t extra_priv_size;
1700 int (*reset)(struct usb_hcd *hcd);
1701 int (*start)(struct usb_hcd *hcd);
1702 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1703 struct usb_host_endpoint *ep);
1704 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1705 struct usb_host_endpoint *ep);
1706 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1707 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1708 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1709 struct usb_tt *tt, gfp_t mem_flags);
1710 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1711 u16 wIndex, char *buf, u16 wLength);
1712 };
1713
1714 #define XHCI_CFC_DELAY 10
1715
1716 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1717 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1718 {
1719 struct usb_hcd *primary_hcd;
1720
1721 if (usb_hcd_is_primary_hcd(hcd))
1722 primary_hcd = hcd;
1723 else
1724 primary_hcd = hcd->primary_hcd;
1725
1726 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1727 }
1728
xhci_to_hcd(struct xhci_hcd * xhci)1729 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1730 {
1731 return xhci->main_hcd;
1732 }
1733
xhci_get_usb3_hcd(struct xhci_hcd * xhci)1734 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1735 {
1736 if (xhci->shared_hcd)
1737 return xhci->shared_hcd;
1738
1739 if (!xhci->usb2_rhub.num_ports)
1740 return xhci->main_hcd;
1741
1742 return NULL;
1743 }
1744
xhci_hcd_is_usb3(struct usb_hcd * hcd)1745 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1746 {
1747 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1748
1749 return hcd == xhci_get_usb3_hcd(xhci);
1750 }
1751
xhci_has_one_roothub(struct xhci_hcd * xhci)1752 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1753 {
1754 return xhci->allow_single_roothub &&
1755 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1756 }
1757
1758 #define xhci_dbg(xhci, fmt, args...) \
1759 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1760 #define xhci_err(xhci, fmt, args...) \
1761 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1762 #define xhci_warn(xhci, fmt, args...) \
1763 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1764 #define xhci_info(xhci, fmt, args...) \
1765 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1766
1767 /*
1768 * Registers should always be accessed with double word or quad word accesses.
1769 *
1770 * Some xHCI implementations may support 64-bit address pointers. Registers
1771 * with 64-bit address pointers should be written to with dword accesses by
1772 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1773 * xHCI implementations that do not support 64-bit address pointers will ignore
1774 * the high dword, and write order is irrelevant.
1775 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)1776 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1777 __le64 __iomem *regs)
1778 {
1779 return lo_hi_readq(regs);
1780 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)1781 static inline void xhci_write_64(struct xhci_hcd *xhci,
1782 const u64 val, __le64 __iomem *regs)
1783 {
1784 lo_hi_writeq(val, regs);
1785 }
1786
xhci_link_trb_quirk(struct xhci_hcd * xhci)1787 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1788 {
1789 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1790 }
1791
1792 /* xHCI debugging */
1793 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1794 struct xhci_container_ctx *ctx);
1795 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1796 const char *fmt, ...);
1797
1798 /* xHCI memory management */
1799 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1800 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1801 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1802 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1803 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1804 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1805 struct usb_device *udev);
1806 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1807 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1808 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1809 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1810 struct xhci_virt_device *virt_dev,
1811 int old_active_eps);
1812 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1813 void xhci_update_bw_info(struct xhci_hcd *xhci,
1814 struct xhci_container_ctx *in_ctx,
1815 struct xhci_input_control_ctx *ctrl_ctx,
1816 struct xhci_virt_device *virt_dev);
1817 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1818 struct xhci_container_ctx *in_ctx,
1819 struct xhci_container_ctx *out_ctx,
1820 unsigned int ep_index);
1821 void xhci_slot_copy(struct xhci_hcd *xhci,
1822 struct xhci_container_ctx *in_ctx,
1823 struct xhci_container_ctx *out_ctx);
1824 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1825 struct usb_device *udev, struct usb_host_endpoint *ep,
1826 gfp_t mem_flags);
1827 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1828 unsigned int num_segs, unsigned int cycle_state,
1829 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1830 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1831 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1832 unsigned int num_trbs, gfp_t flags);
1833 int xhci_alloc_erst(struct xhci_hcd *xhci,
1834 struct xhci_ring *evt_ring,
1835 struct xhci_erst *erst,
1836 gfp_t flags);
1837 void xhci_initialize_ring_info(struct xhci_ring *ring,
1838 unsigned int cycle_state);
1839 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1840 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1841 struct xhci_virt_device *virt_dev,
1842 unsigned int ep_index);
1843 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1844 unsigned int num_stream_ctxs,
1845 unsigned int num_streams,
1846 unsigned int max_packet, gfp_t flags);
1847 void xhci_free_stream_info(struct xhci_hcd *xhci,
1848 struct xhci_stream_info *stream_info);
1849 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1850 struct xhci_ep_ctx *ep_ctx,
1851 struct xhci_stream_info *stream_info);
1852 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1853 struct xhci_virt_ep *ep);
1854 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1855 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1856 struct xhci_ring *xhci_dma_to_transfer_ring(
1857 struct xhci_virt_ep *ep,
1858 u64 address);
1859 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1860 bool allocate_completion, gfp_t mem_flags);
1861 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1862 bool allocate_completion, gfp_t mem_flags);
1863 void xhci_urb_free_priv(struct urb_priv *urb_priv);
1864 void xhci_free_command(struct xhci_hcd *xhci,
1865 struct xhci_command *command);
1866 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1867 int type, gfp_t flags);
1868 void xhci_free_container_ctx(struct xhci_hcd *xhci,
1869 struct xhci_container_ctx *ctx);
1870 struct xhci_interrupter *
1871 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs,
1872 u32 imod_interval);
1873 void xhci_remove_secondary_interrupter(struct usb_hcd
1874 *hcd, struct xhci_interrupter *ir);
1875
1876 /* xHCI host controller glue */
1877 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1878 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
1879 void xhci_quiesce(struct xhci_hcd *xhci);
1880 int xhci_halt(struct xhci_hcd *xhci);
1881 int xhci_start(struct xhci_hcd *xhci);
1882 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1883 int xhci_run(struct usb_hcd *hcd);
1884 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1885 void xhci_shutdown(struct usb_hcd *hcd);
1886 void xhci_stop(struct usb_hcd *hcd);
1887 void xhci_init_driver(struct hc_driver *drv,
1888 const struct xhci_driver_overrides *over);
1889 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1890 struct usb_host_endpoint *ep);
1891 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1892 struct usb_host_endpoint *ep);
1893 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1894 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1895 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1896 struct usb_tt *tt, gfp_t mem_flags);
1897 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1898 int xhci_ext_cap_init(struct xhci_hcd *xhci);
1899
1900 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1901 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1902
1903 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1904 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1905 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1906 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1907 struct xhci_virt_device *virt_dev,
1908 struct usb_device *hdev,
1909 struct usb_tt *tt, gfp_t mem_flags);
1910 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
1911 u32 imod_interval);
1912 int xhci_enable_interrupter(struct xhci_interrupter *ir);
1913 int xhci_disable_interrupter(struct xhci_interrupter *ir);
1914
1915 /* xHCI ring, segment, TRB, and TD functions */
1916 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1917 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1918 struct xhci_segment *start_seg, union xhci_trb *start_trb,
1919 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1920 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1921 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1922 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1923 u32 trb_type, u32 slot_id);
1924 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1925 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1926 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1927 u32 field1, u32 field2, u32 field3, u32 field4);
1928 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1929 int slot_id, unsigned int ep_index, int suspend);
1930 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1931 int slot_id, unsigned int ep_index);
1932 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1933 int slot_id, unsigned int ep_index);
1934 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1935 int slot_id, unsigned int ep_index);
1936 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1937 struct urb *urb, int slot_id, unsigned int ep_index);
1938 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1939 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1940 bool command_must_succeed);
1941 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1942 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1943 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1944 int slot_id, unsigned int ep_index,
1945 enum xhci_ep_reset_type reset_type);
1946 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1947 u32 slot_id);
1948 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
1949 unsigned int ep_index, unsigned int stream_id,
1950 struct xhci_td *td);
1951 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
1952 void xhci_handle_command_timeout(struct work_struct *work);
1953
1954 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1955 unsigned int ep_index, unsigned int stream_id);
1956 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1957 unsigned int slot_id,
1958 unsigned int ep_index);
1959 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1960 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1961 unsigned int count_trbs(u64 addr, u64 len);
1962 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep);
1963
1964 /* xHCI roothub code */
1965 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1966 u32 link_state);
1967 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1968 u32 port_bit);
1969 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1970 char *buf, u16 wLength);
1971 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1972 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1973 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
1974
1975 void xhci_hc_died(struct xhci_hcd *xhci);
1976
1977 #ifdef CONFIG_PM
1978 int xhci_bus_suspend(struct usb_hcd *hcd);
1979 int xhci_bus_resume(struct usb_hcd *hcd);
1980 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
1981 #else
1982 #define xhci_bus_suspend NULL
1983 #define xhci_bus_resume NULL
1984 #define xhci_get_resuming_ports NULL
1985 #endif /* CONFIG_PM */
1986
1987 u32 xhci_port_state_to_neutral(u32 state);
1988 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1989 u16 port);
1990 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1991
1992 /* xHCI contexts */
1993 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1994 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1995 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1996
1997 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1998 unsigned int slot_id, unsigned int ep_index,
1999 unsigned int stream_id);
2000
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)2001 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2002 struct urb *urb)
2003 {
2004 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2005 xhci_get_endpoint_index(&urb->ep->desc),
2006 urb->stream_id);
2007 }
2008
2009 /*
2010 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2011 * them anyways as we where unable to find a device that matches the
2012 * constraints.
2013 */
xhci_urb_suitable_for_idt(struct urb * urb)2014 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2015 {
2016 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2017 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2018 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2019 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2020 !urb->num_sgs)
2021 return true;
2022
2023 return false;
2024 }
2025
xhci_slot_state_string(u32 state)2026 static inline char *xhci_slot_state_string(u32 state)
2027 {
2028 switch (state) {
2029 case SLOT_STATE_ENABLED:
2030 return "enabled/disabled";
2031 case SLOT_STATE_DEFAULT:
2032 return "default";
2033 case SLOT_STATE_ADDRESSED:
2034 return "addressed";
2035 case SLOT_STATE_CONFIGURED:
2036 return "configured";
2037 default:
2038 return "reserved";
2039 }
2040 }
2041
xhci_decode_trb(char * str,size_t size,u32 field0,u32 field1,u32 field2,u32 field3)2042 static inline const char *xhci_decode_trb(char *str, size_t size,
2043 u32 field0, u32 field1, u32 field2, u32 field3)
2044 {
2045 int type = TRB_FIELD_TO_TYPE(field3);
2046
2047 switch (type) {
2048 case TRB_LINK:
2049 snprintf(str, size,
2050 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2051 field1, field0, GET_INTR_TARGET(field2),
2052 xhci_trb_type_string(type),
2053 field3 & TRB_IOC ? 'I' : 'i',
2054 field3 & TRB_CHAIN ? 'C' : 'c',
2055 field3 & TRB_TC ? 'T' : 't',
2056 field3 & TRB_CYCLE ? 'C' : 'c');
2057 break;
2058 case TRB_TRANSFER:
2059 case TRB_COMPLETION:
2060 case TRB_PORT_STATUS:
2061 case TRB_BANDWIDTH_EVENT:
2062 case TRB_DOORBELL:
2063 case TRB_HC_EVENT:
2064 case TRB_DEV_NOTE:
2065 case TRB_MFINDEX_WRAP:
2066 snprintf(str, size,
2067 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2068 field1, field0,
2069 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2070 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2071 /* Macro decrements 1, maybe it shouldn't?!? */
2072 TRB_TO_EP_INDEX(field3) + 1,
2073 xhci_trb_type_string(type),
2074 field3 & EVENT_DATA ? 'E' : 'e',
2075 field3 & TRB_CYCLE ? 'C' : 'c');
2076
2077 break;
2078 case TRB_SETUP:
2079 snprintf(str, size,
2080 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2081 field0 & 0xff,
2082 (field0 & 0xff00) >> 8,
2083 (field0 & 0xff000000) >> 24,
2084 (field0 & 0xff0000) >> 16,
2085 (field1 & 0xff00) >> 8,
2086 field1 & 0xff,
2087 (field1 & 0xff000000) >> 16 |
2088 (field1 & 0xff0000) >> 16,
2089 TRB_LEN(field2), GET_TD_SIZE(field2),
2090 GET_INTR_TARGET(field2),
2091 xhci_trb_type_string(type),
2092 field3 & TRB_IDT ? 'I' : 'i',
2093 field3 & TRB_IOC ? 'I' : 'i',
2094 field3 & TRB_CYCLE ? 'C' : 'c');
2095 break;
2096 case TRB_DATA:
2097 snprintf(str, size,
2098 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2099 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2100 GET_INTR_TARGET(field2),
2101 xhci_trb_type_string(type),
2102 field3 & TRB_IDT ? 'I' : 'i',
2103 field3 & TRB_IOC ? 'I' : 'i',
2104 field3 & TRB_CHAIN ? 'C' : 'c',
2105 field3 & TRB_NO_SNOOP ? 'S' : 's',
2106 field3 & TRB_ISP ? 'I' : 'i',
2107 field3 & TRB_ENT ? 'E' : 'e',
2108 field3 & TRB_CYCLE ? 'C' : 'c');
2109 break;
2110 case TRB_STATUS:
2111 snprintf(str, size,
2112 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2113 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2114 GET_INTR_TARGET(field2),
2115 xhci_trb_type_string(type),
2116 field3 & TRB_IOC ? 'I' : 'i',
2117 field3 & TRB_CHAIN ? 'C' : 'c',
2118 field3 & TRB_ENT ? 'E' : 'e',
2119 field3 & TRB_CYCLE ? 'C' : 'c');
2120 break;
2121 case TRB_NORMAL:
2122 case TRB_ISOC:
2123 case TRB_EVENT_DATA:
2124 case TRB_TR_NOOP:
2125 snprintf(str, size,
2126 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2127 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2128 GET_INTR_TARGET(field2),
2129 xhci_trb_type_string(type),
2130 field3 & TRB_BEI ? 'B' : 'b',
2131 field3 & TRB_IDT ? 'I' : 'i',
2132 field3 & TRB_IOC ? 'I' : 'i',
2133 field3 & TRB_CHAIN ? 'C' : 'c',
2134 field3 & TRB_NO_SNOOP ? 'S' : 's',
2135 field3 & TRB_ISP ? 'I' : 'i',
2136 field3 & TRB_ENT ? 'E' : 'e',
2137 field3 & TRB_CYCLE ? 'C' : 'c');
2138 break;
2139
2140 case TRB_CMD_NOOP:
2141 case TRB_ENABLE_SLOT:
2142 snprintf(str, size,
2143 "%s: flags %c",
2144 xhci_trb_type_string(type),
2145 field3 & TRB_CYCLE ? 'C' : 'c');
2146 break;
2147 case TRB_DISABLE_SLOT:
2148 case TRB_NEG_BANDWIDTH:
2149 snprintf(str, size,
2150 "%s: slot %d flags %c",
2151 xhci_trb_type_string(type),
2152 TRB_TO_SLOT_ID(field3),
2153 field3 & TRB_CYCLE ? 'C' : 'c');
2154 break;
2155 case TRB_ADDR_DEV:
2156 snprintf(str, size,
2157 "%s: ctx %08x%08x slot %d flags %c:%c",
2158 xhci_trb_type_string(type),
2159 field1, field0,
2160 TRB_TO_SLOT_ID(field3),
2161 field3 & TRB_BSR ? 'B' : 'b',
2162 field3 & TRB_CYCLE ? 'C' : 'c');
2163 break;
2164 case TRB_CONFIG_EP:
2165 snprintf(str, size,
2166 "%s: ctx %08x%08x slot %d flags %c:%c",
2167 xhci_trb_type_string(type),
2168 field1, field0,
2169 TRB_TO_SLOT_ID(field3),
2170 field3 & TRB_DC ? 'D' : 'd',
2171 field3 & TRB_CYCLE ? 'C' : 'c');
2172 break;
2173 case TRB_EVAL_CONTEXT:
2174 snprintf(str, size,
2175 "%s: ctx %08x%08x slot %d flags %c",
2176 xhci_trb_type_string(type),
2177 field1, field0,
2178 TRB_TO_SLOT_ID(field3),
2179 field3 & TRB_CYCLE ? 'C' : 'c');
2180 break;
2181 case TRB_RESET_EP:
2182 snprintf(str, size,
2183 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2184 xhci_trb_type_string(type),
2185 field1, field0,
2186 TRB_TO_SLOT_ID(field3),
2187 /* Macro decrements 1, maybe it shouldn't?!? */
2188 TRB_TO_EP_INDEX(field3) + 1,
2189 field3 & TRB_TSP ? 'T' : 't',
2190 field3 & TRB_CYCLE ? 'C' : 'c');
2191 break;
2192 case TRB_STOP_RING:
2193 snprintf(str, size,
2194 "%s: slot %d sp %d ep %d flags %c",
2195 xhci_trb_type_string(type),
2196 TRB_TO_SLOT_ID(field3),
2197 TRB_TO_SUSPEND_PORT(field3),
2198 /* Macro decrements 1, maybe it shouldn't?!? */
2199 TRB_TO_EP_INDEX(field3) + 1,
2200 field3 & TRB_CYCLE ? 'C' : 'c');
2201 break;
2202 case TRB_SET_DEQ:
2203 snprintf(str, size,
2204 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2205 xhci_trb_type_string(type),
2206 field1, field0,
2207 TRB_TO_STREAM_ID(field2),
2208 TRB_TO_SLOT_ID(field3),
2209 /* Macro decrements 1, maybe it shouldn't?!? */
2210 TRB_TO_EP_INDEX(field3) + 1,
2211 field3 & TRB_CYCLE ? 'C' : 'c');
2212 break;
2213 case TRB_RESET_DEV:
2214 snprintf(str, size,
2215 "%s: slot %d flags %c",
2216 xhci_trb_type_string(type),
2217 TRB_TO_SLOT_ID(field3),
2218 field3 & TRB_CYCLE ? 'C' : 'c');
2219 break;
2220 case TRB_FORCE_EVENT:
2221 snprintf(str, size,
2222 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2223 xhci_trb_type_string(type),
2224 field1, field0,
2225 TRB_TO_VF_INTR_TARGET(field2),
2226 TRB_TO_VF_ID(field3),
2227 field3 & TRB_CYCLE ? 'C' : 'c');
2228 break;
2229 case TRB_SET_LT:
2230 snprintf(str, size,
2231 "%s: belt %d flags %c",
2232 xhci_trb_type_string(type),
2233 TRB_TO_BELT(field3),
2234 field3 & TRB_CYCLE ? 'C' : 'c');
2235 break;
2236 case TRB_GET_BW:
2237 snprintf(str, size,
2238 "%s: ctx %08x%08x slot %d speed %d flags %c",
2239 xhci_trb_type_string(type),
2240 field1, field0,
2241 TRB_TO_SLOT_ID(field3),
2242 TRB_TO_DEV_SPEED(field3),
2243 field3 & TRB_CYCLE ? 'C' : 'c');
2244 break;
2245 case TRB_FORCE_HEADER:
2246 snprintf(str, size,
2247 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2248 xhci_trb_type_string(type),
2249 field2, field1, field0 & 0xffffffe0,
2250 TRB_TO_PACKET_TYPE(field0),
2251 TRB_TO_ROOTHUB_PORT(field3),
2252 field3 & TRB_CYCLE ? 'C' : 'c');
2253 break;
2254 default:
2255 snprintf(str, size,
2256 "type '%s' -> raw %08x %08x %08x %08x",
2257 xhci_trb_type_string(type),
2258 field0, field1, field2, field3);
2259 }
2260
2261 return str;
2262 }
2263
xhci_decode_ctrl_ctx(char * str,unsigned long drop,unsigned long add)2264 static inline const char *xhci_decode_ctrl_ctx(char *str,
2265 unsigned long drop, unsigned long add)
2266 {
2267 unsigned int bit;
2268 int ret = 0;
2269
2270 str[0] = '\0';
2271
2272 if (drop) {
2273 ret = sprintf(str, "Drop:");
2274 for_each_set_bit(bit, &drop, 32)
2275 ret += sprintf(str + ret, " %d%s",
2276 bit / 2,
2277 bit % 2 ? "in":"out");
2278 ret += sprintf(str + ret, ", ");
2279 }
2280
2281 if (add) {
2282 ret += sprintf(str + ret, "Add:%s%s",
2283 (add & SLOT_FLAG) ? " slot":"",
2284 (add & EP0_FLAG) ? " ep0":"");
2285 add &= ~(SLOT_FLAG | EP0_FLAG);
2286 for_each_set_bit(bit, &add, 32)
2287 ret += sprintf(str + ret, " %d%s",
2288 bit / 2,
2289 bit % 2 ? "in":"out");
2290 }
2291 return str;
2292 }
2293
xhci_decode_slot_context(char * str,u32 info,u32 info2,u32 tt_info,u32 state)2294 static inline const char *xhci_decode_slot_context(char *str,
2295 u32 info, u32 info2, u32 tt_info, u32 state)
2296 {
2297 u32 speed;
2298 u32 hub;
2299 u32 mtt;
2300 int ret = 0;
2301
2302 speed = info & DEV_SPEED;
2303 hub = info & DEV_HUB;
2304 mtt = info & DEV_MTT;
2305
2306 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2307 info & ROUTE_STRING_MASK,
2308 ({ char *s;
2309 switch (speed) {
2310 case SLOT_SPEED_FS:
2311 s = "full-speed";
2312 break;
2313 case SLOT_SPEED_LS:
2314 s = "low-speed";
2315 break;
2316 case SLOT_SPEED_HS:
2317 s = "high-speed";
2318 break;
2319 case SLOT_SPEED_SS:
2320 s = "super-speed";
2321 break;
2322 case SLOT_SPEED_SSP:
2323 s = "super-speed plus";
2324 break;
2325 default:
2326 s = "UNKNOWN speed";
2327 } s; }),
2328 mtt ? " multi-TT" : "",
2329 hub ? " Hub" : "",
2330 (info & LAST_CTX_MASK) >> 27,
2331 info2 & MAX_EXIT,
2332 DEVINFO_TO_ROOT_HUB_PORT(info2),
2333 DEVINFO_TO_MAX_PORTS(info2));
2334
2335 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2336 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2337 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2338 state & DEV_ADDR_MASK,
2339 xhci_slot_state_string(GET_SLOT_STATE(state)));
2340
2341 return str;
2342 }
2343
2344
xhci_portsc_link_state_string(u32 portsc)2345 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2346 {
2347 switch (portsc & PORT_PLS_MASK) {
2348 case XDEV_U0:
2349 return "U0";
2350 case XDEV_U1:
2351 return "U1";
2352 case XDEV_U2:
2353 return "U2";
2354 case XDEV_U3:
2355 return "U3";
2356 case XDEV_DISABLED:
2357 return "Disabled";
2358 case XDEV_RXDETECT:
2359 return "RxDetect";
2360 case XDEV_INACTIVE:
2361 return "Inactive";
2362 case XDEV_POLLING:
2363 return "Polling";
2364 case XDEV_RECOVERY:
2365 return "Recovery";
2366 case XDEV_HOT_RESET:
2367 return "Hot Reset";
2368 case XDEV_COMP_MODE:
2369 return "Compliance mode";
2370 case XDEV_TEST_MODE:
2371 return "Test mode";
2372 case XDEV_RESUME:
2373 return "Resume";
2374 default:
2375 break;
2376 }
2377 return "Unknown";
2378 }
2379
xhci_decode_portsc(char * str,u32 portsc)2380 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2381 {
2382 int ret;
2383
2384 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2385 portsc & PORT_POWER ? "Powered" : "Powered-off",
2386 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2387 portsc & PORT_PE ? "Enabled" : "Disabled",
2388 xhci_portsc_link_state_string(portsc),
2389 DEV_PORT_SPEED(portsc));
2390
2391 if (portsc & PORT_OC)
2392 ret += sprintf(str + ret, "OverCurrent ");
2393 if (portsc & PORT_RESET)
2394 ret += sprintf(str + ret, "In-Reset ");
2395
2396 ret += sprintf(str + ret, "Change: ");
2397 if (portsc & PORT_CSC)
2398 ret += sprintf(str + ret, "CSC ");
2399 if (portsc & PORT_PEC)
2400 ret += sprintf(str + ret, "PEC ");
2401 if (portsc & PORT_WRC)
2402 ret += sprintf(str + ret, "WRC ");
2403 if (portsc & PORT_OCC)
2404 ret += sprintf(str + ret, "OCC ");
2405 if (portsc & PORT_RC)
2406 ret += sprintf(str + ret, "PRC ");
2407 if (portsc & PORT_PLC)
2408 ret += sprintf(str + ret, "PLC ");
2409 if (portsc & PORT_CEC)
2410 ret += sprintf(str + ret, "CEC ");
2411 if (portsc & PORT_CAS)
2412 ret += sprintf(str + ret, "CAS ");
2413
2414 ret += sprintf(str + ret, "Wake: ");
2415 if (portsc & PORT_WKCONN_E)
2416 ret += sprintf(str + ret, "WCE ");
2417 if (portsc & PORT_WKDISC_E)
2418 ret += sprintf(str + ret, "WDE ");
2419 if (portsc & PORT_WKOC_E)
2420 ret += sprintf(str + ret, "WOE ");
2421
2422 return str;
2423 }
2424
xhci_decode_usbsts(char * str,u32 usbsts)2425 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2426 {
2427 int ret = 0;
2428
2429 ret = sprintf(str, " 0x%08x", usbsts);
2430
2431 if (usbsts == ~(u32)0)
2432 return str;
2433
2434 if (usbsts & STS_HALT)
2435 ret += sprintf(str + ret, " HCHalted");
2436 if (usbsts & STS_FATAL)
2437 ret += sprintf(str + ret, " HSE");
2438 if (usbsts & STS_EINT)
2439 ret += sprintf(str + ret, " EINT");
2440 if (usbsts & STS_PORT)
2441 ret += sprintf(str + ret, " PCD");
2442 if (usbsts & STS_SAVE)
2443 ret += sprintf(str + ret, " SSS");
2444 if (usbsts & STS_RESTORE)
2445 ret += sprintf(str + ret, " RSS");
2446 if (usbsts & STS_SRE)
2447 ret += sprintf(str + ret, " SRE");
2448 if (usbsts & STS_CNR)
2449 ret += sprintf(str + ret, " CNR");
2450 if (usbsts & STS_HCE)
2451 ret += sprintf(str + ret, " HCE");
2452
2453 return str;
2454 }
2455
xhci_decode_doorbell(char * str,u32 slot,u32 doorbell)2456 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2457 {
2458 u8 ep;
2459 u16 stream;
2460 int ret;
2461
2462 ep = (doorbell & 0xff);
2463 stream = doorbell >> 16;
2464
2465 if (slot == 0) {
2466 sprintf(str, "Command Ring %d", doorbell);
2467 return str;
2468 }
2469 ret = sprintf(str, "Slot %d ", slot);
2470 if (ep > 0 && ep < 32)
2471 ret = sprintf(str + ret, "ep%d%s",
2472 ep / 2,
2473 ep % 2 ? "in" : "out");
2474 else if (ep == 0 || ep < 248)
2475 ret = sprintf(str + ret, "Reserved %d", ep);
2476 else
2477 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2478 if (stream)
2479 ret = sprintf(str + ret, " Stream %d", stream);
2480
2481 return str;
2482 }
2483
xhci_ep_state_string(u8 state)2484 static inline const char *xhci_ep_state_string(u8 state)
2485 {
2486 switch (state) {
2487 case EP_STATE_DISABLED:
2488 return "disabled";
2489 case EP_STATE_RUNNING:
2490 return "running";
2491 case EP_STATE_HALTED:
2492 return "halted";
2493 case EP_STATE_STOPPED:
2494 return "stopped";
2495 case EP_STATE_ERROR:
2496 return "error";
2497 default:
2498 return "INVALID";
2499 }
2500 }
2501
xhci_ep_type_string(u8 type)2502 static inline const char *xhci_ep_type_string(u8 type)
2503 {
2504 switch (type) {
2505 case ISOC_OUT_EP:
2506 return "Isoc OUT";
2507 case BULK_OUT_EP:
2508 return "Bulk OUT";
2509 case INT_OUT_EP:
2510 return "Int OUT";
2511 case CTRL_EP:
2512 return "Ctrl";
2513 case ISOC_IN_EP:
2514 return "Isoc IN";
2515 case BULK_IN_EP:
2516 return "Bulk IN";
2517 case INT_IN_EP:
2518 return "Int IN";
2519 default:
2520 return "INVALID";
2521 }
2522 }
2523
xhci_decode_ep_context(char * str,u32 info,u32 info2,u64 deq,u32 tx_info)2524 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2525 u32 info2, u64 deq, u32 tx_info)
2526 {
2527 int ret;
2528
2529 u32 esit;
2530 u16 maxp;
2531 u16 avg;
2532
2533 u8 max_pstr;
2534 u8 ep_state;
2535 u8 interval;
2536 u8 ep_type;
2537 u8 burst;
2538 u8 cerr;
2539 u8 mult;
2540
2541 bool lsa;
2542 bool hid;
2543
2544 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2545 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2546
2547 ep_state = info & EP_STATE_MASK;
2548 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2549 interval = CTX_TO_EP_INTERVAL(info);
2550 mult = CTX_TO_EP_MULT(info) + 1;
2551 lsa = !!(info & EP_HAS_LSA);
2552
2553 cerr = (info2 & (3 << 1)) >> 1;
2554 ep_type = CTX_TO_EP_TYPE(info2);
2555 hid = !!(info2 & (1 << 7));
2556 burst = CTX_TO_MAX_BURST(info2);
2557 maxp = MAX_PACKET_DECODED(info2);
2558
2559 avg = EP_AVG_TRB_LENGTH(tx_info);
2560
2561 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2562 xhci_ep_state_string(ep_state), mult,
2563 max_pstr, lsa ? "LSA " : "");
2564
2565 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2566 (1 << interval) * 125, esit, cerr);
2567
2568 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2569 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2570 burst, maxp, deq);
2571
2572 ret += sprintf(str + ret, "avg trb len %d", avg);
2573
2574 return str;
2575 }
2576
2577 #endif /* __LINUX_XHCI_HCD_H */
2578