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Searched defs:TCG_TARGET_REG_BITS (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/tcg/mips/
H A Dtcg-target-reg-bits.h11 # define TCG_TARGET_REG_BITS 32 macro
13 # define TCG_TARGET_REG_BITS 64 macro
/openbmc/qemu/tcg/tci/
H A Dtcg-target-reg-bits.h11 # define TCG_TARGET_REG_BITS 32 macro
13 # define TCG_TARGET_REG_BITS 64 macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target-reg-bits.h11 # define TCG_TARGET_REG_BITS 64 macro
13 # define TCG_TARGET_REG_BITS 32 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-reg-bits.h11 # define TCG_TARGET_REG_BITS 64 macro
13 # define TCG_TARGET_REG_BITS 32 macro
/openbmc/qemu/tcg/arm/
H A Dtcg-target-reg-bits.h10 #define TCG_TARGET_REG_BITS 32 macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-reg-bits.h16 # define TCG_TARGET_REG_BITS 64 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target-reg-bits.h10 #define TCG_TARGET_REG_BITS 64 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target-reg-bits.h12 # define TCG_TARGET_REG_BITS 64 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-reg-bits.h10 #define TCG_TARGET_REG_BITS 64 macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-reg-bits.h17 #define TCG_TARGET_REG_BITS 64 macro