1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef RISCV_TCG_TARGET_H 26 #define RISCV_TCG_TARGET_H 27 28 #include "host/cpuinfo.h" 29 30 #define TCG_TARGET_INSN_UNIT_SIZE 4 31 #define TCG_TARGET_NB_REGS 32 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 33 34 typedef enum { 35 TCG_REG_ZERO, 36 TCG_REG_RA, 37 TCG_REG_SP, 38 TCG_REG_GP, 39 TCG_REG_TP, 40 TCG_REG_T0, 41 TCG_REG_T1, 42 TCG_REG_T2, 43 TCG_REG_S0, 44 TCG_REG_S1, 45 TCG_REG_A0, 46 TCG_REG_A1, 47 TCG_REG_A2, 48 TCG_REG_A3, 49 TCG_REG_A4, 50 TCG_REG_A5, 51 TCG_REG_A6, 52 TCG_REG_A7, 53 TCG_REG_S2, 54 TCG_REG_S3, 55 TCG_REG_S4, 56 TCG_REG_S5, 57 TCG_REG_S6, 58 TCG_REG_S7, 59 TCG_REG_S8, 60 TCG_REG_S9, 61 TCG_REG_S10, 62 TCG_REG_S11, 63 TCG_REG_T3, 64 TCG_REG_T4, 65 TCG_REG_T5, 66 TCG_REG_T6, 67 68 /* aliases */ 69 TCG_AREG0 = TCG_REG_S0, 70 TCG_GUEST_BASE_REG = TCG_REG_S1, 71 TCG_REG_TMP0 = TCG_REG_T6, 72 TCG_REG_TMP1 = TCG_REG_T5, 73 TCG_REG_TMP2 = TCG_REG_T4, 74 } TCGReg; 75 76 /* used for function call generation */ 77 #define TCG_REG_CALL_STACK TCG_REG_SP 78 #define TCG_TARGET_STACK_ALIGN 16 79 #define TCG_TARGET_CALL_STACK_OFFSET 0 80 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 81 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 82 #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 83 #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 84 85 /* optional instructions */ 86 #define TCG_TARGET_HAS_negsetcond_i32 1 87 #define TCG_TARGET_HAS_div_i32 1 88 #define TCG_TARGET_HAS_rem_i32 1 89 #define TCG_TARGET_HAS_div2_i32 0 90 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) 91 #define TCG_TARGET_HAS_deposit_i32 0 92 #define TCG_TARGET_HAS_extract_i32 0 93 #define TCG_TARGET_HAS_sextract_i32 0 94 #define TCG_TARGET_HAS_extract2_i32 0 95 #define TCG_TARGET_HAS_add2_i32 1 96 #define TCG_TARGET_HAS_sub2_i32 1 97 #define TCG_TARGET_HAS_mulu2_i32 0 98 #define TCG_TARGET_HAS_muls2_i32 0 99 #define TCG_TARGET_HAS_muluh_i32 0 100 #define TCG_TARGET_HAS_mulsh_i32 0 101 #define TCG_TARGET_HAS_ext8s_i32 1 102 #define TCG_TARGET_HAS_ext16s_i32 1 103 #define TCG_TARGET_HAS_ext8u_i32 1 104 #define TCG_TARGET_HAS_ext16u_i32 1 105 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) 106 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) 107 #define TCG_TARGET_HAS_not_i32 1 108 #define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB) 109 #define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB) 110 #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) 111 #define TCG_TARGET_HAS_nand_i32 0 112 #define TCG_TARGET_HAS_nor_i32 0 113 #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) 114 #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) 115 #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) 116 #define TCG_TARGET_HAS_brcond2 1 117 #define TCG_TARGET_HAS_setcond2 1 118 #define TCG_TARGET_HAS_qemu_st8_i32 0 119 120 #define TCG_TARGET_HAS_negsetcond_i64 1 121 #define TCG_TARGET_HAS_div_i64 1 122 #define TCG_TARGET_HAS_rem_i64 1 123 #define TCG_TARGET_HAS_div2_i64 0 124 #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) 125 #define TCG_TARGET_HAS_deposit_i64 0 126 #define TCG_TARGET_HAS_extract_i64 0 127 #define TCG_TARGET_HAS_sextract_i64 0 128 #define TCG_TARGET_HAS_extract2_i64 0 129 #define TCG_TARGET_HAS_extr_i64_i32 1 130 #define TCG_TARGET_HAS_ext8s_i64 1 131 #define TCG_TARGET_HAS_ext16s_i64 1 132 #define TCG_TARGET_HAS_ext32s_i64 1 133 #define TCG_TARGET_HAS_ext8u_i64 1 134 #define TCG_TARGET_HAS_ext16u_i64 1 135 #define TCG_TARGET_HAS_ext32u_i64 1 136 #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) 137 #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) 138 #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) 139 #define TCG_TARGET_HAS_not_i64 1 140 #define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB) 141 #define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB) 142 #define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) 143 #define TCG_TARGET_HAS_nand_i64 0 144 #define TCG_TARGET_HAS_nor_i64 0 145 #define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) 146 #define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) 147 #define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) 148 #define TCG_TARGET_HAS_add2_i64 1 149 #define TCG_TARGET_HAS_sub2_i64 1 150 #define TCG_TARGET_HAS_mulu2_i64 0 151 #define TCG_TARGET_HAS_muls2_i64 0 152 #define TCG_TARGET_HAS_muluh_i64 1 153 #define TCG_TARGET_HAS_mulsh_i64 1 154 155 #define TCG_TARGET_HAS_qemu_ldst_i128 0 156 157 #define TCG_TARGET_HAS_tst 0 158 159 #define TCG_TARGET_DEFAULT_MO (0) 160 161 #define TCG_TARGET_NEED_LDST_LABELS 162 #define TCG_TARGET_NEED_POOL_LABELS 163 164 #endif 165