xref: /openbmc/qemu/tcg/sparc64/tcg-target.h (revision b9ddaf56)
1 /*
2  * Tiny Code Generator for QEMU
3  *
4  * Copyright (c) 2008 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef SPARC_TCG_TARGET_H
26 #define SPARC_TCG_TARGET_H
27 
28 #define TCG_TARGET_INSN_UNIT_SIZE 4
29 #define TCG_TARGET_NB_REGS 32
30 #define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
31 
32 typedef enum {
33     TCG_REG_G0 = 0,
34     TCG_REG_G1,
35     TCG_REG_G2,
36     TCG_REG_G3,
37     TCG_REG_G4,
38     TCG_REG_G5,
39     TCG_REG_G6,
40     TCG_REG_G7,
41     TCG_REG_O0,
42     TCG_REG_O1,
43     TCG_REG_O2,
44     TCG_REG_O3,
45     TCG_REG_O4,
46     TCG_REG_O5,
47     TCG_REG_O6,
48     TCG_REG_O7,
49     TCG_REG_L0,
50     TCG_REG_L1,
51     TCG_REG_L2,
52     TCG_REG_L3,
53     TCG_REG_L4,
54     TCG_REG_L5,
55     TCG_REG_L6,
56     TCG_REG_L7,
57     TCG_REG_I0,
58     TCG_REG_I1,
59     TCG_REG_I2,
60     TCG_REG_I3,
61     TCG_REG_I4,
62     TCG_REG_I5,
63     TCG_REG_I6,
64     TCG_REG_I7,
65 } TCGReg;
66 
67 /* used for function call generation */
68 #define TCG_REG_CALL_STACK TCG_REG_O6
69 
70 #define TCG_TARGET_STACK_BIAS           2047
71 #define TCG_TARGET_STACK_ALIGN          16
72 #define TCG_TARGET_CALL_STACK_OFFSET    (128 + 6*8 + TCG_TARGET_STACK_BIAS)
73 #define TCG_TARGET_CALL_ARG_I32         TCG_CALL_ARG_EXTEND
74 #define TCG_TARGET_CALL_ARG_I64         TCG_CALL_ARG_NORMAL
75 #define TCG_TARGET_CALL_ARG_I128        TCG_CALL_ARG_NORMAL
76 #define TCG_TARGET_CALL_RET_I128        TCG_CALL_RET_NORMAL
77 
78 #if defined(__VIS__) && __VIS__ >= 0x300
79 #define use_vis3_instructions  1
80 #else
81 extern bool use_vis3_instructions;
82 #endif
83 
84 /* optional instructions */
85 #define TCG_TARGET_HAS_div_i32		1
86 #define TCG_TARGET_HAS_rem_i32		0
87 #define TCG_TARGET_HAS_rot_i32          0
88 #define TCG_TARGET_HAS_ext8s_i32        0
89 #define TCG_TARGET_HAS_ext16s_i32       0
90 #define TCG_TARGET_HAS_ext8u_i32        0
91 #define TCG_TARGET_HAS_ext16u_i32       0
92 #define TCG_TARGET_HAS_bswap16_i32      0
93 #define TCG_TARGET_HAS_bswap32_i32      0
94 #define TCG_TARGET_HAS_not_i32          1
95 #define TCG_TARGET_HAS_andc_i32         1
96 #define TCG_TARGET_HAS_orc_i32          1
97 #define TCG_TARGET_HAS_eqv_i32          0
98 #define TCG_TARGET_HAS_nand_i32         0
99 #define TCG_TARGET_HAS_nor_i32          0
100 #define TCG_TARGET_HAS_clz_i32          0
101 #define TCG_TARGET_HAS_ctz_i32          0
102 #define TCG_TARGET_HAS_ctpop_i32        0
103 #define TCG_TARGET_HAS_deposit_i32      0
104 #define TCG_TARGET_HAS_extract_i32      0
105 #define TCG_TARGET_HAS_sextract_i32     0
106 #define TCG_TARGET_HAS_extract2_i32     0
107 #define TCG_TARGET_HAS_negsetcond_i32   1
108 #define TCG_TARGET_HAS_add2_i32         1
109 #define TCG_TARGET_HAS_sub2_i32         1
110 #define TCG_TARGET_HAS_mulu2_i32        1
111 #define TCG_TARGET_HAS_muls2_i32        1
112 #define TCG_TARGET_HAS_muluh_i32        0
113 #define TCG_TARGET_HAS_mulsh_i32        0
114 #define TCG_TARGET_HAS_qemu_st8_i32     0
115 
116 #define TCG_TARGET_HAS_extr_i64_i32     0
117 #define TCG_TARGET_HAS_div_i64          1
118 #define TCG_TARGET_HAS_rem_i64          0
119 #define TCG_TARGET_HAS_rot_i64          0
120 #define TCG_TARGET_HAS_ext8s_i64        0
121 #define TCG_TARGET_HAS_ext16s_i64       0
122 #define TCG_TARGET_HAS_ext32s_i64       1
123 #define TCG_TARGET_HAS_ext8u_i64        0
124 #define TCG_TARGET_HAS_ext16u_i64       0
125 #define TCG_TARGET_HAS_ext32u_i64       1
126 #define TCG_TARGET_HAS_bswap16_i64      0
127 #define TCG_TARGET_HAS_bswap32_i64      0
128 #define TCG_TARGET_HAS_bswap64_i64      0
129 #define TCG_TARGET_HAS_not_i64          1
130 #define TCG_TARGET_HAS_andc_i64         1
131 #define TCG_TARGET_HAS_orc_i64          1
132 #define TCG_TARGET_HAS_eqv_i64          0
133 #define TCG_TARGET_HAS_nand_i64         0
134 #define TCG_TARGET_HAS_nor_i64          0
135 #define TCG_TARGET_HAS_clz_i64          0
136 #define TCG_TARGET_HAS_ctz_i64          0
137 #define TCG_TARGET_HAS_ctpop_i64        0
138 #define TCG_TARGET_HAS_deposit_i64      0
139 #define TCG_TARGET_HAS_extract_i64      0
140 #define TCG_TARGET_HAS_sextract_i64     0
141 #define TCG_TARGET_HAS_extract2_i64     0
142 #define TCG_TARGET_HAS_negsetcond_i64   1
143 #define TCG_TARGET_HAS_add2_i64         1
144 #define TCG_TARGET_HAS_sub2_i64         1
145 #define TCG_TARGET_HAS_mulu2_i64        0
146 #define TCG_TARGET_HAS_muls2_i64        0
147 #define TCG_TARGET_HAS_muluh_i64        use_vis3_instructions
148 #define TCG_TARGET_HAS_mulsh_i64        0
149 
150 #define TCG_TARGET_HAS_qemu_ldst_i128   0
151 
152 #define TCG_TARGET_HAS_tst              1
153 
154 #define TCG_AREG0 TCG_REG_I0
155 
156 #define TCG_TARGET_DEFAULT_MO (0)
157 #define TCG_TARGET_NEED_LDST_LABELS
158 #define TCG_TARGET_NEED_POOL_LABELS
159 
160 #endif
161